fix(riscv_trace): protect shared RCC register access with PERIPH_RCC_ATOMIC

riscv_trace_ll_enable_bus_clock and riscv_trace_ll_reset_register operate
on shared HP_SYS_CLKRST registers and were called concurrently from both
cores during SECONDARY init, creating RMW race conditions.

Move the clock/reset logic out of the HAL layer into
esp_riscv_trace_early_init, protected by PERIPH_RCC_ATOMIC() spinlock.
Wrap the LL functions with macros that enforce the caller must be inside
a PERIPH_RCC_ATOMIC() critical section at compile time.

components/esp_riscv_trace/test_apps/basic/sdkconfig.defaults

@@ -1,3 +1,4 @@
+# CONFIG_ESP_TASK_WDT_INIT is not set
 CONFIG_ESP_RISCV_TRACE_ENABLE=y
 CONFIG_ESP_RISCV_TRACE_RESYNC_MODE_PACKET=y
 CONFIG_ESP_RISCV_TRACE_RESYNC_THRESHOLD=32