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fix(driver_spi): added bit trans length check for master driver

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Closes https://github.com/espressif/esp-idf/issues/16049

Closes https://github.com/espressif/esp-idf/issues/17725
This commit is contained in:
wanckl
2026-01-21 19:02:09 +08:00
committed by Wan Lei
parent 89d3051b53
commit 488c933500
16 changed files with 169 additions and 18 deletions
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components/esp_hal_gpspi/esp32/include/hal/spi_ll.h
+2
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@@ -41,6 +41,8 @@ extern "C" {
#define SPI_LL_DMA_CHANNEL_NUM (2)
#define SPI_LL_DMA_MAX_BIT_LEN (1 << 24) //reg len: 24 bits
#define SPI_LL_CPU_MAX_BIT_LEN (16 * 32) //Fifo len: 16 words
#define SPI_LL_TX_MINI_EXTRA_BITS 1 //Minimum length of TX non byte aligned data in bits
#define SPI_LL_RX_MINI_EXTRA_BITS 1 //Minimum length of RX non byte aligned data in bits
#define SPI_LL_MAX_PRE_DIV_NUM (8192)
#define SPI_LL_SUPPORT_CLK_AS_CS 1 //Output clock on CS line if CS is active
#define SPI_LL_MOSI_FREE_LEVEL 0 //Default level after bus initialized