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fix(mspi): fixed possible boot failure in some builds when psram is enabled

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A typical scenario is: when XIP on PSRAM enabled, compiler optimization level is Os. Under certain binary layout, boot hangs and backtrace points to `esp_sleep_config_gpio_isolate`.

The root cause is that, during PSRAM initialization, it calls esp_gpio_reserve, which happens to place before the reported function. However, after call, there is no barrier before the clock adjustment in `mspi_timing_enter_low_speed_mode`. The clock gets changed when the cache is still fetching data, resulting in the corrupted data in the end of the cache line.

This commits add spi_flash_disable_cache as a barrier to make sure the cache transactions is finished before the clock switch.
This commit is contained in:
Xiao Xufeng
2026-05-15 17:31:37 +08:00
parent 11fa0fe619
commit 475ec39cb4
8 changed files with 105 additions and 12 deletions
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components/esp_tee/subproject/main/core/esp_secure_services_iram.c
+10
View File
@@ -552,6 +552,16 @@ void _ss_mspi_timing_enter_high_speed_mode(bool control_spi1)
mspi_timing_enter_high_speed_mode(control_spi1);
}
void _ss_mspi_timing_enter_low_speed_early(void)
{
mspi_timing_enter_low_speed_early();
}
void _ss_mspi_timing_enter_high_speed_early(void)
{
mspi_timing_enter_high_speed_early();
}
void _ss_mspi_timing_change_speed_mode_cache_safe(bool switch_down)
{
mspi_timing_change_speed_mode_cache_safe(switch_down);
components/esp_tee/subproject/main/ld/esp32c5/esp_tee.ld.in
+2
View File
@@ -36,6 +36,8 @@ PROVIDE ( esp_tee_app_config = SRAM_REE_SEG_START + 0x2b0 );
PROVIDE ( GDMA = 0x60080000 );
/* SPI Flash functions required from the ROM (refer esp32c5.rom.spiflash.ld) */
PROVIDE ( rom_spi_flash_disable_cache = 0x40000204 );
PROVIDE ( rom_spi_flash_restore_cache = 0x40000208 );
PROVIDE ( spi_flash_check_and_flush_cache = 0x40000230 );
PROVIDE ( spi_flash_chip_generic_config_host_io_mode = 0x400002d4 );
PROVIDE ( memspi_host_flush_cache = 0x40000318 );