fix(mspi): fixed possible boot failure in some builds when psram is enabled

A typical scenario is: when XIP on PSRAM enabled, compiler optimization level is Os. Under certain binary layout, boot hangs and backtrace points to `esp_sleep_config_gpio_isolate`.

The root cause is that, during PSRAM initialization, it calls esp_gpio_reserve, which happens to place before the reported function. However, after call, there is no barrier before the clock adjustment in `mspi_timing_enter_low_speed_mode`. The clock gets changed when the cache is still fetching data, resulting in the corrupted data in the end of the cache line.

This commits add spi_flash_disable_cache as a barrier to make sure the cache transactions is finished before the clock switch.

components/esp_tee/scripts/esp32c5/sec_srv_tbl_default.yml

@@ -120,6 +120,14 @@ secure_services:
         type: IDF
         function: spi_timing_get_flash_timing_param
         args: 1
+      - id: 29
+        type: IDF
+        function: mspi_timing_enter_low_speed_early
+        args: 0
+      - id: 10
+        type: IDF
+        function: mspi_timing_enter_high_speed_early
+        args: 0
   # ID: 30-53 (24) - Interrupt Handling
   - family: interrupt_handling
     entries:

components/esp_tee/src/esp_secure_service_wrapper.c

@@ -491,6 +491,16 @@ void IRAM_ATTR __wrap_mspi_timing_enter_high_speed_mode(bool control_spi1)
     esp_tee_service_call(2, SS_MSPI_TIMING_ENTER_HIGH_SPEED_MODE, control_spi1);
 }
 
+void IRAM_ATTR __wrap_mspi_timing_enter_low_speed_early(void)
+{
+    esp_tee_service_call(1, SS_MSPI_TIMING_ENTER_LOW_SPEED_EARLY);
+}
+
+void IRAM_ATTR __wrap_mspi_timing_enter_high_speed_early(void)
+{
+    esp_tee_service_call(1, SS_MSPI_TIMING_ENTER_HIGH_SPEED_EARLY);
+}
+
 void IRAM_ATTR __wrap_mspi_timing_change_speed_mode_cache_safe(bool switch_down)
 {
     esp_tee_service_call(2, SS_MSPI_TIMING_CHANGE_SPEED_MODE_CACHE_SAFE, switch_down);

components/esp_tee/subproject/main/core/esp_secure_services_iram.c

@@ -552,6 +552,16 @@ void _ss_mspi_timing_enter_high_speed_mode(bool control_spi1)
     mspi_timing_enter_high_speed_mode(control_spi1);
 }
 
+void _ss_mspi_timing_enter_low_speed_early(void)
+{
+    mspi_timing_enter_low_speed_early();
+}
+
+void _ss_mspi_timing_enter_high_speed_early(void)
+{
+    mspi_timing_enter_high_speed_early();
+}
+
 void _ss_mspi_timing_change_speed_mode_cache_safe(bool switch_down)
 {
     mspi_timing_change_speed_mode_cache_safe(switch_down);

components/esp_tee/subproject/main/ld/esp32c5/esp_tee.ld.in

@@ -36,6 +36,8 @@ PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x2b0 );
 PROVIDE ( GDMA                      = 0x60080000 );
 
 /* SPI Flash functions required from the ROM (refer esp32c5.rom.spiflash.ld) */
+PROVIDE ( rom_spi_flash_disable_cache                = 0x40000204 );
+PROVIDE ( rom_spi_flash_restore_cache                = 0x40000208 );
 PROVIDE ( spi_flash_check_and_flush_cache            = 0x40000230 );
 PROVIDE ( spi_flash_chip_generic_config_host_io_mode = 0x400002d4 );
 PROVIDE ( memspi_host_flush_cache                    = 0x40000318 );