diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild
index f3cb448e254..3f9b1144ec4 100644
--- a/components/bootloader/Kconfig.projbuild
+++ b/components/bootloader/Kconfig.projbuild
@@ -41,8 +41,7 @@ menu "Bootloader config"
 
     config BOOTLOADER_CPU_CLK_FREQ_MHZ
         int
-        default 48 if IDF_TARGET_ESP32H21
-        default 64 if IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32H4
+        default 64 if IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32H4 || IDF_TARGET_ESP32H21
         default 90 if IDF_TARGET_ESP32P4 && ESP32P4_SELECTS_REV_LESS_V3
         default 100 if IDF_TARGET_ESP32P4 && !ESP32P4_SELECTS_REV_LESS_V3
         default 80
diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h21.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h21.c
index c52086c38e4..264e78d1501 100644
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h21.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h21.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -82,11 +82,13 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
 
 static void IRAM_ATTR bootloader_flash_clock_init(void)
 {
-    // // To raise the MSPI clock to 64MHz, needs to enable the 64MHz clock source, which is XTAL_X2_CLK
-    // // (FPGA image fixed MSPI0/1 clock to 64MHz)
-    // clk_ll_xtal_x2_enable();
-    // _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F64M);
-    _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F48M);
+    // To raise the MSPI clock to 64MHz, needs to enable the 64MHz clock source, which is XTAL_X2_CLK
+    // (FPGA image fixed MSPI0/1 clock to 64MHz)
+    clk_ll_xtal_x2_enable();
+    _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_REF_F64M);
+    // Note: MSPI clock source cannot be set to 48MHz in bootloader
+    //       48MHz is derived from SPLL, and SPLL is not ready to be used in bootloader for H21
+    //       (calibration not done since bootloader CPU clock source is also set to 64MHz, which does not rely on SPLL)
 }
 
 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
diff --git a/components/esp_hal_mspi/esp32h21/include/hal/mspi_ll.h b/components/esp_hal_mspi/esp32h21/include/hal/mspi_ll.h
index 0060a2324b8..1f83b4c3d4d 100644
--- a/components/esp_hal_mspi/esp32h21/include/hal/mspi_ll.h
+++ b/components/esp_hal_mspi/esp32h21/include/hal/mspi_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -54,9 +54,9 @@ static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_perip
     case FLASH_CLK_SRC_RC_FAST:
         PCR.mspi_conf.mspi_clk_sel = 1;
         break;
-    // case FLASH_CLK_SRC_PLL_F64M:
-    //     PCR.mspi_conf.mspi_clk_sel = 2;
-    //     break;
+    case FLASH_CLK_SRC_REF_F64M:
+        PCR.mspi_conf.mspi_clk_sel = 2;
+        break;
     case FLASH_CLK_SRC_PLL_F48M:
         PCR.mspi_conf.mspi_clk_sel = 3;
         break;
diff --git a/components/esp_hw_support/port/esp32h21/esp_clk_tree.c b/components/esp_hw_support/port/esp32h21/esp_clk_tree.c
index 98f65e7b5e7..7a4e0601ded 100644
--- a/components/esp_hw_support/port/esp32h21/esp_clk_tree.c
+++ b/components/esp_hw_support/port/esp32h21/esp_clk_tree.c
@@ -61,14 +61,22 @@ uint32_t *freq_value)
 }
 
 static int16_t s_xtal_x2_ref_cnt = 0;
+static int16_t s_bbpll_ref_cnt = 0;
 
 void esp_clk_tree_initialize(void)
 {
+    // Power
     // In bootloader, flash clock source will always be switched to use XTAL_X2 clock
-    // s_xtal_x2_ref_cnt++;
-    if (clk_ll_cpu_get_src() == SOC_CPU_CLK_SRC_XTAL_X2) {
+    s_xtal_x2_ref_cnt++;
+    soc_cpu_clk_src_t cpu_clk_src_btld = clk_ll_cpu_get_src();
+    if (cpu_clk_src_btld == SOC_CPU_CLK_SRC_XTAL_X2) {
         s_xtal_x2_ref_cnt++;
+    } else if (cpu_clk_src_btld == SOC_CPU_CLK_SRC_PLL) {
+        s_bbpll_ref_cnt++;
     }
+
+    // Gating
+    // PLL_F64M ++ for MSPI
 }
 
 bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit)
@@ -76,6 +84,8 @@ bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit)
     switch (clk_circuit) {
     case SOC_ROOT_CIRCUIT_CLK_XTAL_X2:
         return s_xtal_x2_ref_cnt > 0;
+    case SOC_ROOT_CIRCUIT_CLK_BBPLL:
+        return s_bbpll_ref_cnt > 0;
     default:
         break;
     }
@@ -84,6 +94,7 @@ bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit)
 
 bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable)
 {
+    bool toggled = false;
     switch (clk_circuit) {
     case SOC_ROOT_CIRCUIT_CLK_XTAL_X2:
         if (enable) {
@@ -94,27 +105,54 @@ bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable)
 
         if (s_xtal_x2_ref_cnt == 1) {
             clk_ll_xtal_x2_enable();
+            toggled = true;
         } else if (s_xtal_x2_ref_cnt == 0) {
             clk_ll_xtal_x2_disable();
+            toggled = true;
         }
 
         assert(s_xtal_x2_ref_cnt >= 0);
         break;
+    case SOC_ROOT_CIRCUIT_CLK_BBPLL:
+        if (enable) {
+            s_bbpll_ref_cnt++;
+        } else {
+            s_bbpll_ref_cnt--;
+        }
+
+        // Note that a calibration is usually needed after enabling BBPLL
+        if (s_bbpll_ref_cnt == 1) {
+            clk_ll_bbpll_enable();
+            toggled = true;
+        } else if (s_bbpll_ref_cnt == 0) {
+            clk_ll_bbpll_disable();
+            toggled = true;
+        }
+
+        assert(s_bbpll_ref_cnt >= 0);
+        break;
     default:
         break;
     }
-    return false; // TODO: PM-653
+    return toggled; // TODO: PM-653
 }
 
 esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
 {
-    switch (clk_src) {
-    case SOC_MOD_CLK_XTAL_X2_F64M:
-        // later, here should handle ref count for XTAL_X2_F64M clock gating, then also handle XTAL_X2 circuit enable/disable
-        esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, enable);
-        break;
-    default:
-        break;
+    PERIPH_RCC_ATOMIC() {
+        switch (clk_src) {
+        case SOC_MOD_CLK_XTAL_X2_F64M:
+            // later, here should handle ref count for XTAL_X2_F64M clock gating, then also handle XTAL_X2 circuit enable/disable
+            esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, enable);
+            break;
+        // case SOC_MOD_CLK_PLL_FxxM:
+        //     bool truly_toggled = esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_BBPLL, enable);
+        //     if (enable && truly_toggled) {
+        //         ESP_LOGW(TAG, "BBPLL enabled, a calibration may be needed");
+        //     }
+        default:
+            break;
+        }
     }
     return ESP_OK; // TODO: PM-653
 }
diff --git a/components/esp_hw_support/port/esp32h21/rtc_clk.c b/components/esp_hw_support/port/esp32h21/rtc_clk.c
index 56641c10b1f..d585f4c48fd 100644
--- a/components/esp_hw_support/port/esp32h21/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32h21/rtc_clk.c
@@ -131,16 +131,18 @@ soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void)
     return clk_ll_rtc_fast_get_src();
 }
 
-static __attribute__((unused)) void rtc_clk_bbpll_disable(void)
+#if BOOTLOADER_BUILD
+static void rtc_clk_bbpll_disable(void)
 {
     clk_ll_bbpll_disable();
     s_cur_pll_freq = 0;
 }
 
-static __attribute__((unused)) void rtc_clk_bbpll_enable(void)
+static void rtc_clk_bbpll_enable(void)
 {
     clk_ll_bbpll_enable();
 }
+#endif
 
 static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
 {
diff --git a/components/esp_security/src/esp32h21/esp_crypto_clk.h b/components/esp_security/src/esp32h21/esp_crypto_clk.h
index f56da300581..33184965077 100644
--- a/components/esp_security/src/esp32h21/esp_crypto_clk.h
+++ b/components/esp_security/src/esp32h21/esp_crypto_clk.h
@@ -13,4 +13,5 @@ static inline void esp_crypto_clk_init(void)
 {
     // Set crypto clock (`clk_sec`) to use 96M PLL clock
     REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x3);
+    // TODO: IDF-12266 need to call esp_clk_tree_enable_src() to acquire PLL 96M clock gating
 }
diff --git a/components/spi_flash/esp32h21/Kconfig.flash_freq b/components/spi_flash/esp32h21/Kconfig.flash_freq
index 4109c78217c..a23abaa6cb7 100644
--- a/components/spi_flash/esp32h21/Kconfig.flash_freq
+++ b/components/spi_flash/esp32h21/Kconfig.flash_freq
@@ -1,12 +1,8 @@
 choice ESPTOOLPY_FLASHFREQ
     prompt "Flash SPI speed"
-    default ESPTOOLPY_FLASHFREQ_32M if IDF_ENV_FPGA
-    default ESPTOOLPY_FLASHFREQ_48M
-    config ESPTOOLPY_FLASHFREQ_48M
-        bool "48 MHz"
+    default ESPTOOLPY_FLASHFREQ_64M
+    config ESPTOOLPY_FLASHFREQ_64M
+        bool "64 MHz"
     config ESPTOOLPY_FLASHFREQ_32M
         bool "32 MHz"
-        depends on IDF_ENV_FPGA
-    config ESPTOOLPY_FLASHFREQ_24M
-        bool "24 MHz"
 endchoice
diff --git a/components/spi_flash/esp32h4/Kconfig.flash_freq b/components/spi_flash/esp32h4/Kconfig.flash_freq
index 6c5f35eeaf5..a23abaa6cb7 100644
--- a/components/spi_flash/esp32h4/Kconfig.flash_freq
+++ b/components/spi_flash/esp32h4/Kconfig.flash_freq
@@ -1,6 +1,5 @@
 choice ESPTOOLPY_FLASHFREQ
     prompt "Flash SPI speed"
-    default ESPTOOLPY_FLASHFREQ_32M if IDF_ENV_FPGA
     default ESPTOOLPY_FLASHFREQ_64M
     config ESPTOOLPY_FLASHFREQ_64M
         bool "64 MHz"