fix(ulp): fix lp uart keep wakeup triggered

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -1606,3 +1606,7 @@ config SOC_LP_CORE_SUPPORT_I2C
 config SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE
     bool
     default y
+
+config SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED
+    bool
+    default y

components/soc/esp32c5/include/soc/soc_caps.h

@@ -639,3 +639,4 @@
 #define SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS   (1) /*!< LP Core will raise exceptions if accessing invalid addresses */
 #define SOC_LP_CORE_SUPPORT_I2C                     (1) /*!< LP Core supports I2C */
 #define SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE          (1) /*!< LP core requests sleep, PMU clears both HP and LP wakeup causes */
+#define SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED   (1) /*!< LP UART wakeup source is kept triggered */

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -1343,6 +1343,10 @@ config SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE
     bool
     default y
 
+config SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED
+    bool
+    default y
+
 config SOC_DEBUG_HAVE_OCD_STUB_BINS
     bool
     default y

components/soc/esp32c6/include/soc/soc_caps.h

@@ -544,6 +544,7 @@
 #define SOC_LP_CORE_SUPPORT_ETM               (1) /*!< LP Core supports ETM */
 #define SOC_LP_CORE_SUPPORT_I2C               (1) /*!< LP Core supports I2C */
 #define SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE    (1) /*!< LP core requests sleep, PMU clears both HP and LP wakeup causes */
+#define SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED   (1) /*!< LP UART wakeup source is kept triggered */
 
 /*------------------------------------- DEBUG CAPS -------------------------------------*/
 #define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -1922,3 +1922,7 @@ config SOC_LP_CORE_SUPPORT_I2C
 config SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE
     bool
     default y
+
+config SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED
+    bool
+    default y

components/soc/esp32p4/include/soc/soc_caps.h

@@ -735,3 +735,4 @@
 #define SOC_LP_CORE_SUPPORT_STORE_LOAD_EXCEPTIONS   (1) /*!< LP Core will raise exceptions if accessing invalid addresses */
 #define SOC_LP_CORE_SUPPORT_I2C                     (1) /*!< LP Core supports I2C */
 #define SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE          (1) /*!< LP core requests sleep, PMU clears both HP and LP wakeup causes */
+#define SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED   (1) /*!< LP UART wakeup source is kept triggered */

components/soc/esp32s31/include/soc/Kconfig.soc_caps.in

@@ -1547,6 +1547,10 @@ config SOC_LP_CORE_HAS_PMP
     bool
     default y
 
+config SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED
+    bool
+    default y
+
 config SOC_LP_TIMER_BIT_WIDTH_LO
     int
     default 32

components/soc/esp32s31/include/soc/soc_caps.h

@@ -576,6 +576,7 @@
 #define SOC_LP_CORE_SUPPORT_I2C                     (1) /*!< LP Core supports I2C */
 #define SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE          (1) /*!< LP core requests sleep, PMU clears both HP and LP wakeup causes */
 #define SOC_LP_CORE_HAS_PMP                         (1) /*!< LP Core RISC-V has 16 PMP entries (128-byte granularity, RISC-V v1.10) */
+#define SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED   (1) /*!< LP UART wakeup source is kept triggered */
 
 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
 #define SOC_LP_TIMER_BIT_WIDTH_LO           32 // Bit width of lp_timer low part