Merge branch 'feat/spi_p4_eco5_support' into 'master'

feat(driver_spi): update p4 eco5 spi and twai support

Closes IDF-13509, IDF-13434, and IDF-13726

See merge request espressif/esp-idf!41676

components/esp_driver_spi/src/gpspi/spi_common.c

@@ -614,7 +614,8 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
     }
     //set flags for DUAL mode according to output-capability of MOSI and MISO pins.
     if ((bus_config->mosi_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->mosi_io_num)) &&
-            (bus_config->miso_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->miso_io_num))) {
+            (bus_config->miso_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->miso_io_num)) &&
+            (bus_config->miso_io_num != bus_config->mosi_io_num)) {
         temp_flag |= SPICOMMON_BUSFLAG_DUAL;
     }
 

components/esp_driver_spi/src/gpspi/spi_master.c

@@ -633,9 +633,7 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle)
 
 esp_err_t spi_device_get_actual_freq(spi_device_handle_t handle, int* freq_khz)
 {
-    if ((spi_device_t *)handle == NULL || freq_khz == NULL) {
+    SPI_CHECK(handle && freq_khz, "invalid arg", ESP_ERR_INVALID_ARG);
-        return ESP_ERR_INVALID_ARG;
-    }
 
     *freq_khz = handle->hal_dev.timing_conf.real_freq / 1000;
     return ESP_OK;

components/esp_driver_spi/src/gpspi/spi_slave.c

@@ -104,20 +104,26 @@ static inline bool SPI_SLAVE_ISR_ATTR bus_is_iomux(spi_slave_t *host)
     return host->flags & SPICOMMON_BUSFLAG_IOMUX_PINS;
 }
 
-static void SPI_SLAVE_ISR_ATTR freeze_cs(spi_slave_t *host)
+static inline void SPI_SLAVE_ISR_ATTR freeze_cs(spi_slave_t *host)
 {
+#if SPI_LL_SLAVE_NEEDS_CS_WORKAROUND
+    // This workaround only for ESP32 due to old hardware design, see MR !3207
     esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, host->cs_in_signal, false);
+#endif
 }
 
 // Use this function instead of cs_initial to avoid overwrite the output config
 // This is used in test by internal gpio matrix connections
 static inline void SPI_SLAVE_ISR_ATTR restore_cs(spi_slave_t *host)
 {
+#if SPI_LL_SLAVE_NEEDS_CS_WORKAROUND
+    // This workaround only for ESP32 due to old hardware design, see MR !3207
     if (host->cs_iomux) {
         gpio_ll_set_input_signal_from(GPIO_HAL_GET_HW(GPIO_PORT_0), host->cs_in_signal, false);
     } else {
         esp_rom_gpio_connect_in_signal(host->cfg.spics_io_num, host->cs_in_signal, false);
     }
+#endif
 }
 
 #if (SOC_CPU_CORES_NUM > 1) && (!CONFIG_FREERTOS_UNICORE)
@@ -640,21 +646,13 @@ static void SPI_SLAVE_ISR_ATTR s_spi_slave_dma_prepare_data(spi_dma_ctx_t *dma_c
 
         spi_dma_reset(dma_ctx->rx_dma_chan);
         spi_slave_hal_hw_prepare_rx(hal->hw);
+        spi_dma_start(dma_ctx->rx_dma_chan, dma_ctx->dmadesc_rx);
     }
     if (hal->tx_buffer) {
         spicommon_dma_desc_setup_link(dma_ctx->dmadesc_tx, hal->tx_buffer, (hal->bitlen + 7) / 8, false);
 
         spi_dma_reset(dma_ctx->tx_dma_chan);
         spi_slave_hal_hw_prepare_tx(hal->hw);
-    }
-}
-
-static void SPI_SLAVE_ISR_ATTR s_spi_slave_start_dma(spi_dma_ctx_t *dma_ctx, spi_slave_hal_context_t *hal)
-{
-    if (hal->rx_buffer) {
-        spi_dma_start(dma_ctx->rx_dma_chan, dma_ctx->dmadesc_rx);
-    }
-    if (hal->tx_buffer) {
         spi_dma_start(dma_ctx->tx_dma_chan, dma_ctx->dmadesc_tx);
     }
 }
@@ -784,10 +782,7 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg)
 
         //The slave rx dma get disturbed by unexpected transaction. Only connect the CS and start DMA when slave is ready.
         if (use_dma) {
-            // Note: order of restore_cs and s_spi_slave_start_dma is important
-            // restore_cs also bring potential glitch, should happen before start DMA
             restore_cs(host);
-            s_spi_slave_start_dma(host->dma_ctx, hal);
         }
 
         //Kick off transfer

components/esp_driver_spi/test_apps/master/main/test_spi_master.c

@@ -1855,6 +1855,7 @@ TEST_CASE("test_spi_master_sleep_retention", "[spi]")
     spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
     buscfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS;
     buscfg.flags |= SPICOMMON_BUSFLAG_SLP_ALLOW_PD;
+    buscfg.miso_io_num = buscfg.mosi_io_num;    // set spi "self-loop"
     uint8_t send[16] = "hello spi x\n";
     uint8_t recv[16];
     spi_transaction_t trans_cfg = {
@@ -1871,8 +1872,6 @@ TEST_CASE("test_spi_master_sleep_retention", "[spi]")
 #endif
             printf("Retention on GPSPI%d with dma: %d\n", periph + 1, use_dma);
             TEST_ESP_OK(spi_bus_initialize(periph, &buscfg, use_dma));
-            // set spi "self-loop" after bus initialized
-            spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, spi_periph_signal[periph].spid_out);
             TEST_ESP_OK(spi_bus_add_device(periph, &devcfg, &dev_handle));
 
             for (uint8_t cnt = 0; cnt < 3; cnt ++) {
@@ -1927,9 +1926,8 @@ TEST_CASE("test_spi_master_auto_sleep_retention", "[spi]")
         spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
         buscfg.flags = (allow_pd) ? SPICOMMON_BUSFLAG_SLP_ALLOW_PD : 0;
         buscfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS;
+        buscfg.miso_io_num = buscfg.mosi_io_num;    // set spi "self-loop"
         TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_DISABLED));
-        // set spi "self-loop" after bus initialized
-        spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out);
 
         spi_device_handle_t dev_handle;
         spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();

components/hal/esp32/include/hal/spi_ll.h

@@ -44,6 +44,9 @@ extern "C" {
 #define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 #define SPI_LL_MOSI_FREE_LEVEL    0            //Default level after bus initialized
 
+// CS_WORKAROUND: SPI slave with using DMA, the rx dma suffers from unexpected transactions
+// before slave is ready, need disconnect CS before and after each transaction
+#define SPI_LL_SLAVE_NEEDS_CS_WORKAROUND    1
 #define SPI_LL_SLAVE_NEEDS_RESET_WORKAROUND 1
 #define SPI_LL_SUPPORT_TIME_TUNING          1
 

components/hal/esp32p4/include/hal/spi_ll.h

@@ -16,6 +16,7 @@
 
 #include <stdlib.h> //for abs()
 #include <string.h>
+#include "hal/config.h"
 #include "esp_types.h"
 #include "soc/spi_periph.h"
 #include "soc/spi_struct.h"
@@ -262,6 +263,10 @@ static inline void spi_ll_master_init(spi_dev_t *hw)
     hw->slave.val = 0;
     hw->user.val = 0;
 
+    //Disable unused error_end condition
+    hw->user1.mst_wfull_err_end_en = 0;
+    hw->user2.mst_rempty_err_end_en = 0;
+
     hw->dma_conf.val = 0;
     hw->dma_conf.slv_tx_seg_trans_clr_en = 1;
     hw->dma_conf.slv_rx_seg_trans_clr_en = 1;
@@ -763,13 +768,16 @@ static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active)
  *----------------------------------------------------------------------------*/
 /**
  * Set the standard clock mode for master.
+ * This config take effect only when SPI_CLK (pre-div before periph) div >=2
  *
  * @param hw  Beginning address of the peripheral registers.
  * @param enable_std True for std timing, False for half cycle delay sampling.
  */
 static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_point_t sample_point)
 {
-    //This is not supported
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    hw->clock.clk_edge_sel = (sample_point == SPI_SAMPLING_POINT_PHASE_1);
+#endif
 }
 
 /**
@@ -777,7 +785,11 @@ static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_
  */
 static inline bool spi_ll_master_is_rx_std_sample_supported(void)
 {
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    return true;
+#else
     return false;
+#endif
 }
 
 /**

components/soc/esp32p4/register/hw_ver3/soc/spi_struct.h

@@ -627,7 +627,15 @@ typedef union {
          *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
          */
         uint32_t clkdiv_pre:4;
-        uint32_t reserved_22:9;
+        uint32_t reserved_22:8;
+        /** clk_edge_sel : R/W; bitpos: [30]; default: 0;
+         *  Configures use standard clock sampling edge or delay the sampling edge by half a
+         *  cycle in master transfer.
+         *  0: clock sampling edge is delayed by half a cycle.
+         *  1: clock sampling edge is standard.
+         *  Can be configured in CONF state.
+         */
+        uint32_t clk_edge_sel:1;
         /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
          *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
          *  clock. Can be configured in CONF state.
@@ -975,7 +983,7 @@ typedef union {
  */
 typedef union {
     struct {
-        /** date : R/W; bitpos: [27:0]; default: 35680770;
+        /** date : R/W; bitpos: [27:0]; default: 37761424;
          *  SPI register version.
          */
         uint32_t date:28;

components/soc/esp32p4/register/hw_ver3/soc/twai_eco5_struct.h

@@ -1,799 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Registers */
-/** Type of mode register
- *  TWAI mode register.
- */
-typedef union {
-    struct {
-        /** reset_mode : R/W; bitpos: [0]; default: 1;
-         *  1: reset, detection of a set reset mode bit results in aborting the current
-         *  transmission/reception of a message and entering the reset mode. 0: normal, on the
-         *  '1-to-0' transition of the reset mode bit, the TWAI controller returns to the
-         *  operating mode.
-         */
-        uint32_t reset_mode:1;
-        /** listen_only_mode : R/W; bitpos: [1]; default: 0;
-         *  1: listen only, in this mode the TWAI controller would give no acknowledge to the
-         *  TWAI-bus, even if a message is received successfully. The error counters are
-         *  stopped at the current value. 0: normal.
-         */
-        uint32_t listen_only_mode:1;
-        /** self_test_mode : R/W; bitpos: [2]; default: 0;
-         *  1: self test, in this mode a full node test is possible without any other active
-         *  node on the bus using the self reception request command. The TWAI controller will
-         *  perform a successful transmission, even if there is no acknowledge received. 0:
-         *  normal, an acknowledge is required for successful transmission.
-         */
-        uint32_t self_test_mode:1;
-        /** acceptance_filter_mode : R/W; bitpos: [3]; default: 0;
-         *  1:single, the single acceptance filter option is enabled (one filter with the
-         *  length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled
-         *  (two filters, each with the length of 16 bit are active).
-         */
-        uint32_t acceptance_filter_mode:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} twai_mode_reg_t;
-
-/** Type of cmd register
- *  TWAI command register.
- */
-typedef union {
-    struct {
-        /** tx_request : WO; bitpos: [0]; default: 0;
-         *  1: present, a message shall be transmitted. 0: absent
-         */
-        uint32_t tx_request:1;
-        /** abort_tx : WO; bitpos: [1]; default: 0;
-         *  1: present, if not already in progress, a pending transmission request is
-         *  cancelled. 0: absent
-         */
-        uint32_t abort_tx:1;
-        /** release_buffer : WO; bitpos: [2]; default: 0;
-         *  1: released, the receive buffer, representing the message memory space in the
-         *  RXFIFO is released. 0: no action
-         */
-        uint32_t release_buffer:1;
-        /** clear_data_overrun : WO; bitpos: [3]; default: 0;
-         *  1: clear, the data overrun status bit is cleared. 0: no action.
-         */
-        uint32_t clear_data_overrun:1;
-        /** self_rx_request : WO; bitpos: [4]; default: 0;
-         *  1: present, a message shall be transmitted and received simultaneously. 0: absent.
-         */
-        uint32_t self_rx_request:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} twai_cmd_reg_t;
-
-/** Type of bus_timing_0 register
- *  Bit timing configuration register 0.
- */
-typedef union {
-    struct {
-        /** baud_presc : R/W; bitpos: [13:0]; default: 0;
-         *  The period of the TWAI system clock is programmable and determines the individual
-         *  bit timing. Software has R/W permission in reset mode and RO permission in
-         *  operation mode.
-         */
-        uint32_t baud_presc:14;
-        /** sync_jump_width : R/W; bitpos: [15:14]; default: 0;
-         *  The synchronization jump width defines the maximum number of clock cycles a bit
-         *  period may be shortened or lengthened. Software has R/W permission in reset mode
-         *  and RO in operation mode.
-         */
-        uint32_t sync_jump_width:2;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} twai_bus_timing_0_reg_t;
-
-/** Type of bus_timing_1 register
- *  Bit timing configuration register 1.
- */
-typedef union {
-    struct {
-        /** time_segment1 : R/W; bitpos: [3:0]; default: 0;
-         *  The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
-         *  reset mode and RO in operation mode.
-         */
-        uint32_t time_segment1:4;
-        /** time_segment2 : R/W; bitpos: [6:4]; default: 0;
-         *  The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in
-         *  reset mode and RO in operation mode.
-         */
-        uint32_t time_segment2:3;
-        /** time_sampling : R/W; bitpos: [7]; default: 0;
-         *  1: triple, the bus is sampled three times. 0: single, the bus is sampled once.
-         *  Software has R/W permission in reset mode and RO in operation mode.
-         */
-        uint32_t time_sampling:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_bus_timing_1_reg_t;
-
-/** Type of err_warning_limit register
- *  TWAI error threshold configuration register.
- */
-typedef union {
-    struct {
-        /** err_warning_limit : R/W; bitpos: [7:0]; default: 96;
-         *  The threshold that trigger error warning interrupt when this interrupt is enabled.
-         *  Software has R/W permission in reset mode and RO in operation mode.
-         */
-        uint32_t err_warning_limit:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_err_warning_limit_reg_t;
-
-/** Type of clock_divider register
- *  Clock divider register.
- */
-typedef union {
-    struct {
-        /** cd : R/W; bitpos: [7:0]; default: 0;
-         *  These bits are used to define the frequency at the external CLKOUT pin.
-         */
-        uint32_t cd:8;
-        /** clock_off : R/W; bitpos: [8]; default: 0;
-         *  1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has
-         *  R/W permission in reset mode and RO in operation mode.
-         */
-        uint32_t clock_off:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} twai_clock_divider_reg_t;
-
-/** Type of sw_standby_cfg register
- *  Software configure standby pin directly.
- */
-typedef union {
-    struct {
-        /** sw_standby_en : R/W; bitpos: [0]; default: 0;
-         *  Enable standby pin.
-         */
-        uint32_t sw_standby_en:1;
-        /** sw_standby_clr : R/W; bitpos: [1]; default: 1;
-         *  Clear standby pin.
-         */
-        uint32_t sw_standby_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} twai_sw_standby_cfg_reg_t;
-
-/** Type of hw_cfg register
- *  Hardware configure standby pin.
- */
-typedef union {
-    struct {
-        /** hw_standby_en : R/W; bitpos: [0]; default: 0;
-         *  Enable function that hardware control standby pin.
-         */
-        uint32_t hw_standby_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} twai_hw_cfg_reg_t;
-
-/** Type of hw_standby_cnt register
- *  Configure standby counter.
- */
-typedef union {
-    struct {
-        /** standby_wait_cnt : R/W; bitpos: [31:0]; default: 1;
-         *  Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
-         *  is enabled.
-         */
-        uint32_t standby_wait_cnt:32;
-    };
-    uint32_t val;
-} twai_hw_standby_cnt_reg_t;
-
-/** Type of idle_intr_cnt register
- *  Configure idle interrupt counter.
- */
-typedef union {
-    struct {
-        /** idle_intr_cnt : R/W; bitpos: [31:0]; default: 1;
-         *  Configure the number of cycles before triggering idle interrupt.
-         */
-        uint32_t idle_intr_cnt:32;
-    };
-    uint32_t val;
-} twai_idle_intr_cnt_reg_t;
-
-/** Type of eco_cfg register
- *  ECO configuration register.
- */
-typedef union {
-    struct {
-        /** rdn_ena : R/W; bitpos: [0]; default: 0;
-         *  Enable eco module.
-         */
-        uint32_t rdn_ena:1;
-        /** rdn_result : RO; bitpos: [1]; default: 1;
-         *  Output of eco module.
-         */
-        uint32_t rdn_result:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} twai_eco_cfg_reg_t;
-
-
-/** Group: Status Registers */
-/** Type of status register
- *  TWAI status register.
- */
-typedef union {
-    struct {
-        /** status_receive_buffer : RO; bitpos: [0]; default: 0;
-         *  1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
-         *  message is available
-         */
-        uint32_t status_receive_buffer:1;
-        /** status_overrun : RO; bitpos: [1]; default: 0;
-         *  1: overrun, a message was lost because there was not enough space for that message
-         *  in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data
-         *  overrun command was given
-         */
-        uint32_t status_overrun:1;
-        /** status_transmit_buffer : RO; bitpos: [2]; default: 0;
-         *  1: released, the CPU may write a message into the transmit buffer. 0: locked, the
-         *  CPU cannot access the transmit buffer, a message is either waiting for transmission
-         *  or is in the process of being transmitted
-         */
-        uint32_t status_transmit_buffer:1;
-        /** status_transmission_complete : RO; bitpos: [3]; default: 0;
-         *  1: complete, last requested transmission has been successfully completed. 0:
-         *  incomplete, previously requested transmission is not yet completed
-         */
-        uint32_t status_transmission_complete:1;
-        /** status_receive : RO; bitpos: [4]; default: 0;
-         *  1: receive, the TWAI controller is receiving a message. 0: idle
-         */
-        uint32_t status_receive:1;
-        /** status_transmit : RO; bitpos: [5]; default: 0;
-         *  1: transmit, the TWAI controller is transmitting a message. 0: idle
-         */
-        uint32_t status_transmit:1;
-        /** status_err : RO; bitpos: [6]; default: 0;
-         *  1: error, at least one of the error counters has reached or exceeded the CPU
-         *  warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error
-         *  counters are below the warning limit
-         */
-        uint32_t status_err:1;
-        /** status_node_bus_off : RO; bitpos: [7]; default: 0;
-         *  1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the
-         *  TWAI controller is involved in bus activities
-         */
-        uint32_t status_node_bus_off:1;
-        /** status_miss : RO; bitpos: [8]; default: 0;
-         *  1: current message is destroyed because of FIFO overflow.
-         */
-        uint32_t status_miss:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} twai_status_reg_t;
-
-/** Type of arb_lost_cap register
- *  TWAI arbiter lost capture register.
- */
-typedef union {
-    struct {
-        /** arbitration_lost_capture : RO; bitpos: [4:0]; default: 0;
-         *  This register contains information about the bit position of losing arbitration.
-         */
-        uint32_t arbitration_lost_capture:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} twai_arb_lost_cap_reg_t;
-
-/** Type of err_code_cap register
- *  TWAI error info capture register.
- */
-typedef union {
-    struct {
-        /** err_capture_code_segment : RO; bitpos: [4:0]; default: 0;
-         *  This register contains information about the location of errors on the bus.
-         */
-        uint32_t err_capture_code_segment:5;
-        /** err_capture_code_direction : RO; bitpos: [5]; default: 0;
-         *  1: RX, error occurred during reception. 0: TX, error occurred during transmission.
-         */
-        uint32_t err_capture_code_direction:1;
-        /** err_capture_code_type : RO; bitpos: [7:6]; default: 0;
-         *  00: bit error. 01: form error. 10:stuff error. 11:other type of error.
-         */
-        uint32_t err_capture_code_type:2;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_err_code_cap_reg_t;
-
-/** Type of rx_err_cnt register
- *  Rx error counter register.
- */
-typedef union {
-    struct {
-        /** rx_err_cnt : R/W; bitpos: [7:0]; default: 0;
-         *  The RX error counter register reflects the current value of the transmit error
-         *  counter. Software has R/W permission in reset mode and RO in operation mode.
-         */
-        uint32_t rx_err_cnt:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_rx_err_cnt_reg_t;
-
-/** Type of tx_err_cnt register
- *  Tx error counter register.
- */
-typedef union {
-    struct {
-        /** tx_err_cnt : R/W; bitpos: [7:0]; default: 0;
-         *  The TX error counter register reflects the current value of the transmit error
-         *  counter. Software has R/W permission in reset mode and RO in operation mode.
-         */
-        uint32_t tx_err_cnt:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_tx_err_cnt_reg_t;
-
-/** Type of rx_message_counter register
- *  Received message counter register.
- */
-typedef union {
-    struct {
-        /** rx_message_counter : RO; bitpos: [6:0]; default: 0;
-         *  Reflects the number of messages available within the RXFIFO. The value is
-         *  incremented with each receive event and decremented by the release receive buffer
-         *  command.
-         */
-        uint32_t rx_message_counter:7;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} twai_rx_message_counter_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of interrupt register
- *  Interrupt signals' register.
- */
-typedef union {
-    struct {
-        /** receive_int_st : RO; bitpos: [0]; default: 0;
-         *  1: this bit is set while the receive FIFO is not empty and the RIE bit is set
-         *  within the interrupt enable register. 0: reset
-         */
-        uint32_t receive_int_st:1;
-        /** transmit_int_st : RO; bitpos: [1]; default: 0;
-         *  1: this bit is set whenever the transmit buffer status changes from '0-to-1'
-         *  (released) and the TIE bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t transmit_int_st:1;
-        /** err_warning_int_st : RO; bitpos: [2]; default: 0;
-         *  1: this bit is set on every change (set and clear) of either the error status or
-         *  bus status bits and the EIE bit is set within the interrupt enable register. 0:
-         *  reset
-         */
-        uint32_t err_warning_int_st:1;
-        /** data_overrun_int_st : RO; bitpos: [3]; default: 0;
-         *  1: this bit is set on a '0-to-1' transition of the data overrun status bit and the
-         *  DOIE bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t data_overrun_int_st:1;
-        /** ts_counter_ovfl_int_st : RO; bitpos: [4]; default: 0;
-         *  1: this bit is set then the timestamp counter reaches the maximum value and
-         *  overflow.
-         */
-        uint32_t ts_counter_ovfl_int_st:1;
-        /** err_passive_int_st : RO; bitpos: [5]; default: 0;
-         *  1: this bit is set whenever the TWAI controller has reached the error passive
-         *  status (at least one error counter exceeds the protocol-defined level of 127) or if
-         *  the TWAI controller is in the error passive status and enters the error active
-         *  status again and the EPIE bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t err_passive_int_st:1;
-        /** arbitration_lost_int_st : RO; bitpos: [6]; default: 0;
-         *  1: this bit is set when the TWAI controller lost the arbitration and becomes a
-         *  receiver and the ALIE bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t arbitration_lost_int_st:1;
-        /** bus_err_int_st : RO; bitpos: [7]; default: 0;
-         *  1: this bit is set when the TWAI controller detects an error on the TWAI-bus and
-         *  the BEIE bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t bus_err_int_st:1;
-        /** idle_int_st : RO; bitpos: [8]; default: 0;
-         *  1: this bit is set when the TWAI controller detects state of TWAI become IDLE and
-         *  this interrupt enable bit is set within the interrupt enable register. 0: reset
-         */
-        uint32_t idle_int_st:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} twai_interrupt_reg_t;
-
-/** Type of interrupt_enable register
- *  Interrupt enable register.
- */
-typedef union {
-    struct {
-        /** ext_receive_int_ena : R/W; bitpos: [0]; default: 0;
-         *  1: enabled, when the receive buffer status is 'full' the TWAI controller requests
-         *  the respective interrupt. 0: disable
-         */
-        uint32_t ext_receive_int_ena:1;
-        /** ext_transmit_int_ena : R/W; bitpos: [1]; default: 0;
-         *  1: enabled, when a message has been successfully transmitted or the transmit buffer
-         *  is accessible again (e.g. after an abort transmission command), the TWAI controller
-         *  requests the respective interrupt. 0: disable
-         */
-        uint32_t ext_transmit_int_ena:1;
-        /** ext_err_warning_int_ena : R/W; bitpos: [2]; default: 0;
-         *  1: enabled, if the error or bus status change (see status register. Table 14), the
-         *  TWAI controllerrequests the respective interrupt. 0: disable
-         */
-        uint32_t ext_err_warning_int_ena:1;
-        /** ext_data_overrun_int_ena : R/W; bitpos: [3]; default: 0;
-         *  1: enabled, if the data overrun status bit is set (see status register. Table 14),
-         *  the TWAI controllerrequests the respective interrupt. 0: disable
-         */
-        uint32_t ext_data_overrun_int_ena:1;
-        /** ts_counter_ovfl_int_ena : R/W; bitpos: [4]; default: 0;
-         *  enable the timestamp counter overflow interrupt request.
-         */
-        uint32_t ts_counter_ovfl_int_ena:1;
-        /** err_passive_int_ena : R/W; bitpos: [5]; default: 0;
-         *  1: enabled, if the error status of the TWAI controller changes from error active to
-         *  error passive or vice versa, the respective interrupt is requested. 0: disable
-         */
-        uint32_t err_passive_int_ena:1;
-        /** arbitration_lost_int_ena : R/W; bitpos: [6]; default: 0;
-         *  1: enabled, if the TWAI controller has lost arbitration, the respective interrupt
-         *  is requested. 0: disable
-         */
-        uint32_t arbitration_lost_int_ena:1;
-        /** bus_err_int_ena : R/W; bitpos: [7]; default: 0;
-         *  1: enabled, if an bus error has been detected, the TWAI controller requests the
-         *  respective interrupt. 0: disable
-         */
-        uint32_t bus_err_int_ena:1;
-        /** idle_int_ena : RO; bitpos: [8]; default: 0;
-         *  1: enabled, if state of TWAI become IDLE, the TWAI controller requests the
-         *  respective interrupt. 0: disable
-         */
-        uint32_t idle_int_ena:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} twai_interrupt_enable_reg_t;
-
-
-/** Group: Data Registers */
-/** Type of data_0 register
- *  Data register 0.
- */
-typedef union {
-    struct {
-        /** data_0 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance code register 0 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 0 and when
-         *  software initiate read operation, it is rx data register 0.
-         */
-        uint32_t data_0:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_0_reg_t;
-
-/** Type of data_1 register
- *  Data register 1.
- */
-typedef union {
-    struct {
-        /** data_1 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance code register 1 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 1 and when
-         *  software initiate read operation, it is rx data register 1.
-         */
-        uint32_t data_1:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_1_reg_t;
-
-/** Type of data_2 register
- *  Data register 2.
- */
-typedef union {
-    struct {
-        /** data_2 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance code register 2 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 2 and when
-         *  software initiate read operation, it is rx data register 2.
-         */
-        uint32_t data_2:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_2_reg_t;
-
-/** Type of data_3 register
- *  Data register 3.
- */
-typedef union {
-    struct {
-        /** data_3 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance code register 3 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 3 and when
-         *  software initiate read operation, it is rx data register 3.
-         */
-        uint32_t data_3:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_3_reg_t;
-
-/** Type of data_4 register
- *  Data register 4.
- */
-typedef union {
-    struct {
-        /** data_4 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance mask register 0 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 4 and when
-         *  software initiate read operation, it is rx data register 4.
-         */
-        uint32_t data_4:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_4_reg_t;
-
-/** Type of data_5 register
- *  Data register 5.
- */
-typedef union {
-    struct {
-        /** data_5 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance mask register 1 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 5 and when
-         *  software initiate read operation, it is rx data register 5.
-         */
-        uint32_t data_5:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_5_reg_t;
-
-/** Type of data_6 register
- *  Data register 6.
- */
-typedef union {
-    struct {
-        /** data_6 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance mask register 2 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 6 and when
-         *  software initiate read operation, it is rx data register 6.
-         */
-        uint32_t data_6:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_6_reg_t;
-
-/** Type of data_7 register
- *  Data register 7.
- */
-typedef union {
-    struct {
-        /** data_7 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, it is acceptance mask register 3 with R/W Permission. In operation
-         *  mode, when software initiate write operation, it is tx data register 7 and when
-         *  software initiate read operation, it is rx data register 7.
-         */
-        uint32_t data_7:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_7_reg_t;
-
-/** Type of data_8 register
- *  Data register 8.
- */
-typedef union {
-    struct {
-        /** data_8 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, reserved with RO. In operation mode, when software initiate write
-         *  operation, it is tx data register 8 and when software initiate read operation, it
-         *  is rx data register 8.
-         */
-        uint32_t data_8:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_8_reg_t;
-
-/** Type of data_9 register
- *  Data register 9.
- */
-typedef union {
-    struct {
-        /** data_9 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, reserved with RO. In operation mode, when software initiate write
-         *  operation, it is tx data register 9 and when software initiate read operation, it
-         *  is rx data register 9.
-         */
-        uint32_t data_9:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_9_reg_t;
-
-/** Type of data_10 register
- *  Data register 10.
- */
-typedef union {
-    struct {
-        /** data_10 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, reserved with RO. In operation mode, when software initiate write
-         *  operation, it is tx data register 10 and when software initiate read operation, it
-         *  is rx data register 10.
-         */
-        uint32_t data_10:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_10_reg_t;
-
-/** Type of data_11 register
- *  Data register 11.
- */
-typedef union {
-    struct {
-        /** data_11 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, reserved with RO. In operation mode, when software initiate write
-         *  operation, it is tx data register 11 and when software initiate read operation, it
-         *  is rx data register 11.
-         */
-        uint32_t data_11:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_11_reg_t;
-
-/** Type of data_12 register
- *  Data register 12.
- */
-typedef union {
-    struct {
-        /** data_12 : R/W; bitpos: [7:0]; default: 0;
-         *  In reset mode, reserved with RO. In operation mode, when software initiate write
-         *  operation, it is tx data register 12 and when software initiate read operation, it
-         *  is rx data register 12.
-         */
-        uint32_t data_12:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} twai_data_12_reg_t;
-
-
-/** Group: Timestamp Register */
-/** Type of timestamp_data register
- *  Timestamp data register
- */
-typedef union {
-    struct {
-        /** timestamp_data : RO; bitpos: [31:0]; default: 0;
-         *  Data of timestamp of a CAN frame.
-         */
-        uint32_t timestamp_data:32;
-    };
-    uint32_t val;
-} twai_timestamp_data_reg_t;
-
-/** Type of timestamp_prescaler register
- *  Timestamp configuration register
- */
-typedef union {
-    struct {
-        /** ts_div_num : R/W; bitpos: [15:0]; default: 31;
-         *  Configures the clock division number of timestamp counter.
-         */
-        uint32_t ts_div_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} twai_timestamp_prescaler_reg_t;
-
-/** Type of timestamp_cfg register
- *  Timestamp configuration register
- */
-typedef union {
-    struct {
-        /** ts_enable : R/W; bitpos: [0]; default: 0;
-         *  enable the timestamp collection function.
-         */
-        uint32_t ts_enable:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} twai_timestamp_cfg_reg_t;
-
-
-typedef struct {
-    volatile twai_mode_reg_t mode;
-    volatile twai_cmd_reg_t cmd;
-    volatile twai_status_reg_t status;
-    volatile twai_interrupt_reg_t interrupt;
-    volatile twai_interrupt_enable_reg_t interrupt_enable;
-    uint32_t reserved_014;
-    volatile twai_bus_timing_0_reg_t bus_timing_0;
-    volatile twai_bus_timing_1_reg_t bus_timing_1;
-    uint32_t reserved_020[3];
-    volatile twai_arb_lost_cap_reg_t arb_lost_cap;
-    volatile twai_err_code_cap_reg_t err_code_cap;
-    volatile twai_err_warning_limit_reg_t err_warning_limit;
-    volatile twai_rx_err_cnt_reg_t rx_err_cnt;
-    volatile twai_tx_err_cnt_reg_t tx_err_cnt;
-    volatile twai_data_0_reg_t data_0;
-    volatile twai_data_1_reg_t data_1;
-    volatile twai_data_2_reg_t data_2;
-    volatile twai_data_3_reg_t data_3;
-    volatile twai_data_4_reg_t data_4;
-    volatile twai_data_5_reg_t data_5;
-    volatile twai_data_6_reg_t data_6;
-    volatile twai_data_7_reg_t data_7;
-    volatile twai_data_8_reg_t data_8;
-    volatile twai_data_9_reg_t data_9;
-    volatile twai_data_10_reg_t data_10;
-    volatile twai_data_11_reg_t data_11;
-    volatile twai_data_12_reg_t data_12;
-    volatile twai_rx_message_counter_reg_t rx_message_counter;
-    uint32_t reserved_078;
-    volatile twai_clock_divider_reg_t clock_divider;
-    volatile twai_sw_standby_cfg_reg_t sw_standby_cfg;
-    volatile twai_hw_cfg_reg_t hw_cfg;
-    volatile twai_hw_standby_cnt_reg_t hw_standby_cnt;
-    volatile twai_idle_intr_cnt_reg_t idle_intr_cnt;
-    volatile twai_eco_cfg_reg_t eco_cfg;
-    volatile twai_timestamp_data_reg_t timestamp_data;
-    volatile twai_timestamp_prescaler_reg_t timestamp_prescaler;
-    volatile twai_timestamp_cfg_reg_t timestamp_cfg;
-} twai_dev_t;
-
-extern twai_dev_t TWAI0;
-extern twai_dev_t TWAI1;
-extern twai_dev_t TWAI2;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(twai_dev_t) == 0xa0, "Invalid size of twai_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif