feat(esp32h4): finnal introduce hello world

2026-10-02 11:10:54 +03:00 · 2025-03-19 18:48:41 +08:00
parent 9fd0f634d2
commit 45ba78940f
45 changed files with 6088 additions and 92 deletions
@@ -357,16 +357,12 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_128

 config SOC_UART_NUM
    int
-    default 3
+    default 2

 config SOC_UART_HP_NUM
    int
    default 2

-config SOC_UART_LP_NUM
-    int
-    default 1
-
 config SOC_UART_FIFO_LEN
    int
    default 128
@@ -469,10 +469,9 @@
 // #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED     1

 /*-------------------------- UART CAPS ---------------------------------------*/
-// ESP32-H4 has 3 UARTs (2 HP UART, and 1 LP UART)  TODO: IDF-12445 [ESP32H4] inherit from verify code, need remove LP*/
-#define SOC_UART_NUM                    (3)
+// ESP32-H4 has 2 HP UARTs
+#define SOC_UART_NUM                    (2)
 #define SOC_UART_HP_NUM                 (2)
-#define SOC_UART_LP_NUM                 (1U)
 #define SOC_UART_FIFO_LEN               (128)       /*!< The UART hardware FIFO length */
 #define SOC_LP_UART_FIFO_LEN            (16)        /*!< The LP UART hardware FIFO length */
 #define SOC_UART_BITRATE_MAX            (5000000)   /*!< Max bit rate supported by UART */
@@ -11,10 +11,12 @@
 extern "C" {
 #endif

+#define DR_REG_SPI_BASE(i)                       (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0))    // GPSPI2 and GPSPI3
+
 /** SPI_CMD_REG register
 *  Command control register
 */
-#define SPI_CMD_REG (DR_REG_SPI_BASE + 0x0)
+#define SPI_CMD_REG(i) (DR_REG_SPI_BASE(i) + 0x0)
 /** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0;
 *  Configures the SPI_CLK cycles of SPI CONF state.
 *  Measurement unit: SPI_CLK clock cycle.
@@ -50,7 +52,7 @@ extern "C" {
 /** SPI_ADDR_REG register
 *  Address value register
 */
-#define SPI_ADDR_REG (DR_REG_SPI_BASE + 0x4)
+#define SPI_ADDR_REG(i) (DR_REG_SPI_BASE(i) + 0x4)
 /** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
 *  Configures the address to slave.
 *  Can be configured in CONF state.
@@ -63,7 +65,7 @@ extern "C" {
 /** SPI_CTRL_REG register
 *  SPI control register
 */
-#define SPI_CTRL_REG (DR_REG_SPI_BASE + 0x8)
+#define SPI_CTRL_REG(i) (DR_REG_SPI_BASE(i) + 0x8)
 /** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
 *  Configures whether or not to output the FSPI bus signals in DUMMY state.
 *  0: Not output
@@ -232,7 +234,7 @@ extern "C" {
 /** SPI_CLOCK_REG register
 *  SPI clock control register
 */
-#define SPI_CLOCK_REG (DR_REG_SPI_BASE + 0xc)
+#define SPI_CLOCK_REG(i) (DR_REG_SPI_BASE(i) + 0xc)
 /** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
 *  In master transfer, this field must be equal to SPI_CLKCNT_N. In slave mode, it
 *  must be 0. Can be configured in CONF state.
@@ -295,7 +297,7 @@ extern "C" {
 /** SPI_USER_REG register
 *  SPI USER control register
 */
-#define SPI_USER_REG (DR_REG_SPI_BASE + 0x10)
+#define SPI_USER_REG(i) (DR_REG_SPI_BASE(i) + 0x10)
 /** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable full-duplex communication.
 *  0: Disable
@@ -511,7 +513,7 @@ extern "C" {
 /** SPI_USER1_REG register
 *  SPI USER control register 1
 */
-#define SPI_USER1_REG (DR_REG_SPI_BASE + 0x14)
+#define SPI_USER1_REG(i) (DR_REG_SPI_BASE(i) + 0x14)
 /** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
 *  Configures the length of DUMMY state.
 *  Measurement unit: SPI_CLK clock cycles.
@@ -562,7 +564,7 @@ extern "C" {
 /** SPI_USER2_REG register
 *  SPI USER control register 2
 */
-#define SPI_USER2_REG (DR_REG_SPI_BASE + 0x18)
+#define SPI_USER2_REG(i) (DR_REG_SPI_BASE(i) + 0x18)
 /** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
 *  Configures the command value.
 *  Can be configured in CONF state.
@@ -593,7 +595,7 @@ extern "C" {
 /** SPI_MS_DLEN_REG register
 *  SPI data bit length control register
 */
-#define SPI_MS_DLEN_REG (DR_REG_SPI_BASE + 0x1c)
+#define SPI_MS_DLEN_REG(i) (DR_REG_SPI_BASE(i) + 0x1c)
 /** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0;
 *  Configures the data bit length of SPI transfer in DMA-controlled master transfer or
 *  in CPU-controlled master transfer. Or configures the bit length of SPI RX transfer
@@ -608,7 +610,7 @@ extern "C" {
 /** SPI_MISC_REG register
 *  SPI misc register
 */
-#define SPI_MISC_REG (DR_REG_SPI_BASE + 0x20)
+#define SPI_MISC_REG(i) (DR_REG_SPI_BASE(i) + 0x20)
 /** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to disable SPI_CS$n pin.
 *  0: SPI_CS$n signal is from/to SPI_CS$n pin.
@@ -773,7 +775,7 @@ extern "C" {
 /** SPI_DIN_MODE_REG register
 *  SPI input delay mode configuration
 */
-#define SPI_DIN_MODE_REG (DR_REG_SPI_BASE + 0x24)
+#define SPI_DIN_MODE_REG(i) (DR_REG_SPI_BASE(i) + 0x24)
 /** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0;
 *  Configures the input mode for FSPID signal.
 *  0: Input without delay
@@ -882,7 +884,7 @@ extern "C" {
 /** SPI_DIN_NUM_REG register
 *  SPI input delay number configuration
 */
-#define SPI_DIN_NUM_REG (DR_REG_SPI_BASE + 0x28)
+#define SPI_DIN_NUM_REG(i) (DR_REG_SPI_BASE(i) + 0x28)
 /** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
 *  Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE.
 *  0: Delayed by 1 clock cycle
@@ -967,7 +969,7 @@ extern "C" {
 /** SPI_DOUT_MODE_REG register
 *  SPI output delay mode configuration
 */
-#define SPI_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x2c)
+#define SPI_DOUT_MODE_REG(i) (DR_REG_SPI_BASE(i) + 0x2c)
 /** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
 *  Configures the output mode for FSPID signal.
 *  0: Output without delay
@@ -1057,7 +1059,7 @@ extern "C" {
 /** SPI_DMA_CONF_REG register
 *  SPI DMA control register
 */
-#define SPI_DMA_CONF_REG (DR_REG_SPI_BASE + 0x30)
+#define SPI_DMA_CONF_REG(i) (DR_REG_SPI_BASE(i) + 0x30)
 /** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1;
 *  Represents whether or not the DMA TX FIFO is ready for sending data.
 *  0: Ready
@@ -1178,7 +1180,7 @@ extern "C" {
 /** SPI_DMA_INT_ENA_REG register
 *  SPI interrupt enable register
 */
-#define SPI_DMA_INT_ENA_REG (DR_REG_SPI_BASE + 0x34)
+#define SPI_DMA_INT_ENA_REG(i) (DR_REG_SPI_BASE(i) + 0x34)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
 *  Write 1 to enable SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
 */
@@ -1330,7 +1332,7 @@ extern "C" {
 /** SPI_DMA_INT_CLR_REG register
 *  SPI interrupt clear register
 */
-#define SPI_DMA_INT_CLR_REG (DR_REG_SPI_BASE + 0x38)
+#define SPI_DMA_INT_CLR_REG(i) (DR_REG_SPI_BASE(i) + 0x38)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
 *  Write 1 to clear SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
 */
@@ -1482,7 +1484,7 @@ extern "C" {
 /** SPI_DMA_INT_RAW_REG register
 *  SPI interrupt raw register
 */
-#define SPI_DMA_INT_RAW_REG (DR_REG_SPI_BASE + 0x3c)
+#define SPI_DMA_INT_RAW_REG(i) (DR_REG_SPI_BASE(i) + 0x3c)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
 *  The raw interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
 */
@@ -1638,7 +1640,7 @@ extern "C" {
 /** SPI_DMA_INT_ST_REG register
 *  SPI interrupt status register
 */
-#define SPI_DMA_INT_ST_REG (DR_REG_SPI_BASE + 0x40)
+#define SPI_DMA_INT_ST_REG(i) (DR_REG_SPI_BASE(i) + 0x40)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0;
 *  The interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
 */
@@ -1790,7 +1792,7 @@ extern "C" {
 /** SPI_DMA_INT_SET_REG register
 *  SPI interrupt software set register
 */
-#define SPI_DMA_INT_SET_REG (DR_REG_SPI_BASE + 0x44)
+#define SPI_DMA_INT_SET_REG(i) (DR_REG_SPI_BASE(i) + 0x44)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0;
 *  Write 1 to set SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
 */
@@ -1942,7 +1944,7 @@ extern "C" {
 /** SPI_W0_REG register
 *  SPI CPU-controlled buffer0
 */
-#define SPI_W0_REG (DR_REG_SPI_BASE + 0x98)
+#define SPI_W0_REG(i) (DR_REG_SPI_BASE(i) + 0x98)
 /** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@@ -1954,7 +1956,7 @@ extern "C" {
 /** SPI_W1_REG register
 *  SPI CPU-controlled buffer1
 */
-#define SPI_W1_REG (DR_REG_SPI_BASE + 0x9c)
+#define SPI_W1_REG(i) (DR_REG_SPI_BASE(i) + 0x9c)
 /** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@@ -1966,7 +1968,7 @@ extern "C" {
 /** SPI_W2_REG register
 *  SPI CPU-controlled buffer2
 */
-#define SPI_W2_REG (DR_REG_SPI_BASE + 0xa0)
+#define SPI_W2_REG(i) (DR_REG_SPI_BASE(i) + 0xa0)
 /** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@@ -1978,7 +1980,7 @@ extern "C" {
 /** SPI_W3_REG register
 *  SPI CPU-controlled buffer3
 */
-#define SPI_W3_REG (DR_REG_SPI_BASE + 0xa4)
+#define SPI_W3_REG(i) (DR_REG_SPI_BASE(i) + 0xa4)
 /** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@@ -1990,7 +1992,7 @@ extern "C" {
 /** SPI_W4_REG register
 *  SPI CPU-controlled buffer4
 */
-#define SPI_W4_REG (DR_REG_SPI_BASE + 0xa8)
+#define SPI_W4_REG(i) (DR_REG_SPI_BASE(i) + 0xa8)
 /** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@@ -2002,7 +2004,7 @@ extern "C" {
 /** SPI_W5_REG register
 *  SPI CPU-controlled buffer5
 */
-#define SPI_W5_REG (DR_REG_SPI_BASE + 0xac)
+#define SPI_W5_REG(i) (DR_REG_SPI_BASE(i) + 0xac)
 /** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@@ -2014,7 +2016,7 @@ extern "C" {
 /** SPI_W6_REG register
 *  SPI CPU-controlled buffer6
 */
-#define SPI_W6_REG (DR_REG_SPI_BASE + 0xb0)
+#define SPI_W6_REG(i) (DR_REG_SPI_BASE(i) + 0xb0)
 /** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@@ -2026,7 +2028,7 @@ extern "C" {
 /** SPI_W7_REG register
 *  SPI CPU-controlled buffer7
 */
-#define SPI_W7_REG (DR_REG_SPI_BASE + 0xb4)
+#define SPI_W7_REG(i) (DR_REG_SPI_BASE(i) + 0xb4)
 /** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@@ -2038,7 +2040,7 @@ extern "C" {
 /** SPI_W8_REG register
 *  SPI CPU-controlled buffer8
 */
-#define SPI_W8_REG (DR_REG_SPI_BASE + 0xb8)
+#define SPI_W8_REG(i) (DR_REG_SPI_BASE(i) + 0xb8)
 /** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@@ -2050,7 +2052,7 @@ extern "C" {
 /** SPI_W9_REG register
 *  SPI CPU-controlled buffer9
 */
-#define SPI_W9_REG (DR_REG_SPI_BASE + 0xbc)
+#define SPI_W9_REG(i) (DR_REG_SPI_BASE(i) + 0xbc)
 /** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@@ -2062,7 +2064,7 @@ extern "C" {
 /** SPI_W10_REG register
 *  SPI CPU-controlled buffer10
 */
-#define SPI_W10_REG (DR_REG_SPI_BASE + 0xc0)
+#define SPI_W10_REG(i) (DR_REG_SPI_BASE(i) + 0xc0)
 /** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@@ -2074,7 +2076,7 @@ extern "C" {
 /** SPI_W11_REG register
 *  SPI CPU-controlled buffer11
 */
-#define SPI_W11_REG (DR_REG_SPI_BASE + 0xc4)
+#define SPI_W11_REG(i) (DR_REG_SPI_BASE(i) + 0xc4)
 /** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@@ -2086,7 +2088,7 @@ extern "C" {
 /** SPI_W12_REG register
 *  SPI CPU-controlled buffer12
 */
-#define SPI_W12_REG (DR_REG_SPI_BASE + 0xc8)
+#define SPI_W12_REG(i) (DR_REG_SPI_BASE(i) + 0xc8)
 /** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@@ -2098,7 +2100,7 @@ extern "C" {
 /** SPI_W13_REG register
 *  SPI CPU-controlled buffer13
 */
-#define SPI_W13_REG (DR_REG_SPI_BASE + 0xcc)
+#define SPI_W13_REG(i) (DR_REG_SPI_BASE(i) + 0xcc)
 /** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@@ -2110,7 +2112,7 @@ extern "C" {
 /** SPI_W14_REG register
 *  SPI CPU-controlled buffer14
 */
-#define SPI_W14_REG (DR_REG_SPI_BASE + 0xd0)
+#define SPI_W14_REG(i) (DR_REG_SPI_BASE(i) + 0xd0)
 /** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@@ -2122,7 +2124,7 @@ extern "C" {
 /** SPI_W15_REG register
 *  SPI CPU-controlled buffer15
 */
-#define SPI_W15_REG (DR_REG_SPI_BASE + 0xd4)
+#define SPI_W15_REG(i) (DR_REG_SPI_BASE(i) + 0xd4)
 /** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
 *  32-bit data buffer $n.
 */
@@ -2134,7 +2136,7 @@ extern "C" {
 /** SPI_SLAVE_REG register
 *  SPI slave control register
 */
-#define SPI_SLAVE_REG (DR_REG_SPI_BASE + 0xe0)
+#define SPI_SLAVE_REG(i) (DR_REG_SPI_BASE(i) + 0xe0)
 /** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
 *  Configures SPI clock mode.
 *  0: SPI clock is off when CS becomes inactive.
@@ -2265,7 +2267,7 @@ extern "C" {
 /** SPI_SLAVE1_REG register
 *  SPI slave control register 1
 */
-#define SPI_SLAVE1_REG (DR_REG_SPI_BASE + 0xe4)
+#define SPI_SLAVE1_REG(i) (DR_REG_SPI_BASE(i) + 0xe4)
 /** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0;
 *  Configures the transferred data bit length in SPI slave full-/half-duplex modes.
 */
@@ -2291,7 +2293,7 @@ extern "C" {
 /** SPI_CLK_GATE_REG register
 *  SPI module clock and register clock control
 */
-#define SPI_CLK_GATE_REG (DR_REG_SPI_BASE + 0xe8)
+#define SPI_CLK_GATE_REG(i) (DR_REG_SPI_BASE(i) + 0xe8)
 /** SPI_CLK_EN : R/W; bitpos: [0]; default: 0;
 *  Configures whether or not to enable clock gate.
 *  0: Disable
@@ -2320,7 +2322,7 @@ extern "C" {
 /** SPI_DATE_REG register
 *  Version control
 */
-#define SPI_DATE_REG (DR_REG_SPI_BASE + 0xf0)
+#define SPI_DATE_REG(i) (DR_REG_SPI_BASE(i) + 0xf0)
 /** SPI_DATE : R/W; bitpos: [27:0]; default: 37761424;
 *  Version control register.
 */
@@ -11,6 +11,9 @@
 extern "C" {
 #endif

+#define DR_REG_UART_BASE(i)                        (DR_REG_UART0_BASE + (i) * 0x1000)
+#define REG_UART_BASE(i)                           (DR_REG_UART0_BASE + (i) * 0x1000)
+
 /** UART_FIFO_REG register
 *  FIFO data register
 */
@@ -0,0 +1,7 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+
+// TODO: [ESP32H4] IDF-12393