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Merge branch 'feature/support_h2_adc' into 'master'

Browse Source 
adc: support adc h2

Closes IDF-6124, IDF-6214, IDF-6543, IDF-6215, IDF-6664, and IDF-6695

See merge request espressif/esp-idf!22205
This commit is contained in:
Armando (Dou Yiwen)
2023-02-24 14:28:33 +08:00
parent a529771d88 486c765a93
commit 4452a3cf3e
72 changed files with 1446 additions and 457 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+4
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@@ -163,6 +163,10 @@ config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
config SOC_ADC_SELF_HW_CALI_SUPPORTED
bool
default y
config SOC_BROWNOUT_RESET_SUPPORTED
bool
default y
components/soc/esp32c2/include/soc/soc_caps.h
+1
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@@ -79,6 +79,7 @@
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#define SOC_BROWNOUT_RESET_SUPPORTED 1
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+4
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@@ -243,6 +243,10 @@ config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
config SOC_ADC_SELF_HW_CALI_SUPPORTED
bool
default y
config SOC_APB_BACKUP_DMA
bool
default y
components/soc/esp32c3/include/soc/soc_caps.h
+1
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@@ -107,6 +107,7 @@
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
#define SOC_APB_BACKUP_DMA (1)
components/soc/esp32c6/include/soc/reg_base.h
+3 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -76,3 +76,5 @@
#define DR_REG_CPU_BUS_MONITOR_BASE 0x600C2000
#define DR_REG_INTPRI_BASE 0x600C5000
#define DR_REG_EXTMEM_BASE 0x600C8000
#define PWDET_CONF_REG 0x600A8010
components/soc/esp32h2/adc_periph.c
+5 -5
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@@ -10,10 +10,10 @@
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM
ADC1_CHANNEL_0_GPIO_NUM,
ADC1_CHANNEL_1_GPIO_NUM,
ADC1_CHANNEL_2_GPIO_NUM,
ADC1_CHANNEL_3_GPIO_NUM,
ADC1_CHANNEL_4_GPIO_NUM,
},
/* ADC2 */
{
ADC2_CHANNEL_0_GPIO_NUM, -1, -1, -1, -1
}
};
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+20 -4
View File
@@ -3,6 +3,10 @@
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_ADC_SUPPORTED
bool
default y
config SOC_DEDICATED_GPIO_SUPPORTED
bool
default y
@@ -143,10 +147,6 @@ config SOC_ADC_DIG_CTRL_SUPPORTED
bool
default y
config SOC_ADC_ARBITER_SUPPORTED
bool
default y
config SOC_ADC_DIG_IIR_FILTER_SUPPORTED
bool
default y
@@ -155,6 +155,10 @@ config SOC_ADC_MONITOR_SUPPORTED
bool
default y
config SOC_ADC_DMA_SUPPORTED
bool
default y
config SOC_ADC_PERIPH_NUM
int
default 1
@@ -179,6 +183,10 @@ config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 12
config SOC_ADC_DIGI_MIN_BITWIDTH
int
default 12
config SOC_ADC_DIGI_IIR_FILTER_NUM
int
default 2
@@ -187,6 +195,14 @@ config SOC_ADC_DIGI_MONITOR_NUM
int
default 2
config SOC_ADC_DIGI_RESULT_BYTES
int
default 4
config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
int
default 4
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
components/soc/esp32h2/include/soc/adc_channel.h
+10 -13
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@@ -6,20 +6,17 @@
#pragma once
#define ADC1_GPIO0_CHANNEL 0
#define ADC1_CHANNEL_0_GPIO_NUM 0
#define ADC1_GPIO1_CHANNEL 0
#define ADC1_CHANNEL_0_GPIO_NUM 1
#define ADC1_GPIO1_CHANNEL 1
#define ADC1_CHANNEL_1_GPIO_NUM 1
#define ADC1_GPIO2_CHANNEL 1
#define ADC1_CHANNEL_1_GPIO_NUM 2
#define ADC1_GPIO2_CHANNEL 2
#define ADC1_CHANNEL_2_GPIO_NUM 2
#define ADC1_GPIO3_CHANNEL 2
#define ADC1_CHANNEL_2_GPIO_NUM 3
#define ADC1_GPIO3_CHANNEL 3
#define ADC1_CHANNEL_3_GPIO_NUM 3
#define ADC1_GPIO4_CHANNEL 3
#define ADC1_CHANNEL_3_GPIO_NUM 4
#define ADC1_GPIO4_CHANNEL 4
#define ADC1_CHANNEL_4_GPIO_NUM 4
#define ADC2_GPIO5_CHANNEL 0
#define ADC2_CHANNEL_0_GPIO_NUM 5
#define ADC1_GPIO5_CHANNEL 4
#define ADC1_CHANNEL_4_GPIO_NUM 5
components/soc/esp32h2/include/soc/clk_tree_defs.h
+2 -3
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@@ -367,16 +367,15 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of ADC digital controller
*/
// TODO: temporary support, need to check while supporting
#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F96M}
#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_RC_FAST}
/**
* @brief ADC digital controller clock source
*/
// TODO: temporary support, need to check while supporting
typedef enum {
ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
ADC_DIGI_CLK_SRC_PLL_F96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */
} soc_periph_adc_digi_clk_src_t;
components/soc/esp32h2/include/soc/reg_base.h
+2
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@@ -66,3 +66,5 @@
#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000
#define DR_REG_INTPRI_BASE 0x600C5000
#define DR_REG_EXTMEM_BASE 0x600C8000
#define PWDET_CONF_REG 0x600A8010
components/soc/esp32h2/include/soc/regi2c_saradc.h
+8
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@@ -30,6 +30,14 @@
#define ADC_SAR2_DREF_ADDR_MSB 0x6
#define ADC_SAR2_DREF_ADDR_LSB 0x4
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 3
#define I2C_SARADC_TSENS_DAC_LSB 3
components/soc/esp32h2/include/soc/soc_caps.h
+7 -4
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@@ -25,7 +25,7 @@
#pragma once
/*-------------------------- COMMON CAPS ---------------------------------------*/
// #define SOC_ADC_SUPPORTED 1 // TODO: IDF-6214
#define SOC_ADC_SUPPORTED 1
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_UART_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
@@ -76,15 +76,15 @@
#define SOC_AES_SUPPORT_AES_128 (1)
#define SOC_AES_SUPPORT_AES_256 (1)
// TODO: IDF-6215 (Copy from esp32c6, need check)
/*-------------------------- ADC CAPS -------------------------------*/
/*!< SAR ADC Module*/
#define SOC_ADC_DIG_CTRL_SUPPORTED 1
#define SOC_ADC_ARBITER_SUPPORTED 1
#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
#define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (1U)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (5)
#define SOC_ADC_MAX_CHANNEL_NUM (5)
#define SOC_ADC_ATTEN_NUM (4)
@@ -92,8 +92,11 @@
#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
#define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
#define SOC_ADC_DIGI_RESULT_BYTES (4)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval<= 4095 */
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
+4
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@@ -259,6 +259,10 @@ config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
config SOC_ADC_SELF_HW_CALI_SUPPORTED
bool
default y
config SOC_BROWNOUT_RESET_SUPPORTED
bool
default y
components/soc/esp32s2/include/soc/soc_caps.h
+1
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@@ -117,6 +117,7 @@
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#define SOC_BROWNOUT_RESET_SUPPORTED 1
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+4
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@@ -295,6 +295,10 @@ config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
config SOC_ADC_SELF_HW_CALI_SUPPORTED
bool
default y
config SOC_APB_BACKUP_DMA
bool
default y
components/soc/esp32s3/include/soc/soc_caps.h
+1 -1
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@@ -109,7 +109,7 @@
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
#define SOC_APB_BACKUP_DMA (1)