Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 11:10:54 +03:00
Code Issues Packages Projects Releases Wiki Activity

change(parlio_tx): use shift edge instead sample edge

Browse Source 
Made-with: Cursor
This commit is contained in:
Chen Jichang
2026-03-24 11:53:09 +08:00
parent 1ad6fdb5b0
commit 444c14dca2
17 changed files with 68 additions and 60 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_driver_parlio/include/driver/parlio_tx.h
+5 -2
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -35,7 +35,10 @@ typedef struct {
size_t trans_queue_depth; /*!< Depth of internal transaction queue */
size_t max_transfer_size; /*!< Maximum transfer size in one transaction, in bytes. This decides the number of DMA nodes will be used for each transaction */
size_t dma_burst_size; /*!< DMA burst size, in bytes */
parlio_sample_edge_t sample_edge; /*!< Parallel IO sample edge */
union {
parlio_sample_edge_t sample_edge __attribute__((deprecated("Please use `shift_edge` instead"))); /*!< Parallel IO sample edge */
parlio_shift_edge_t shift_edge; /*!< Parallel IO Tx shift edge */
};
parlio_bit_pack_order_t bit_pack_order; /*!< Set the order of packing the bits into bytes (only works when `data_width` < 8) */
struct {
uint32_t clk_gate_en: 1; /*!< Enable TX clock gating,
components/esp_driver_parlio/src/parlio_tx.c
+3 -3
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -340,8 +340,8 @@ esp_err_t parlio_new_tx_unit(const parlio_tx_unit_config_t *config, parlio_tx_un
if (data_width < 8) {
parlio_ll_tx_set_bit_pack_order(hal->regs, config->bit_pack_order);
}
// set sample clock edge
parlio_ll_tx_set_sample_clock_edge(hal->regs, config->sample_edge);
parlio_ll_tx_set_shift_clock_edge(hal->regs, config->shift_edge);
// clear any pending interrupt
parlio_ll_clear_interrupt_status(hal->regs, PARLIO_LL_EVENT_TX_MASK);
components/esp_driver_parlio/test_apps/parlio/main/test_parlio_bitscrambler.c
+1 -1
View File
@@ -59,7 +59,7 @@ static void test_parlio_bitscrambler(void)
.trans_queue_depth = 8,
.max_transfer_size = 128,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_NEG,
};
parlio_rx_unit_handle_t rx_unit = NULL;
components/esp_driver_parlio/test_apps/parlio/main/test_parlio_sleep.c
+1 -1
View File
@@ -50,7 +50,7 @@ static void test_parlio_sleep_retention(bool allow_pd)
.trans_queue_depth = 8,
.max_transfer_size = 128,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_POS,
.flags.allow_pd = allow_pd,
};
TEST_ESP_OK(parlio_new_tx_unit(&tx_config, &tx_unit));
components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c
+10 -10
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -97,7 +97,7 @@ TEST_CASE("parallel_tx_unit_trans_done_event", "[parlio_tx]")
.trans_queue_depth = 8,
.max_transfer_size = 128,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_POS,
};
TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
TEST_ESP_OK(parlio_tx_unit_enable(tx_unit));
@@ -149,7 +149,7 @@ TEST_CASE("parallel_tx_unit_enable_disable", "[parlio_tx]")
.trans_queue_depth = 4,
.max_transfer_size = 256,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_POS,
};
TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
TEST_ESP_OK(parlio_tx_unit_enable(tx_unit));
@@ -210,7 +210,7 @@ TEST_CASE("parallel_tx_unit_idle_value", "[parlio_tx]")
.trans_queue_depth = 4,
.max_transfer_size = 64,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_POS,
};
TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
TEST_ESP_OK(parlio_tx_unit_enable(tx_unit));
@@ -262,7 +262,7 @@ TEST_CASE("parallel_tx_clock_gating", "[paralio_tx]")
.trans_queue_depth = 4,
.max_transfer_size = 64,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_POS,
.flags.clk_gate_en = true, // enable clock gating, controlled by the level of TEST_DATA7_GPIO
};
TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
@@ -325,7 +325,7 @@ TEST_CASE("parallel_tx_clock_gating_and_msb_coexist", "[paralio_tx]")
.trans_queue_depth = 4,
.max_transfer_size = 256,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_POS,
.valid_start_delay = 5,
.valid_stop_delay = 5,
.flags.clk_gate_en = true, // enable clock gating, controlled by the CS signal
@@ -390,7 +390,7 @@ TEST_CASE("parlio_tx_can_transmit_PSRAM_buffer", "[parlio_tx]")
.trans_queue_depth = 4,
.max_transfer_size = 65535,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_POS,
.flags.clk_gate_en = true,
};
@@ -512,7 +512,7 @@ TEST_CASE("parallel tx unit use external non-free running clock", "[parlio_tx]")
.trans_queue_depth = 8,
.max_transfer_size = 256,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_POS,
};
uint8_t test_round = 50;
@@ -571,7 +571,7 @@ TEST_CASE("parlio_tx_loop_transmission", "[parlio_tx]")
.trans_queue_depth = 3,
.max_transfer_size = 256,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_POS,
};
TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
@@ -670,7 +670,7 @@ TEST_CASE("parlio_tx can transmit buffer larger than max_size decided by datalen
.trans_queue_depth = 1,
.max_transfer_size = 100 * 1024,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_POS,
.flags.clk_gate_en = true,
};
components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx_cache_safe.c
+1 -1
View File
@@ -39,7 +39,7 @@ static void test_parlio_tx_cache_safe(void)
.trans_queue_depth = 4,
.max_transfer_size = 65535,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_POS,
};
TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
components/esp_hal_parlio/esp32c5/include/hal/parlio_ll.h
+6 -7
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -562,16 +562,15 @@ static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t sta
}
/**
* @brief Set the sample clock edge
* @brief Set the shift clock edge
*
* @param dev Parallel IO register base address
* @param edge Sample clock edge
* @param edge Shift clock edge
*/
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
static inline void parlio_ll_tx_set_shift_clock_edge(parl_io_dev_t *dev, parlio_shift_edge_t edge)
{
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->tx_clk_cfg.tx_clk_i_inv = invert;
dev->tx_clk_cfg.tx_clk_o_inv = invert;
dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = edge;
}
/**
components/esp_hal_parlio/esp32c6/include/hal/parlio_ll.h
+4 -4
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -533,12 +533,12 @@ static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t sta
}
/**
* @brief Set the sample clock edge
* @brief Set the shift clock edge
*
* @param dev Parallel IO register base address
* @param edge Sample clock edge
* @param edge Shift clock edge
*/
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
static inline void parlio_ll_tx_set_shift_clock_edge(parl_io_dev_t *dev, parlio_shift_edge_t edge)
{
dev->tx_cfg0.tx_smp_edge_sel = edge;
}
components/esp_hal_parlio/esp32h2/include/hal/parlio_ll.h
+6 -7
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -569,16 +569,15 @@ static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t sta
}
/**
* @brief Set the sample clock edge
* @brief Set the shift clock edge
*
* @param dev Parallel IO register base address
* @param edge Sample clock edge
* @param edge Shift clock edge
*/
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
static inline void parlio_ll_tx_set_shift_clock_edge(parl_io_dev_t *dev, parlio_shift_edge_t edge)
{
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->tx_clk_cfg.tx_clk_i_inv = invert;
dev->tx_clk_cfg.tx_clk_o_inv = invert;
dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = edge;
}
/**
components/esp_hal_parlio/esp32h4/include/hal/parlio_ll.h
+4 -4
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -561,12 +561,12 @@ static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t sta
}
/**
* @brief Set the sample clock edge
* @brief Set the shift clock edge
*
* @param dev Parallel IO register base address
* @param edge Sample clock edge
* @param edge Shift clock edge
*/
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
static inline void parlio_ll_tx_set_shift_clock_edge(parl_io_dev_t *dev, parlio_shift_edge_t edge)
{
dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = edge;
components/esp_hal_parlio/esp32p4/include/hal/parlio_ll.h
+6 -7
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -623,16 +623,15 @@ static inline void parlio_ll_tx_start(parl_io_dev_t *dev, bool en)
}
/**
* @brief Set the sample clock edge
* @brief Set the shift clock edge
*
* @param dev Parallel IO register base address
* @param edge Sample clock edge
* @param edge Shift clock edge
*/
static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge)
static inline void parlio_ll_tx_set_shift_clock_edge(parl_io_dev_t *dev, parlio_shift_edge_t edge)
{
bool invert = edge == PARLIO_SAMPLE_EDGE_NEG;
dev->tx_clk_cfg.tx_clk_i_inv = invert;
dev->tx_clk_cfg.tx_clk_o_inv = invert;
dev->tx_clk_cfg.tx_clk_i_inv = edge;
dev->tx_clk_cfg.tx_clk_o_inv = edge;
}
/**
components/esp_hal_parlio/include/hal/parlio_types.h
+10 -2
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,13 +16,21 @@ extern "C" {
#endif
/**
* @brief Parallel IO sample edge
* @brief Parallel IO Rx sample edge
*/
typedef enum {
PARLIO_SAMPLE_EDGE_NEG, /*!< Sample data on falling edge of clock */
PARLIO_SAMPLE_EDGE_POS, /*!< Sample data on rising edge of clock */
} parlio_sample_edge_t;
/**
* @brief Parallel IO Tx shift edge
*/
typedef enum {
PARLIO_SHIFT_EDGE_POS, /*!< Shift data on rising edge of clock */
PARLIO_SHIFT_EDGE_NEG, /*!< Shift data on falling edge of clock */
} parlio_shift_edge_t;
/**
* @brief Parallel IO bit packing order
*
components/esp_lcd/parl/esp_lcd_panel_io_parl.c
+1 -1
View File
@@ -115,7 +115,7 @@ esp_err_t esp_lcd_new_panel_io_parl(const esp_lcd_panel_io_parl_config_t *io_con
.output_clk_freq_hz = io_config->pclk_hz,
.trans_queue_depth = io_config->trans_queue_depth ? io_config->trans_queue_depth : 4,
.max_transfer_size = io_config->max_transfer_bytes,
.sample_edge = PARLIO_SAMPLE_EDGE_POS,
.shift_edge = PARLIO_SHIFT_EDGE_NEG,
.bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB,
.dma_burst_size = io_config->dma_burst_size,
.flags.invert_valid_out = !io_config->flags.cs_active_high,