Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-09-22 13:01:16 +03:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'refactor/dac_priv_dma_callbacks_v6.1' into 'release/v6.1'

Browse Source 
refactor(dac): move DMA interrupt handling behind dac_priv_dma callbacks (v6.1)

See merge request espressif/esp-idf!52150
This commit is contained in:
morris
2026-08-28 10:15:29 +08:00
parent f0cfc287b6 f7dc7a638d
commit 43e6da1796
9 changed files with 332 additions and 263 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
docs/en/api-reference/peripherals/dac.rst
View File

@@ -87,7 +87,7 @@ The following diagram illustrates the life cycle of the DAC continuous driver an
The clock of the DAC digital controller comes from I2S0 as well, so there are two clock sources for selection:
- :cpp:enumerator:`dac_continuous_digi_clk_src_t::DAC_DIGI_CLK_SRC_PLL_D2` supports frequency between 19.6 KHz to several MHz. It is the default clock which can also be selected by :cpp:enumerator:`dac_continuous_digi_clk_src_t::DAC_DIGI_CLK_SRC_DEFAULT`.
- :cpp:enumerator:`dac_continuous_digi_clk_src_t::DAC_DIGI_CLK_SRC_PLL_160M` supports frequency between 19.6 KHz to several MHz. It is the default clock which can also be selected by :cpp:enumerator:`dac_continuous_digi_clk_src_t::DAC_DIGI_CLK_SRC_DEFAULT`.
- :cpp:enumerator:`dac_continuous_digi_clk_src_t::DAC_DIGI_CLK_SRC_APLL` supports frequency between 648 Hz to several MHz. However, it might be occupied by other peripherals, thus not providing the required frequency. In such case, this clock source is available only if APLL still can be correctly divided into the target DAC DMA frequency.
.. only:: esp32s2