feat(etm): add ETM LL and GPIO ETM support on esp32s31

Enable ETM caps and add S31 ETM/GPIO LL and retention support for GPTimer ETM builds.
2026-10-02 03:00:34 +03:00 · 2026-04-07 14:47:36 +08:00
parent 953c40c9aa
commit 43bc8c2fe5
56 changed files with 754 additions and 1268 deletions
@@ -0,0 +1,44 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "hal/etm_periph.h"
+#include "soc/soc_etm_reg.h"
+
+/**
+ * ETM Registers to be saved during sleep retention
+ * - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG
+ */
+#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1)
+
+static const regdma_entries_config_t etm_regdma_entries[] = {
+    // backup stage: save the status of enabled channels
+    // restore stage: store the enabled channels
+    [0] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00),
+                                              SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+    [1] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01),
+                                              SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [2] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02),
+                                              SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+};
+
+const soc_etm_retention_desc_t soc_etm_retention_info[1] = {
+    [0] = {
+        .module = SLEEP_RETENTION_MODULE_ETM0,
+        .regdma_entry_array = etm_regdma_entries,
+        .array_size = ARRAY_SIZE(etm_regdma_entries)
+    },
+};
@@ -0,0 +1,169 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+
+#include <stdbool.h>
+#include "hal/assert.h"
+#include "hal/misc.h"
+#include "hal/etm_types.h"
+#include "soc/soc_etm_struct.h"
+#include "soc/hp_sys_clkrst_struct.h"
+
+#define ETM_LL_GET(_attr) ETM_LL_ ## _attr
+#define ETM_LL_SUPPORT(_feat) ETM_LL_SUPPORT_ ## _feat
+
+// Number of ETM instances
+#define ETM_LL_INST_NUM 1
+
+// Number of channels in each ETM instance
+#define ETM_LL_CHANS_PER_INST 50
+
+// Support to get and clear the status of the ETM event and task
+#define ETM_LL_SUPPORT_STATUS_REG  1
+
+// Support to set the clock source for ETM
+#define ETM_LL_SUPPORT_CLOCK_SRC   1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Enable the clock for ETM register
+ *
+ * @param group_id Group ID
+ * @param enable true to enable, false to disable
+ */
+static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
+{
+    (void)group_id;
+    HP_SYS_CLKRST.etm_ctrl0.reg_etm_apb_clk_en = enable;
+}
+
+/**
+ * @brief Enable the clock for ETM function
+ *
+ * @param group_id Group ID
+ * @param enable true to enable, false to disable
+ */
+static inline void etm_ll_enable_function_clock(int group_id, bool enable)
+{
+    (void)group_id;
+    HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_en = enable;
+}
+
+/**
+ * @brief Set the clock source for ETM
+ *
+ * @param group_id Group ID
+ * @param clk_src Clock source
+ */
+static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_src)
+{
+    (void)group_id;
+    switch (clk_src) {
+    case ETM_CLK_SRC_XTAL:
+        HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_sel = 0;
+        break;
+    case ETM_CLK_SRC_RC_FAST:
+        HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_sel = 1;
+        break;
+    case ETM_CLK_SRC_PLL_F80M:
+        HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_sel = 2;
+        break;
+    default:
+        HAL_ASSERT(false);
+    }
+}
+
+/**
+ * @brief Reset the ETM register
+ *
+ * @param group_id Group ID
+ */
+static inline void etm_ll_reset_register(int group_id)
+{
+    (void)group_id;
+    HP_SYS_CLKRST.etm_ctrl0.reg_etm_rst_en = 1;
+    HP_SYS_CLKRST.etm_ctrl0.reg_etm_rst_en = 0;
+}
+
+/**
+ * @brief Enable ETM channel
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ */
+static inline void etm_ll_enable_channel(soc_etm_dev_t *hw, uint32_t chan)
+{
+    if (chan < 32) {
+        hw->ch_ena_ad0_set.val = 1 << chan;
+    } else {
+        hw->ch_ena_ad1_set.val = 1 << (chan - 32);
+    }
+}
+
+/**
+ * @brief Disable ETM channel
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ */
+static inline void etm_ll_disable_channel(soc_etm_dev_t *hw, uint32_t chan)
+{
+    if (chan < 32) {
+        hw->ch_ena_ad0_clr.val = 1 << chan;
+    } else {
+        hw->ch_ena_ad1_clr.val = 1 << (chan - 32);
+    }
+}
+
+/**
+ * @brief Check whether the ETM channel is enabled or not
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ * @return true if the channel is enabled, false otherwise
+ */
+static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan)
+{
+    if (chan < 32) {
+        return hw->ch_ena_ad0.val & (1 << chan);
+    } else {
+        return hw->ch_ena_ad1.val & (1 << (chan - 32));
+    }
+}
+
+/**
+ * @brief Set the input event for the ETM channel
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ * @param event Event ID
+ */
+static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event)
+{
+    hw->channel[chan].eid.chn_evt_id = event;
+}
+
+/**
+ * @brief Set the output task for the ETM channel
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ * @param task Task ID
+ */
+static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task)
+{
+    hw->channel[chan].tid.chn_task_id = task;
+}
+
+#ifdef __cplusplus
+}
+#endif