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feat(esp_tee): Add support for the RISC-V H/W stack guard mechanism

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Laukik Hase
2026-01-29 11:49:14 +05:30
parent 39f392f943
commit 421246323a
16 changed files with 524 additions and 84 deletions
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components/esp_system/port/include/private/esp_private/hw_stack_guard.h
+62 -10
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -39,10 +39,10 @@ uint32_t esp_hw_stack_guard_get_pc(uint32_t core_id);
#define ASSIST_DEBUG_CORE_0_SP_MAX_OFFSET (ASSIST_DEBUG_CORE_0_SP_MAX_REG - DR_REG_ASSIST_DEBUG_BASE)
#define ASSIST_DEBUG_CORE_0_SP_SPILL_OFFSET (ASSIST_DEBUG_CORE_0_MONITOR_REG - DR_REG_ASSIST_DEBUG_BASE)
.macro ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0 reg1
.macro ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0 reg1 sp_min sp_max
lui \reg1, ASSIST_DEBUG_CORE_0_MONITOR_REG_IMM
sw a0, ASSIST_DEBUG_CORE_0_SP_MIN_OFFSET(\reg1)
sw a1, ASSIST_DEBUG_CORE_0_SP_MAX_OFFSET(\reg1)
sw \sp_min, ASSIST_DEBUG_CORE_0_SP_MIN_OFFSET(\reg1)
sw \sp_max, ASSIST_DEBUG_CORE_0_SP_MAX_OFFSET(\reg1)
.endm
.macro ESP_HW_STACK_GUARD_MONITOR_STOP_CPU0 reg1 reg2
@@ -59,6 +59,18 @@ ori \reg2, \reg2, ASSIST_DEBUG_SP_SPILL_BITS
sw \reg2, ASSIST_DEBUG_CORE_0_SP_SPILL_OFFSET(\reg1)
.endm
.macro ESP_HW_STACK_GUARD_GET_BOUNDS_CPU0 reg1 sp_min sp_max
lui \reg1, ASSIST_DEBUG_CORE_0_MONITOR_REG_IMM
lw \sp_min, ASSIST_DEBUG_CORE_0_SP_MIN_OFFSET(\reg1)
lw \sp_max, ASSIST_DEBUG_CORE_0_SP_MAX_OFFSET(\reg1)
.endm
.macro ESP_HW_STACK_GUARD_MONITOR_QUERY_CPU0 reg1 reg2
lui \reg1, ASSIST_DEBUG_CORE_0_MONITOR_REG_IMM
lw \reg2, ASSIST_DEBUG_CORE_0_SP_SPILL_OFFSET(\reg1)
andi \reg2, \reg2, ASSIST_DEBUG_SP_SPILL_BITS
.endm
#if SOC_CPU_CORES_NUM > 1
#define ASSIST_DEBUG_CORE_1_MONITOR_REG_IMM (ASSIST_DEBUG_CORE_1_MONITOR_REG >> 12)
@@ -66,10 +78,10 @@ sw \reg2, ASSIST_DEBUG_CORE_0_SP_SPILL_OFFSET(\reg1)
#define ASSIST_DEBUG_CORE_1_SP_MAX_OFFSET (ASSIST_DEBUG_CORE_1_SP_MAX_REG - DR_REG_ASSIST_DEBUG_BASE)
#define ASSIST_DEBUG_CORE_1_SP_SPILL_OFFSET (ASSIST_DEBUG_CORE_1_MONITOR_REG - DR_REG_ASSIST_DEBUG_BASE)
.macro ESP_HW_STACK_GUARD_SET_BOUNDS_CPU1 reg1
.macro ESP_HW_STACK_GUARD_SET_BOUNDS_CPU1 reg1 sp_min sp_max
lui \reg1, ASSIST_DEBUG_CORE_1_MONITOR_REG_IMM
sw a0, ASSIST_DEBUG_CORE_1_SP_MIN_OFFSET(\reg1)
sw a1, ASSIST_DEBUG_CORE_1_SP_MAX_OFFSET(\reg1)
sw \sp_min, ASSIST_DEBUG_CORE_1_SP_MIN_OFFSET(\reg1)
sw \sp_max, ASSIST_DEBUG_CORE_1_SP_MAX_OFFSET(\reg1)
.endm
.macro ESP_HW_STACK_GUARD_MONITOR_STOP_CPU1 reg1 reg2
@@ -86,16 +98,28 @@ ori \reg2, \reg2, ASSIST_DEBUG_SP_SPILL_BITS
sw \reg2, ASSIST_DEBUG_CORE_1_SP_SPILL_OFFSET(\reg1)
.endm
.macro ESP_HW_STACK_GUARD_SET_BOUNDS_CUR_CORE reg1
.macro ESP_HW_STACK_GUARD_GET_BOUNDS_CPU1 reg1 sp_min sp_max
lui \reg1, ASSIST_DEBUG_CORE_1_MONITOR_REG_IMM
lw \sp_min, ASSIST_DEBUG_CORE_1_SP_MIN_OFFSET(\reg1)
lw \sp_max, ASSIST_DEBUG_CORE_1_SP_MAX_OFFSET(\reg1)
.endm
.macro ESP_HW_STACK_GUARD_MONITOR_QUERY_CPU1 reg1 reg2
lui \reg1, ASSIST_DEBUG_CORE_1_MONITOR_REG_IMM
lw \reg2, ASSIST_DEBUG_CORE_1_SP_SPILL_OFFSET(\reg1)
andi \reg2, \reg2, ASSIST_DEBUG_SP_SPILL_BITS
.endm
.macro ESP_HW_STACK_GUARD_SET_BOUNDS_CUR_CORE reg1 sp_min sp_max
/* Check the current core ID */
csrr \reg1, mhartid
beqz \reg1, 1f
/* Core 1 */
ESP_HW_STACK_GUARD_SET_BOUNDS_CPU1 \reg1
ESP_HW_STACK_GUARD_SET_BOUNDS_CPU1 \reg1 \sp_min \sp_max
j 2f
1:
/* Core 0 */
ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0 \reg1
ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0 \reg1 \sp_min \sp_max
2:
.endm
@@ -125,11 +149,39 @@ ESP_HW_STACK_GUARD_MONITOR_STOP_CPU0 \reg1 \reg2
2:
.endm
.macro ESP_HW_STACK_GUARD_GET_BOUNDS_CUR_CORE reg1 sp_min sp_max
/* Check the current core ID */
csrr \reg1, mhartid
beqz \reg1, 1f
/* Core 1 */
ESP_HW_STACK_GUARD_GET_BOUNDS_CPU1 \reg1 \sp_min \sp_max
j 2f
1:
/* Core 0 */
ESP_HW_STACK_GUARD_GET_BOUNDS_CPU0 \reg1 \sp_min \sp_max
2:
.endm
.macro ESP_HW_STACK_GUARD_MONITOR_QUERY_CUR_CORE reg1 reg2
/* Check the current core ID */
csrr \reg1, mhartid
beqz \reg1, 1f
/* Core 1 */
ESP_HW_STACK_GUARD_MONITOR_QUERY_CPU1 \reg1 \reg2
j 2f
1:
/* Core 0 */
ESP_HW_STACK_GUARD_MONITOR_QUERY_CPU0 \reg1 \reg2
2:
.endm
#else // SOC_CPU_CORES_NUM <= 1
#define ESP_HW_STACK_GUARD_SET_BOUNDS_CUR_CORE ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0
#define ESP_HW_STACK_GUARD_MONITOR_START_CUR_CORE ESP_HW_STACK_GUARD_MONITOR_START_CPU0
#define ESP_HW_STACK_GUARD_MONITOR_STOP_CUR_CORE ESP_HW_STACK_GUARD_MONITOR_STOP_CPU0
#define ESP_HW_STACK_GUARD_GET_BOUNDS_CUR_CORE ESP_HW_STACK_GUARD_GET_BOUNDS_CPU0
#define ESP_HW_STACK_GUARD_MONITOR_QUERY_CUR_CORE ESP_HW_STACK_GUARD_MONITOR_QUERY_CPU0
#endif // SOC_CPU_CORES_NUM > 1