Merge branch 'fix/32mb_120m' into 'master'

fix(spi_flash): 1. Fix flash 120m in qio mode failed on esp32p4 (with 32M map enabled) 2. Add C61 32M flash support

See merge request espressif/esp-idf!45433

components/bootloader_support/bootloader_flash/src/bootloader_flash.c

@@ -130,6 +130,8 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
 #include "esp32p4/rom/opi_flash.h"
 #elif CONFIG_IDF_TARGET_ESP32C5
 #include "esp32c5/rom/opi_flash.h"
+#elif CONFIG_IDF_TARGET_ESP32C61
+#include "esp32c61/rom/opi_flash.h"
 #endif
 #include "esp_flash_chips/spi_flash_defs.h"
 
@@ -290,7 +292,7 @@ static void rom_read_api_workaround(void)
  */
 static inline bool spi1_wb_mode_save_and_disable(void)
 {
-#if SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
+#if SPI_FLASH_LL_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
     if (REG_GET_BIT(SPI_MEM_RD_STATUS_REG(1), SPI_MEM_WB_MODE_EN)) {
         REG_CLR_BIT(SPI_MEM_RD_STATUS_REG(1), SPI_MEM_WB_MODE_EN);
         return true;
@@ -301,7 +303,7 @@ static inline bool spi1_wb_mode_save_and_disable(void)
 
 static inline void spi1_wb_mode_restore(bool saved_state)
 {
-#if SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
+#if SPI_FLASH_LL_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
     if (saved_state) {
         REG_SET_BIT(SPI_MEM_RD_STATUS_REG(1), SPI_MEM_WB_MODE_EN);
     }

components/esp_hal_mspi/esp32c5/include/hal/spi_flash_ll.h

@@ -35,6 +35,7 @@ extern "C" {
                                      }\
                                      dev_id; \
                                     })
+#define SPI_FLASH_LL_SUPPORT_WB_MODE_INDEPENDENT_CONTROL   (1)
 // Since ESP32-C5, WB_mode is available, we extend 8 bits to occupy `Continuous Read Mode` bits.
 #define SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS  (8)
 

components/esp_hal_mspi/esp32c61/include/hal/spi_flash_ll.h

@@ -35,6 +35,7 @@ extern "C" {
                                      }\
                                      dev_id; \
                                     })
+#define SPI_FLASH_LL_SUPPORT_WB_MODE_INDEPENDENT_CONTROL   (1)
 // Since ESP32-C61, WB_mode is available, we extend 8 bits to occupy `Continuous Read Mode` bits.
 #define SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS  (8)
 
@@ -68,6 +69,7 @@ typedef union  {
 #define spi_flash_ll_set_hold(dev, hold_n)                   gpspi_flash_ll_set_hold((spi_dev_t*)dev, hold_n)
 #define spi_flash_ll_set_cs_setup(dev, cs_setup_time)        gpspi_flash_ll_set_cs_setup((spi_dev_t*)dev, cs_setup_time)
 #define spi_flash_ll_set_extra_address(dev, extra_addr)      { /* Not supported on gpspi on ESP32-C61*/ }
+#define spi_flash_ll_wb_mode_enable(dev, wb_mode_enable)     { /* Not supported on gpspi on ESP32-C61*/ }
 #else
 #define spi_flash_ll_reset(dev)                              spimem_flash_ll_reset((spi_mem_dev_t*)dev)
 #define spi_flash_ll_cmd_is_done(dev)                        spimem_flash_ll_cmd_is_done((spi_mem_dev_t*)dev)
@@ -101,6 +103,7 @@ typedef union  {
 #define spi_flash_ll_sync_reset()                            spimem_flash_ll_sync_reset()
 #define spi_flash_ll_set_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg)        spimem_flash_ll_set_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
 #define spi_flash_ll_get_common_command_register_info(dev, ctrl_reg, user_reg, user1_reg, user2_reg)        spimem_flash_ll_get_common_command_register_info((spi_mem_dev_t*)dev, ctrl_reg, user_reg, user1_reg, user2_reg)
+#define spi_flash_ll_wb_mode_enable(dev, wb_mode_enable)     spimem_flash_ll_wb_mode_enable((spi_mem_dev_t*)dev, wb_mode_enable)
 
 #endif
 

components/esp_hal_mspi/esp32c61/include/hal/spimem_flash_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -577,6 +577,7 @@ static inline int spimem_flash_ll_get_addr_bitlen(spi_mem_dev_t *dev)
 __attribute__((always_inline))
 static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t bitlen)
 {
+    dev->cache_fctrl.cache_usr_addr_4byte = (bitlen == 32) ? 1 : 0;
     dev->user1.usr_addr_bitlen = (bitlen - 1);
     dev->user.usr_addr = bitlen ? 1 : 0;
 }
@@ -589,8 +590,19 @@ static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t
  */
 static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr)
 {
-    dev->cache_fctrl.cache_usr_addr_4byte = 0;
     HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rd_status, wb_mode, extra_addr);
+    dev->rd_status.wb_mode_bitlen = 7;  // 8 - 1
+}
+
+/**
+ * Enable extra address for bits M0-M7 in DIO/QIO mode.
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param wb_mode_enable true for enabling wb_mode
+ */
+static inline void spimem_flash_ll_wb_mode_enable(spi_mem_dev_t *dev, bool wb_mode_enable)
+{
+    dev->rd_status.wb_mode_en = wb_mode_enable;
 }
 
 /**

components/esp_hal_mspi/spi_flash_hal_common.inc

@@ -125,11 +125,11 @@ esp_err_t spi_flash_hal_configure_host_io_mode(
     if (conf_required) {
         int line_width = (io_mode == SPI_FLASH_DIO ? 2 : 4);
         dummy_cyclelen_base -= SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS / line_width;
-#if !SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
+#if !SPI_FLASH_LL_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
         addr_bitlen += SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS;
 #endif
         spi_flash_ll_set_extra_address(dev, 0);
-#if SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
+#if SPI_FLASH_LL_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
         spi_flash_ll_wb_mode_enable(dev, true);
 #endif
     }
@@ -208,7 +208,7 @@ esp_err_t spi_flash_hal_common_command(spi_flash_host_inst_t *host, spi_flash_tr
     if (trans->miso_len > 0) {
         spi_flash_ll_get_buffer_data(dev, trans->miso_data, trans->miso_len);
     }
-#if SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
+#if SPI_FLASH_LL_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
     spi_flash_ll_wb_mode_enable(dev, false);
 #endif
     return ESP_OK;

components/esp_hw_support/mspi/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_flash_delay.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -24,6 +24,7 @@
 #include "esp_private/mspi_timing_config.h"
 #include "hal/mspi_ll.h"
 #include "rom/spi_flash.h"
+#include "esp_private/spi_flash_os.h"
 
 ESP_LOG_ATTR_TAG(TAG, "Flash Delay");
 
@@ -152,6 +153,50 @@ void mspi_timing_flash_config_clear_tuning_regs(bool control_both_mspi)
     }
 }
 
+#if MSPI_TIMING_FLASH_NEEDS_TUNING && CONFIG_SPI_FLASH_HPM_ON
+static uint32_t spi_timing_config_get_dummy(void)
+{
+    mspi_timing_ll_flash_mode_t mode = mspi_timing_ll_get_flash_mode(0);
+
+    if (spi_flash_hpm_dummy_adjust()) { // HPM-DC is enabled
+        const spi_flash_hpm_dummy_conf_t *hpm_dummy = spi_flash_hpm_get_dummy();
+        switch (mode) {
+            case MSPI_TIMING_LL_FLASH_QIO_MODE:
+                return hpm_dummy->qio_dummy - 1;
+            case MSPI_TIMING_LL_FLASH_QUAD_MODE:
+                return hpm_dummy->qout_dummy - 1;
+            case MSPI_TIMING_LL_FLASH_DIO_MODE:
+                return hpm_dummy->dio_dummy - 1;
+            case MSPI_TIMING_LL_FLASH_DUAL_MODE:
+                return hpm_dummy->dout_dummy - 1;
+            case MSPI_TIMING_LL_FLASH_FAST_MODE:
+                return hpm_dummy->fastrd_dummy - 1;
+            case MSPI_TIMING_LL_FLASH_SLOW_MODE:
+                return 0;
+            default:
+                abort();
+        }
+    } else { // HPM-DC is not enabled
+        switch (mode) {
+            case MSPI_TIMING_LL_FLASH_QIO_MODE:
+                return SPI1_R_QIO_DUMMY_CYCLELEN;
+            case MSPI_TIMING_LL_FLASH_QUAD_MODE:
+                return SPI1_R_FAST_DUMMY_CYCLELEN;
+            case MSPI_TIMING_LL_FLASH_DIO_MODE:
+                return SPI1_R_DIO_DUMMY_CYCLELEN;
+            case MSPI_TIMING_LL_FLASH_DUAL_MODE:
+                return SPI1_R_FAST_DUMMY_CYCLELEN;
+            case MSPI_TIMING_LL_FLASH_FAST_MODE:
+                return SPI1_R_FAST_DUMMY_CYCLELEN;
+            case MSPI_TIMING_LL_FLASH_SLOW_MODE:
+                return 0;
+            default:
+                abort();
+        }
+    }
+}
+#endif // MSPI_TIMING_FLASH_NEEDS_TUNING && CONFIG_SPI_FLASH_HPM_ON
+
 void mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi)
 {
     //SPI0 and SPI1 share the registers for flash din mode and num setting, so we only set SPI0's reg
@@ -164,8 +209,17 @@ void mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi)
         //Won't touch SPI1 registers
     }
 
-#if MSPI_TIMING_FLASH_NEEDS_TUNING && CONFIG_ESPTOOLPY_FLASHMODE_QIO && CONFIG_SPI_FLASH_HPM_ON
+#if MSPI_TIMING_FLASH_NEEDS_TUNING && CONFIG_SPI_FLASH_HPM_ON
-    mspi_timing_ll_set_flash_user_dummy(MSPI_TIMING_LL_MSPI_ID_0, 7);
+    uint32_t dummy_len = spi_timing_config_get_dummy();
+#if CONFIG_ESPTOOLPY_FLASHMODE_QIO && !CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH
+    // In the ROM configuration, when esp_rom_spi_set_rd_cmd_bit_len issues the read command in QIO mode, it automatically inserts two dummy cycles.
+    // Therefore, when validating the dummy cycles at 120 MHz, the effective value should be 10 − 2, i.e. 8 dummy cycles.
+    // However, when the 32 MHz cache access configuration is enabled, the corresponding register will be overwritten,
+    // so the extra two dummy cycles no longer exist. In that case, the dummy cycle setting should simply be 10.
+    mspi_timing_ll_set_flash_user_dummy(MSPI_TIMING_LL_MSPI_ID_0, dummy_len - 2);
+#else
+    mspi_timing_ll_set_flash_user_dummy(MSPI_TIMING_LL_MSPI_ID_0, dummy_len);
+#endif // CONFIG_ESPTOOLPY_FLASHMODE_QIO && !CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH
 #endif
 
     int spi1_usr_dummy = 0;

components/esp_rom/patches/esp_rom_spiflash.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -27,6 +27,9 @@
 #elif CONFIG_IDF_TARGET_ESP32C5
 #include "esp32c5/rom/spi_flash.h"
 #include "esp32c5/rom/opi_flash.h"
+#elif CONFIG_IDF_TARGET_ESP32C61
+#include "esp32c61/rom/spi_flash.h"
+#include "esp32c61/rom/opi_flash.h"
 #endif
 
 #define SPI_IDX   1
@@ -768,7 +771,7 @@ void esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, const
         REG_SET_BIT(SPI_MEM_C_CTRL_REG, SPI_MEM_C_Q_POL);
     }
 }
-#elif CONFIG_IDF_TARGET_ESP32C5
+#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
 extern void esp_rom_spi_set_address_bit_len(int spi, int addr_bits);
 void esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, const esp_rom_opiflash_spi0rd_t *cache)
 {

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -1011,10 +1011,6 @@ config SOC_SPI_MEM_SUPPORT_WRAP
     bool
     default y
 
-config SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL
-    bool
-    default y
-
 config SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP
     bool
     default y

components/soc/esp32c5/include/soc/soc_caps.h

@@ -417,7 +417,6 @@
 #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND                    (1)
 #define SOC_SPI_MEM_SUPPORT_CHECK_SUS                     (1)
 #define SOC_SPI_MEM_SUPPORT_WRAP                          (1)
-#define SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL   (1)
 #define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP          (1)
 #define SOC_SPI_MEM_SUPPORT_TIMING_TUNING                 (1)
 #define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR        (1)

components/soc/esp32c61/include/soc/Kconfig.soc_caps.in

@@ -779,6 +779,10 @@ config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
     bool
     default y
 
+config SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP
+    bool
+    default y
+
 config SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY
     bool
     default y

components/soc/esp32c61/include/soc/soc_caps.h

@@ -327,6 +327,7 @@
 #define SOC_SPI_MEM_SUPPORT_WRAP                          (1)
 #define SOC_SPI_MEM_SUPPORT_TIMING_TUNING                 (1)
 #define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR        (1)
+#define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP          (1)
 #define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY            (1)
 
 #define SOC_MEMSPI_IS_INDEPENDENT                 1

components/spi_flash/spi_flash_hpm_enable.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -222,6 +222,71 @@ static void spi_flash_hpm_get_dummy_xmc(spi_flash_hpm_dummy_conf_t *dummy_conf)
     dummy_conf->qout_dummy = SPI_FLASH_QOUT_DUMMY_BITLEN;
     dummy_conf->fastrd_dummy = SPI_FLASH_FASTRD_DUMMY_BITLEN;
 }
+
+
+/**
+ * @brief Probe the chip whether adjust dummy (bit3,4) to enable HPM mode. Take XMC as an example:
+ *        Adjust dummy bits to enable HPM mode of the flash. If XMC works under 80MHz, the dummy bits
+ *        might be 6, but when works under 120MHz, the dummy bits might be 10.
+ */
+static esp_err_t spi_flash_hpm_probe_chip_with_dummy_bit3_4(uint32_t flash_id)
+{
+    esp_err_t ret = ESP_OK;
+
+    switch (flash_id) {
+    /* The flash listed here should enter the HPM by adjusting dummy cycles */
+    // XMC chips.
+    case 0x204019:
+    case 0x204020:
+        break;
+    default:
+        ret = ESP_ERR_NOT_FOUND;
+        break;
+    }
+    return ret;
+}
+
+static spi_flash_requirement_t spi_flash_hpm_chip_hpm_requirement_check_with_dummy_bit3_4(uint32_t flash_id, uint32_t freq_mhz, int voltage_mv, int temperautre)
+{
+    // voltage and temperature are not been used now, to be completed in the future.
+    (void)voltage_mv;
+    (void)temperautre;
+    spi_flash_requirement_t chip_cap = SPI_FLASH_HPM_UNNEEDED;
+
+    if (freq_mhz >= 104) {
+        chip_cap = SPI_FLASH_HPM_DUMMY_NEEDED;
+    }
+    ESP_EARLY_LOGD(HPM_TAG, "HPM with dummy bit3,4, status is %d", chip_cap);
+    return chip_cap;
+}
+
+/**
+* @brief Adjust dummy cycles. This function modifies the Dummy Cycle Bits in SR3.
+*        Usually, the bits are at bit-0, bit-1, sr-3 and set DC[1:0]=[1,1].
+*
+* @note Don't forget to adjust dummy configurations for MSPI, you can get the
+*       correct dummy from interface `spi_flash_hpm_get_dummy`.
+*/
+static void spi_flash_turn_high_performance_dummy_bit3_4(void)
+{
+    uint8_t old_status_3 = bootloader_read_status_8b_rdsr3();
+    uint8_t new_status = (old_status_3 | 0x18);
+    bootloader_execute_flash_command(CMD_WRENVSR, 0, 0, 0);
+    bootloader_write_status_8b_wrsr3(new_status);
+    esp_rom_spiflash_wait_idle(&g_rom_flashchip);
+}
+
+/**
+* @brief Check whether HPM has been enabled. This function checks the DC bits
+*/
+static esp_err_t spi_flash_high_performance_check_dummy_bit3_4(void)
+{
+    if((bootloader_read_status_8b_rdsr3() & 0x18) == 0) {
+        return ESP_FAIL;
+    }
+    return ESP_OK;
+}
+
 #elif !CONFIG_SPI_FLASH_HPM_DC_DISABLE
 
 //This is because bootloader doesn't support this
@@ -317,9 +382,10 @@ const spi_flash_hpm_info_t __attribute__((weak)) spi_flash_hpm_enable_list[] = {
     /* vendor, chip_id, freq_threshold,  temperature threshold,   operation for setting high performance,         reading HPF status,                         get dummy        */
     { "command",    spi_flash_hpm_probe_chip_with_cmd,     spi_flash_hpm_chip_hpm_requirement_check_with_cmd,        spi_flash_enable_high_performance_send_cmd,       spi_flash_high_performance_check_hpf_bit_5,  spi_flash_hpm_get_dummy_generic },
 #if CONFIG_SPI_FLASH_HPM_DC_ON
-    { "dummy",   spi_flash_hpm_probe_chip_with_dummy,     spi_flash_hpm_chip_hpm_requirement_check_with_dummy,    spi_flash_turn_high_performance_reconfig_dummy,   spi_flash_high_performance_check_dummy_sr,  spi_flash_hpm_get_dummy_xmc},
+    { "dummy sr3-bit01",   spi_flash_hpm_probe_chip_with_dummy,     spi_flash_hpm_chip_hpm_requirement_check_with_dummy,    spi_flash_turn_high_performance_reconfig_dummy,   spi_flash_high_performance_check_dummy_sr,  spi_flash_hpm_get_dummy_xmc},
 #endif //CONFIG_SPI_FLASH_HPM_DC_ON
     { "write sr3-bit5", spi_flash_hpm_probe_chip_with_write_hpf_bit_5, spi_flash_hpm_chip_hpm_requirement_check_with_write_hpf_bit_5, spi_flash_turn_high_performance_write_hpf_bit_5, spi_flash_high_performance_check_hpf_bit_5, spi_flash_hpm_get_dummy_generic},
+    { "dummy sr3-bit3_4", spi_flash_hpm_probe_chip_with_dummy_bit3_4, spi_flash_hpm_chip_hpm_requirement_check_with_dummy_bit3_4, spi_flash_turn_high_performance_dummy_bit3_4, spi_flash_high_performance_check_dummy_bit3_4, spi_flash_hpm_get_dummy_xmc},
     { "noting-to-do", spi_flash_hpm_probe_chip_with_doing_nothing, spi_flash_hpm_chip_hpm_requirement_check_with_doing_nothing, NULL, NULL, spi_flash_hpm_get_dummy_generic},
     // default: do nothing, but keep the dummy get function. The first item with NULL as its probe will be the fallback.
     { "NULL",  NULL,                        NULL,              NULL,                            NULL,                             spi_flash_hpm_get_dummy_generic},

components/spi_flash/test_apps/esp_flash/partitions.csv

@@ -1,5 +1,5 @@
 # Name,     Type, SubType, Offset,   Size, Flags
 # Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap
-nvs,        data, nvs,      0x9000,  0x6000,
+nvs,        data, nvs,      0xb000,  0x6000,
-factory,    0,    0,        0x10000, 1M
+factory,    0,    0,        , 1M
 flash_test, data, fat,      ,        700K

components/spi_flash/test_apps/esp_flash/pytest_esp_flash.py

@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
 import pytest
 from pytest_embedded import Dut
@@ -62,3 +62,51 @@ def test_esp_flash_multi(dut: Dut) -> None:
 @idf_parametrize('target', ['esp32c2'], indirect=['target'])
 def test_esp_flash_26mhz_c2(dut: Dut) -> None:
     dut.run_all_single_board_cases(group='esp_flash')
+
+
+@pytest.mark.flash_32m
+@pytest.mark.parametrize(
+    'config',
+    [
+        'c5_32m_120m_qio_map',
+        'c5_32m_120m_dio_map',
+        'c5_32m_120m_qio',
+        'c5_32m_120m_dio',
+    ],
+    indirect=True,
+)
+@idf_parametrize('target', ['esp32c5'], indirect=['target'])
+def test_esp_flash_32m_c5(dut: Dut) -> None:
+    dut.run_all_single_board_cases(group='esp_flash')
+
+
+@pytest.mark.flash_32m
+@pytest.mark.parametrize(
+    'config',
+    [
+        'c61_32m_120m_qio_map',
+        'c61_32m_120m_dio_map',
+        'c61_32m_120m_qio',
+        'c61_32m_120m_dio',
+    ],
+    indirect=True,
+)
+@idf_parametrize('target', ['esp32c61'], indirect=['target'])
+def test_esp_flash_32m_c61(dut: Dut) -> None:
+    dut.run_all_single_board_cases(group='esp_flash')
+
+
+@pytest.mark.flash_32m
+@pytest.mark.parametrize(
+    'config',
+    [
+        'p4_32m_120m_qio_map',
+        'p4_32m_120m_dio_map',
+        'p4_32m_120m_qio',
+        'p4_32m_120m_dio',
+    ],
+    indirect=True,
+)
+@idf_parametrize('target', ['esp32p4'], indirect=['target'])
+def test_esp_flash_32m_p4(dut: Dut) -> None:
+    dut.run_all_single_board_cases(group='esp_flash')

components/spi_flash/test_apps/esp_flash/sdkconfig.ci.c5_32m_120m_dio

@@ -0,0 +1,12 @@
+CONFIG_IDF_TARGET="esp32c5"
+
+CONFIG_ESP_TASK_WDT_INIT=n
+CONFIG_IDF_EXPERIMENTAL_FEATURES=y
+CONFIG_ESPTOOLPY_FLASHSIZE_32MB=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_BOOTLOADER_FLASH_DC_AWARE=y
+CONFIG_SPI_FLASH_HPM_DC_AUTO=y
+CONFIG_SPI_FLASH_HPM_DC_ON=y
+CONFIG_SPI_FLASH_HPM_ENA=y
+CONFIG_ESPTOOLPY_FLASHMODE_DIO=y
+CONFIG_PARTITION_TABLE_OFFSET=0xa000

components/spi_flash/test_apps/esp_flash/sdkconfig.ci.c5_32m_120m_dio_map

@@ -0,0 +1,13 @@
+CONFIG_IDF_TARGET="esp32c5"
+
+CONFIG_ESP_TASK_WDT_INIT=n
+CONFIG_IDF_EXPERIMENTAL_FEATURES=y
+CONFIG_ESPTOOLPY_FLASHSIZE_32MB=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_BOOTLOADER_FLASH_DC_AWARE=y
+CONFIG_SPI_FLASH_HPM_DC_AUTO=y
+CONFIG_SPI_FLASH_HPM_DC_ON=y
+CONFIG_SPI_FLASH_HPM_ENA=y
+CONFIG_ESPTOOLPY_FLASHMODE_DIO=y
+CONFIG_PARTITION_TABLE_OFFSET=0xa000
+CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH=y

components/spi_flash/test_apps/esp_flash/sdkconfig.ci.c5_32m_120m_qio

@@ -0,0 +1,12 @@
+CONFIG_IDF_TARGET="esp32c5"
+
+CONFIG_ESP_TASK_WDT_INIT=n
+CONFIG_IDF_EXPERIMENTAL_FEATURES=y
+CONFIG_ESPTOOLPY_FLASHSIZE_32MB=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_BOOTLOADER_FLASH_DC_AWARE=y
+CONFIG_SPI_FLASH_HPM_DC_AUTO=y
+CONFIG_SPI_FLASH_HPM_DC_ON=y
+CONFIG_SPI_FLASH_HPM_ENA=y
+CONFIG_ESPTOOLPY_FLASHMODE_QIO=y
+CONFIG_PARTITION_TABLE_OFFSET=0xa000

components/spi_flash/test_apps/esp_flash/sdkconfig.ci.c5_32m_120m_qio_map

@@ -0,0 +1,13 @@
+CONFIG_IDF_TARGET="esp32c5"
+
+CONFIG_ESP_TASK_WDT_INIT=n
+CONFIG_IDF_EXPERIMENTAL_FEATURES=y
+CONFIG_ESPTOOLPY_FLASHSIZE_32MB=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_BOOTLOADER_FLASH_DC_AWARE=y
+CONFIG_SPI_FLASH_HPM_DC_AUTO=y
+CONFIG_SPI_FLASH_HPM_DC_ON=y
+CONFIG_SPI_FLASH_HPM_ENA=y
+CONFIG_ESPTOOLPY_FLASHMODE_QIO=y
+CONFIG_PARTITION_TABLE_OFFSET=0xa000
+CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH=y

components/spi_flash/test_apps/esp_flash/sdkconfig.ci.c61_32m_120m_dio

@@ -0,0 +1,12 @@
+CONFIG_IDF_TARGET="esp32c61"
+
+CONFIG_ESP_TASK_WDT_INIT=n
+CONFIG_IDF_EXPERIMENTAL_FEATURES=y
+CONFIG_ESPTOOLPY_FLASHSIZE_32MB=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_BOOTLOADER_FLASH_DC_AWARE=y
+CONFIG_SPI_FLASH_HPM_DC_AUTO=y
+CONFIG_SPI_FLASH_HPM_DC_ON=y
+CONFIG_SPI_FLASH_HPM_ENA=y
+CONFIG_ESPTOOLPY_FLASHMODE_DIO=y
+CONFIG_PARTITION_TABLE_OFFSET=0xa000

components/spi_flash/test_apps/esp_flash/sdkconfig.ci.c61_32m_120m_dio_map

@@ -0,0 +1,13 @@
+CONFIG_IDF_TARGET="esp32c61"
+
+CONFIG_ESP_TASK_WDT_INIT=n
+CONFIG_IDF_EXPERIMENTAL_FEATURES=y
+CONFIG_ESPTOOLPY_FLASHSIZE_32MB=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_BOOTLOADER_FLASH_DC_AWARE=y
+CONFIG_SPI_FLASH_HPM_DC_AUTO=y
+CONFIG_SPI_FLASH_HPM_DC_ON=y
+CONFIG_SPI_FLASH_HPM_ENA=y
+CONFIG_ESPTOOLPY_FLASHMODE_DIO=y
+CONFIG_PARTITION_TABLE_OFFSET=0xa000
+CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH=y

components/spi_flash/test_apps/esp_flash/sdkconfig.ci.c61_32m_120m_qio

@@ -0,0 +1,12 @@
+CONFIG_IDF_TARGET="esp32c61"
+
+CONFIG_ESP_TASK_WDT_INIT=n
+CONFIG_IDF_EXPERIMENTAL_FEATURES=y
+CONFIG_ESPTOOLPY_FLASHSIZE_32MB=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_BOOTLOADER_FLASH_DC_AWARE=y
+CONFIG_SPI_FLASH_HPM_DC_AUTO=y
+CONFIG_SPI_FLASH_HPM_DC_ON=y
+CONFIG_SPI_FLASH_HPM_ENA=y
+CONFIG_ESPTOOLPY_FLASHMODE_QIO=y
+CONFIG_PARTITION_TABLE_OFFSET=0xa000

components/spi_flash/test_apps/esp_flash/sdkconfig.ci.c61_32m_120m_qio_map

@@ -0,0 +1,13 @@
+CONFIG_IDF_TARGET="esp32c61"
+
+CONFIG_ESP_TASK_WDT_INIT=n
+CONFIG_IDF_EXPERIMENTAL_FEATURES=y
+CONFIG_ESPTOOLPY_FLASHSIZE_32MB=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_BOOTLOADER_FLASH_DC_AWARE=y
+CONFIG_SPI_FLASH_HPM_DC_AUTO=y
+CONFIG_SPI_FLASH_HPM_DC_ON=y
+CONFIG_SPI_FLASH_HPM_ENA=y
+CONFIG_ESPTOOLPY_FLASHMODE_QIO=y
+CONFIG_PARTITION_TABLE_OFFSET=0xa000
+CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH=y

components/spi_flash/test_apps/esp_flash/sdkconfig.ci.p4_32m_120m_dio

@@ -0,0 +1,12 @@
+CONFIG_IDF_TARGET="esp32p4"
+
+CONFIG_ESP_TASK_WDT_INIT=n
+CONFIG_IDF_EXPERIMENTAL_FEATURES=y
+CONFIG_ESPTOOLPY_FLASHSIZE_32MB=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_BOOTLOADER_FLASH_DC_AWARE=y
+CONFIG_SPI_FLASH_HPM_DC_AUTO=y
+CONFIG_SPI_FLASH_HPM_DC_ON=y
+CONFIG_SPI_FLASH_HPM_ENA=y
+CONFIG_ESPTOOLPY_FLASHMODE_DIO=y
+CONFIG_PARTITION_TABLE_OFFSET=0xa000

components/spi_flash/test_apps/esp_flash/sdkconfig.ci.p4_32m_120m_dio_map

@@ -0,0 +1,13 @@
+CONFIG_IDF_TARGET="esp32p4"
+
+CONFIG_ESP_TASK_WDT_INIT=n
+CONFIG_IDF_EXPERIMENTAL_FEATURES=y
+CONFIG_ESPTOOLPY_FLASHSIZE_32MB=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_BOOTLOADER_FLASH_DC_AWARE=y
+CONFIG_SPI_FLASH_HPM_DC_AUTO=y
+CONFIG_SPI_FLASH_HPM_DC_ON=y
+CONFIG_SPI_FLASH_HPM_ENA=y
+CONFIG_ESPTOOLPY_FLASHMODE_DIO=y
+CONFIG_PARTITION_TABLE_OFFSET=0xa000
+CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH=y

components/spi_flash/test_apps/esp_flash/sdkconfig.ci.p4_32m_120m_qio

@@ -0,0 +1,12 @@
+CONFIG_IDF_TARGET="esp32p4"
+
+CONFIG_ESP_TASK_WDT_INIT=n
+CONFIG_IDF_EXPERIMENTAL_FEATURES=y
+CONFIG_ESPTOOLPY_FLASHSIZE_32MB=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_BOOTLOADER_FLASH_DC_AWARE=y
+CONFIG_SPI_FLASH_HPM_DC_AUTO=y
+CONFIG_SPI_FLASH_HPM_DC_ON=y
+CONFIG_SPI_FLASH_HPM_ENA=y
+CONFIG_ESPTOOLPY_FLASHMODE_QIO=y
+CONFIG_PARTITION_TABLE_OFFSET=0xa000

components/spi_flash/test_apps/esp_flash/sdkconfig.ci.p4_32m_120m_qio_map

@@ -0,0 +1,13 @@
+CONFIG_IDF_TARGET="esp32p4"
+
+CONFIG_ESP_TASK_WDT_INIT=n
+CONFIG_IDF_EXPERIMENTAL_FEATURES=y
+CONFIG_ESPTOOLPY_FLASHSIZE_32MB=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_BOOTLOADER_FLASH_DC_AWARE=y
+CONFIG_SPI_FLASH_HPM_DC_AUTO=y
+CONFIG_SPI_FLASH_HPM_DC_ON=y
+CONFIG_SPI_FLASH_HPM_ENA=y
+CONFIG_ESPTOOLPY_FLASHMODE_QIO=y
+CONFIG_PARTITION_TABLE_OFFSET=0xa000
+CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_QUAD_FLASH=y

pytest.ini

@@ -133,3 +133,4 @@ env_markers =
     esp32p4_eco4: Runner with esp32p4 eco4 connected
     esp32c5_eco3: Runner with esp32c5 eco3 connected
     rev_default: Runner with default revision connected
+    flash_32m: Runner with 32MB flash