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Merge branch 'feat/support_esp32s31_xtal_fosc_force_pu_v6.1' into 'release/v6.1'

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feat: update XTAL sleep FPU parameters to save power (v6.1)

See merge request espressif/esp-idf!51896
This commit is contained in:
Jiang Jiang Jian
2026-08-31 10:54:55 +08:00
parent d293398710 b4cd651f0a
commit 40feb79578
3 changed files with 23 additions and 21 deletions
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components/esp_system/port/soc/esp32s31/clk.c
+9
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@@ -56,7 +56,16 @@ __attribute__((weak)) void esp_clk_init(void)
assert(rtc_clk_xtal_freq_get() == SOC_XTAL_FREQ_40M);
rtc_clk_8m_enable(true);
#if CONFIG_RTC_FAST_CLK_SRC_RC_FAST
rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
#elif CONFIG_RTC_FAST_CLK_SRC_XTAL
rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_XTAL);
if (esp_sleep_sub_mode_dump_config(NULL)[ESP_SLEEP_RTC_FAST_USE_XTAL_MODE] == 0) {
esp_sleep_sub_mode_config(ESP_SLEEP_RTC_FAST_USE_XTAL_MODE, true);
}
#else
#error "No RTC fast clock source configured"
#endif
#if defined(CONFIG_BOOTLOADER_WDT_ENABLE) && SOC_RTC_WDT_SUPPORTED
// WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.