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refactor(hal): Cleanup some missing hal files

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C.S.M
2025-12-25 16:29:38 +08:00
parent 872f0cd202
commit 4034446cc7
16 changed files with 4 additions and 36 deletions
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261
components/hal/include/hal/dma2d_types.h
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/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "esp_assert.h"
#include "hal/assert.h"
#include "hal/color_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Type of 2D-DMA descriptor
*/
typedef struct dma2d_descriptor_align8_s dma2d_descriptor_align8_t;
struct dma2d_descriptor_align8_s {
struct {
uint32_t vb_size : 14; /*!< Vertical height of the block, unit: pixel
When dma2d_en field is 0, this field is the lower 14-bit of the buffer memory space size, unit: byte */
uint32_t hb_length : 14; /*!< Horizontal width of the block, unit: pixel
When dma2d_en field is 0, this field is the lower 14-bit of the buffer length, unit: byte
For data receive, this field is filled by DMA after transfer finishes */
uint32_t err_eof : 1; /*!< Whether the received buffer contains error
For data transfer, this bit is fixed to 0 */
uint32_t dma2d_en : 1; /*!< Whether to enable 2D functionality */
uint32_t suc_eof : 1; /*!< Whether the descriptor is the last one in the link */
uint32_t owner : 1; /*!< Who is allowed to access the buffer that this descriptor points to, select DMA2D_DESCRIPTOR_BUFFER_OWNER_CPU or DMA2D_DESCRIPTOR_BUFFER_OWNER_DMA
When owner is chosen to be DMA, after DMA finishes with the descriptor, it will clear this bit
For data transfer, the bit won't be cleared unless DMA2D_OUT_AUTO_WRBACK is enabled */
}; /*!< Descriptor Word 0 */
struct {
uint32_t va_size : 14; /*!< Vertical height of the picture, unit: pixel
When dma2d_en field is 0, this field is the higher 14-bit of the buffer memory space size, unit: byte */
uint32_t ha_length : 14; /*!< Horizontal width of the picture, unit: pixel
When dma2d_en field is 0, this field is the higher 14-bit of the buffer length, unit: byte
For data receive, this field is filled by DMA after transfer finishes */
uint32_t pbyte : 4; /*!< Number of bytes per pixel (make use of dma2d_desc_pixel_format_to_pbyte_value to get the value)
When dma2d_en field is 0, this field has no use */
}; /*!< Descriptor Word 1 */
struct {
uint32_t y : 14; /*!< The y-coordinate value of the hb * vb block, unit: pixel
When dma2d_en field is 0, this field has no use */
uint32_t x : 14; /*!< The x-coordinate value of the hb * vb block, unit: pixel
When dma2d_en field is 0, this field has no use */
uint32_t mode : 1; /*!< Data block read/write mode, select DMA2D_DESCRIPTOR_BLOCK_RW_MODE_SINGLE or DMA2D_DESCRIPTOR_BLOCK_RW_MODE_MULTIPLE
When dma2d_en field is 0, this field must be 0 (i.e. DMA2D_DESCRIPTOR_BLOCK_RW_MODE_SINGLE mode) */
uint32_t reserved29 : 3;
}; /*!< Descriptor Word 2 */
void *buffer; /*!< Pointer to the buffer (of ha * va picture)
For RX buffer, there is 4-byte alignment addr and size requirement (spiram and axi bus restriction, otherwises, could overwrite other data or be overwritten) */
dma2d_descriptor_align8_t *next; /*!< Pointer to the next descriptor (set to NULL if the descriptor is the last one, e.g. suc_eof=1) */
} __attribute__((aligned(8)));
ESP_STATIC_ASSERT(sizeof(dma2d_descriptor_align8_t) == 24, "dma2d_descriptor_align8_t should occupy 24 bytes in memory");
// 2D-DMA descriptor requires 8-byte alignment
typedef dma2d_descriptor_align8_t dma2d_descriptor_t;
#define DMA2D_DESCRIPTOR_BUFFER_OWNER_CPU (0) /*!< 2D-DMA buffer is allowed to be accessed by CPU */
#define DMA2D_DESCRIPTOR_BUFFER_OWNER_DMA (1) /*!< 2D-DMA buffer is allowed to be accessed by 2D-DMA engine */
#define DMA2D_DESCRIPTOR_BLOCK_RW_MODE_SINGLE (0) /*!< 2D-DMA data block single R/W mode, only r/w one hb * vb block */
#define DMA2D_DESCRIPTOR_BLOCK_RW_MODE_MULTIPLE (1) /*!< 2D-DMA data block multiple R/W mode, continues r/w hb * vb blocks until the ha * va picture is done */
#define DMA2D_DESCRIPTOR_PBYTE_0B5_PER_PIXEL (0) /*!< 2D-DMA descriptor pbyte value when 0.5 bytes/pixel */
#define DMA2D_DESCRIPTOR_PBYTE_1B0_PER_PIXEL (1) /*!< 2D-DMA descriptor pbyte value when 1 bytes/pixel */
#define DMA2D_DESCRIPTOR_PBYTE_1B5_PER_PIXEL (2) /*!< 2D-DMA descriptor pbyte value when 1.5 bytes/pixel */
#define DMA2D_DESCRIPTOR_PBYTE_2B0_PER_PIXEL (3) /*!< 2D-DMA descriptor pbyte value when 2 bytes/pixel */
#define DMA2D_DESCRIPTOR_PBYTE_3B0_PER_PIXEL (4) /*!< 2D-DMA descriptor pbyte value when 3 bytes/pixel */
#define DMA2D_DESCRIPTOR_PBYTE_4B0_PER_PIXEL (5) /*!< 2D-DMA descriptor pbyte value when 4 bytes/pixel */
// Helper function to convert pixel format to 2D-DMA descriptor pbyte value
static inline uint32_t dma2d_desc_pixel_format_to_pbyte_value(esp_color_fourcc_t pixel_format)
{
switch (color_hal_pixel_format_fourcc_get_bit_depth(pixel_format)) {
case 4:
return DMA2D_DESCRIPTOR_PBYTE_0B5_PER_PIXEL;
case 8:
return DMA2D_DESCRIPTOR_PBYTE_1B0_PER_PIXEL;
case 12:
return DMA2D_DESCRIPTOR_PBYTE_1B5_PER_PIXEL;
case 16:
return DMA2D_DESCRIPTOR_PBYTE_2B0_PER_PIXEL;
case 24:
return DMA2D_DESCRIPTOR_PBYTE_3B0_PER_PIXEL;
case 32:
return DMA2D_DESCRIPTOR_PBYTE_4B0_PER_PIXEL;
default:
// Unsupported bit depth
abort();
}
}
/**
* @brief Enumeration of peripherals which have the 2D-DMA capability
*/
typedef enum {
DMA2D_TRIG_PERIPH_M2M, /*!< 2D-DMA trigger peripheral: M2M */
DMA2D_TRIG_PERIPH_JPEG_ENCODER, /*!< 2D-DMA trigger peripheral: JPEG Encoder */
DMA2D_TRIG_PERIPH_JPEG_DECODER, /*!< 2D-DMA trigger peripheral: JPEG Decoder */
DMA2D_TRIG_PERIPH_PPA_SRM, /*!< 2D-DMA trigger peripheral: PPA SRM engine */
DMA2D_TRIG_PERIPH_PPA_BLEND, /*!< 2D-DMA trigger peripheral: PPA Blending engine */
} dma2d_trigger_peripheral_t;
/**
* @brief Enumeration of 2D-DMA channel direction
*/
typedef enum {
DMA2D_CHANNEL_DIRECTION_TX, /*!< 2D-DMA channel direction: TX */
DMA2D_CHANNEL_DIRECTION_RX, /*!< 2D-DMA channel direction: RX */
} dma2d_channel_direction_t;
/**
* @brief Enumeration of 2D-DMA data burst length options
*
* Starting from 1, saving 0 for special purpose (upper layer could use 0 to be a default burst length)
*/
typedef enum {
DMA2D_DATA_BURST_LENGTH_8 = 1, /*!< 2D-DMA block size: 8 bytes */
DMA2D_DATA_BURST_LENGTH_16, /*!< 2D-DMA block size: 16 bytes */
DMA2D_DATA_BURST_LENGTH_32, /*!< 2D-DMA block size: 32 bytes */
DMA2D_DATA_BURST_LENGTH_64, /*!< 2D-DMA block size: 64 bytes */
DMA2D_DATA_BURST_LENGTH_128, /*!< 2D-DMA block size: 128 bytes */
DMA2D_DATA_BURST_LENGTH_INVALID, /*!< Invalid 2D-DMA block size */
} dma2d_data_burst_length_t;
/**
* @brief Enumeration of 2D-DMA macro block size options
* Only useful in DMA2D_DESCRIPTOR_BLOCK_RW_MODE_MULTIPLE mode (dma2d_en = 1, mode = 1)
* Descriptor vb and hb fields has to be multiples of macro block sizes
*/
typedef enum {
DMA2D_MACRO_BLOCK_SIZE_NONE, /*!< 2D-DMA no macro block */
DMA2D_MACRO_BLOCK_SIZE_8_8, /*!< 2D-DMA 8 pixel x 8 pixel macro block */
DMA2D_MACRO_BLOCK_SIZE_8_16, /*!< 2D-DMA 8 pixel x 16 pixel macro block */
DMA2D_MACRO_BLOCK_SIZE_16_16, /*!< 2D-DMA 16 pixel x 16 pixel macro block */
DMA2D_MACRO_BLOCK_SIZE_INVALID, /*!< Invalid 2D-DMA macro block size */
} dma2d_macro_block_size_t;
/**
* @brief Enumeration of 2D-DMA pixel bytes scamble order in color space conversion
*
* Assuming the original pixel byte order (from MSB to LSB) is 2-1-0 .
*/
typedef enum {
DMA2D_SCRAMBLE_ORDER_BYTE2_1_0, /*!< 2D-DMA pixel data scrambled as BYTE2-1-0 (no scramble) */
DMA2D_SCRAMBLE_ORDER_BYTE2_0_1, /*!< 2D-DMA pixel data scrambled as BYTE2-0-1 */
DMA2D_SCRAMBLE_ORDER_BYTE1_0_2, /*!< 2D-DMA pixel data scrambled as BYTE1-0-2 */
DMA2D_SCRAMBLE_ORDER_BYTE1_2_0, /*!< 2D-DMA pixel data scrambled as BYTE1-2-0 */
DMA2D_SCRAMBLE_ORDER_BYTE0_2_1, /*!< 2D-DMA pixel data scrambled as BYTE0-2-1 */
DMA2D_SCRAMBLE_ORDER_BYTE0_1_2, /*!< 2D-DMA pixel data scrambled as BYTE0-1-2 */
DMA2D_SCRAMBLE_ORDER_INVALID, /*!< Invalid 2D-DMA pixel data scramble order */
} dma2d_scramble_order_t;
//*********************BT601***********************************//
// Y = 16 + 0.257 * R + 0.504 * g + 0.098 * b //
// Cb = 128 - 0.148 * R - 0.291 * g + 0.439 * b //
// Cr = 128 + 0.439 * R - 0.368 * g - 0.071 * b //
// R = 1.164 *(Y - 16) + 1.596 *(Cr - 128) //
// G = 1.164 *(Y - 16) - 0.392 *(Cb - 128) - 0.812 *(Cr - 128)//
// B = 1.164 *(Y - 16) + 2.016 *(Cb - 128) //
//*********************BT601***********************************//
//*********************BT709***********************************//
// Y = 16 + 0.183 * R + 0.614 * g + 0.062 * b //
// Cb = 128 - 0.101 * R - 0.339 * g + 0.439 * b //
// Cr = 128 + 0.439 * R - 0.399 * g - 0.040 * b //
// R = 1.164 *(Y - 16) + 1.792 *(Cr - 128) //
// G = 1.164 *(Y - 16) - 0.213 *(Cb - 128) - 0.534 *(Cr - 128)//
// B = 1.164 *(Y - 16) + 2.114 *(Cb - 128) //
//*********************BT709***********************************//
// R/G/B [0 ... 255]
// Y [16 ... 235]
// Cb/Cr [16 ... 240]
// 256 * Q = A[9:0] * x + B[10:0] * y + C[9:0] * z + D[17:0]
#define DMA2D_COLOR_SPACE_CONV_PARAM_RGB2YUV_BT601 \
{ \
{ 66, 129, 25, 4096}, \
{ -38, -74, 112, 32768}, \
{ 112, -94, -18, 32768}, \
}
#define DMA2D_COLOR_SPACE_CONV_PARAM_RGB2YUV_BT709 \
{ \
{ 47, 157, 16, 4096}, \
{ -26, -86, 112, 32768}, \
{ 112, -102, -10, 32768}, \
}
#define DMA2D_COLOR_SPACE_CONV_PARAM_YUV2RGB_BT601 \
{ \
{ 298, 0, 409, -56906}, \
{ 298, -100, -208, 34707}, \
{ 298, 516, 0, -70836}, \
}
#define DMA2D_COLOR_SPACE_CONV_PARAM_YUV2RGB_BT709 \
{ \
{ 298, 0, 459, -63367}, \
{ 298, -55, -136, 19681}, \
{ 298, 541, 0, -73918}, \
}
/**
* @brief Enumeration of 2D-DMA TX color space conversion (CSC) option
*/
typedef enum {
DMA2D_CSC_TX_NONE, /*!< 2D-DMA TX perform no CSC */
DMA2D_CSC_TX_SCRAMBLE, /*!< 2D-DMA TX perform only data scramble */
DMA2D_CSC_TX_RGB888_TO_RGB565, /*!< 2D-DMA TX perform RGB888 to RGB565 conversion */
DMA2D_CSC_TX_RGB565_TO_RGB888, /*!< 2D-DMA TX perform RGB565 to RGB888 conversion */
DMA2D_CSC_TX_RGB888_TO_YUV444_601, /*!< 2D-DMA TX perform RGB888 to YUV444 conversion (follow BT601 standard) */
DMA2D_CSC_TX_RGB888_TO_YUV444_709, /*!< 2D-DMA TX perform RGB888 to YUV444 conversion (follow BT709 standard) */
DMA2D_CSC_TX_RGB888_TO_YUV422_601, /*!< 2D-DMA TX perform RGB888 to YUV422-MIPI conversion (follow BT601 standard) */
DMA2D_CSC_TX_RGB888_TO_YUV422_709, /*!< 2D-DMA TX perform RGB888 to YUV422-MIPI conversion (follow BT709 standard) */
DMA2D_CSC_TX_YUV444_TO_RGB888_601, /*!< 2D-DMA TX perform YUV444 to RGB888 conversion (follow BT601 standard) */
DMA2D_CSC_TX_YUV444_TO_RGB888_709, /*!< 2D-DMA TX perform YUV444 to RGB888 conversion (follow BT709 standard) */
DMA2D_CSC_TX_YUV422_TO_RGB888_601, /*!< 2D-DMA TX perform YUV422-MIPI to RGB888 conversion (follow BT601 standard) */
DMA2D_CSC_TX_YUV422_TO_RGB888_709, /*!< 2D-DMA TX perform YUV422-MIPI to RGB888 conversion (follow BT709 standard) */
DMA2D_CSC_TX_INVALID, /*!< Invalid 2D-DMA TX color space conversion */
} dma2d_csc_tx_option_t;
/**
* @brief Enumeration of 2D-DMA RX color space conversion (CSC) option
* RX side only JPEG requires CSC
*/
typedef enum {
DMA2D_CSC_RX_NONE, /*!< 2D-DMA RX perform no CSC */
DMA2D_CSC_RX_SCRAMBLE, /*!< 2D-DMA RX perform only data scramble */
DMA2D_CSC_RX_YUV422_TO_YUV444, /*!< 2D-DMA RX perform YUV422-JPEG to YUV444 conversion */
DMA2D_CSC_RX_YUV422_TO_YUV420, /*!< 2D-DMA RX perform YUV422-JPEG to YUV420 conversion */
DMA2D_CSC_RX_YUV420_TO_YUV444, /*!< 2D-DMA RX perform YUV420-JPEG to YUV444 conversion */
DMA2D_CSC_RX_YUV420_TO_RGB888_601, /*!< 2D-DMA RX perform YUV420-JPEG to RGB888 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV420_TO_RGB565_601, /*!< 2D-DMA RX perform YUV420-JPEG to RGB565 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV420_TO_RGB888_709, /*!< 2D-DMA RX perform YUV420-JPEG to RGB888 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV420_TO_RGB565_709, /*!< 2D-DMA RX perform YUV420-JPEG to RGB565 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV422_TO_RGB888_601, /*!< 2D-DMA RX perform YUV422-JPEG to RGB888 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV422_TO_RGB565_601, /*!< 2D-DMA RX perform YUV422-JPEG to RGB565 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV422_TO_RGB888_709, /*!< 2D-DMA RX perform YUV422-JPEG to RGB888 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV422_TO_RGB565_709, /*!< 2D-DMA RX perform YUV422-JPEG to RGB565 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV444_TO_YUV422, /*!< 2D-DMA RX perform YUV444-JPEG to YUV422-MIPI conversion */
DMA2D_CSC_RX_YUV444_TO_YUV420, /*!< 2D-DMA RX perform YUV444-JPEG to YUV420 conversion */
DMA2D_CSC_RX_YUV444_TO_RGB888_601, /*!< 2D-DMA RX perform YUV444-JPEG to RGB888 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV444_TO_RGB565_601, /*!< 2D-DMA RX perform YUV444-JPEG to RGB565 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV444_TO_RGB888_709, /*!< 2D-DMA RX perform YUV444-JPEG to RGB888 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV444_TO_RGB565_709, /*!< 2D-DMA RX perform YUV444-JPEG to RGB565 conversion (follow BT709 standard) */
DMA2D_CSC_RX_INVALID, /*!< Invalid 2D-DMA RX color space conversion */
} dma2d_csc_rx_option_t;
#ifdef __cplusplus
}
#endif

77
components/hal/include/hal/dma_types.h
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/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stddef.h>
#include "esp_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Type of DMA descriptor the aligned to 4 bytes
*/
typedef struct dma_descriptor_s dma_descriptor_t;
struct dma_descriptor_s {
struct {
uint32_t size : 12; /*!< Buffer size */
uint32_t length : 12; /*!< Number of valid bytes in the buffer */
uint32_t reversed24_27 : 4; /*!< Reserved */
uint32_t err_eof : 1; /*!< Whether the received buffer contains error */
uint32_t reserved29 : 1; /*!< Reserved */
uint32_t suc_eof : 1; /*!< Whether the descriptor is the last one in the link */
uint32_t owner : 1; /*!< Who is allowed to access the buffer that this descriptor points to */
} dw0; /*!< Descriptor Word 0 */
void *buffer; /*!< Pointer to the buffer */
dma_descriptor_t *next; /*!< Pointer to the next descriptor (set to NULL if the descriptor is the last one, e.g. suc_eof=1) */
} __attribute__((aligned(4)));
typedef dma_descriptor_t dma_descriptor_align4_t;
ESP_STATIC_ASSERT(sizeof(dma_descriptor_align4_t) == 12, "dma_descriptor_align4_t should occupy 12 bytes in memory");
/**
* @brief Type of DMA descriptor the aligned to 8 bytes
*/
typedef struct dma_descriptor_align8_s dma_descriptor_align8_t;
struct dma_descriptor_align8_s {
struct {
uint32_t size : 12; /*!< Buffer size */
uint32_t length : 12; /*!< Number of valid bytes in the buffer */
uint32_t reversed24_27 : 4; /*!< Reserved */
uint32_t err_eof : 1; /*!< Whether the received buffer contains error */
uint32_t reserved29 : 1; /*!< Reserved */
uint32_t suc_eof : 1; /*!< Whether the descriptor is the last one in the link */
uint32_t owner : 1; /*!< Who is allowed to access the buffer that this descriptor points to */
} dw0; /*!< Descriptor Word 0 */
void *buffer; /*!< Pointer to the buffer */
dma_descriptor_align8_t *next; /*!< Pointer to the next descriptor (set to NULL if the descriptor is the last one, e.g. suc_eof=1) */
} __attribute__((aligned(8)));
ESP_STATIC_ASSERT(sizeof(dma_descriptor_align8_t) == 16, "dma_descriptor_align8_t should occupy 16 bytes in memory");
#define DMA_DESCRIPTOR_BUFFER_OWNER_CPU (0) /*!< DMA buffer is allowed to be accessed by CPU */
#define DMA_DESCRIPTOR_BUFFER_OWNER_DMA (1) /*!< DMA buffer is allowed to be accessed by DMA engine */
#define DMA_DESCRIPTOR_BUFFER_MAX_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */
#define DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED (4095-3) /*!< Maximum size of the buffer that can be attached to descriptor, and aligned to 4B */
#define DMA_DESCRIPTOR_BUFFER_MAX_SIZE_16B_ALIGNED (4095-15) /*!< Maximum size of the buffer that can be attached to descriptor, and aligned to 16B */
#define DMA_DESCRIPTOR_BUFFER_MAX_SIZE_64B_ALIGNED (4095-63) /*!< Maximum size of the buffer that can be attached to descriptor, and aligned to 64B */
/**
* Get the number of DMA descriptors required for a given buffer size.
*
* @param data_size Size to check DMA descriptor number.
* @param max_desc_size Maximum length of each descriptor
* @return Number of DMA descriptors required.
*/
static inline size_t dma_desc_get_required_num(size_t data_size, size_t max_desc_size)
{
return (data_size + max_desc_size - 1) / max_desc_size;
}
#ifdef __cplusplus
}
#endif

89
components/hal/include/hal/eth_types.h
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@@ -1,89 +0,0 @@
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Ethernet interface
*
*/
typedef enum {
EMAC_DATA_INTERFACE_RMII, /*!< Reduced Media Independent Interface */
EMAC_DATA_INTERFACE_MII, /*!< Media Independent Interface */
} eth_data_interface_t;
/**
* @brief Ethernet link status
*
*/
typedef enum {
ETH_LINK_UP, /*!< Ethernet link is up */
ETH_LINK_DOWN /*!< Ethernet link is down */
} eth_link_t;
/**
* @brief Ethernet speed
*
*/
typedef enum {
ETH_SPEED_10M, /*!< Ethernet speed is 10Mbps */
ETH_SPEED_100M, /*!< Ethernet speed is 100Mbps */
ETH_SPEED_MAX /*!< Max speed mode (for checking purpose) */
} eth_speed_t;
/**
* @brief Ethernet duplex mode
*
*/
typedef enum {
ETH_DUPLEX_HALF, /*!< Ethernet is in half duplex */
ETH_DUPLEX_FULL, /*!< Ethernet is in full duplex */
} eth_duplex_t;
/**
* @brief Ethernet Checksum
*/
typedef enum {
ETH_CHECKSUM_SW, /*!< Ethernet checksum calculate by software */
ETH_CHECKSUM_HW /*!< Ethernet checksum calculate by hardware */
} eth_checksum_t;
/**
* @brief Internal ethernet EMAC's DMA available burst sizes
*/
typedef enum {
ETH_DMA_BURST_LEN_32,
ETH_DMA_BURST_LEN_16,
ETH_DMA_BURST_LEN_8,
ETH_DMA_BURST_LEN_4,
ETH_DMA_BURST_LEN_2,
ETH_DMA_BURST_LEN_1,
} eth_mac_dma_burst_len_t;
/**
* @brief EMAC System timestamp update update method
*
*/
typedef enum {
ETH_PTP_UPDATE_METHOD_COARSE, /*!< EMAC System timestamp update using the Coarse method */
ETH_PTP_UPDATE_METHOD_FINE /*!< EMAC System timestamp update using the Fine method */
} eth_mac_ptp_update_method_t;
/**
* @brief EMAC System Timestamp Rollover
*
*/
typedef enum {
ETH_PTP_DIGITAL_ROLLOVER, /*!< Digital - subseconds register rolls over after 999999999 value (1 nanosecond accuracy) */
ETH_PTP_BINARY_ROLLOVER /*!< Binary - subseconds register rolls over after 0x7FFFFFFF value */
} eth_mac_ptp_roll_type_t;
#ifdef __cplusplus
}
#endif

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components/hal/include/hal/gdma_types.h
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@@ -1,63 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#if __has_include("hal/gdma_channel.h")
#include "hal/gdma_channel.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enumeration of peripherals which have the DMA capability
* @note Some peripheral might not be available on certain chip, please refer to `soc_caps.h` for detail.
*/
typedef enum {
GDMA_TRIG_PERIPH_M2M, /*!< GDMA trigger peripheral: M2M */
GDMA_TRIG_PERIPH_UHCI, /*!< GDMA trigger peripheral: UHCI */
GDMA_TRIG_PERIPH_SPI, /*!< GDMA trigger peripheral: SPI */
GDMA_TRIG_PERIPH_I2S, /*!< GDMA trigger peripheral: I2S */
GDMA_TRIG_PERIPH_AES, /*!< GDMA trigger peripheral: AES */
GDMA_TRIG_PERIPH_SHA, /*!< GDMA trigger peripheral: SHA */
GDMA_TRIG_PERIPH_ADC, /*!< GDMA trigger peripheral: ADC */
GDMA_TRIG_PERIPH_DAC, /*!< GDMA trigger peripheral: DAC */
GDMA_TRIG_PERIPH_LCD, /*!< GDMA trigger peripheral: LCD */
GDMA_TRIG_PERIPH_CAM, /*!< GDMA trigger peripheral: CAM */
GDMA_TRIG_PERIPH_RMT, /*!< GDMA trigger peripheral: RMT */
GDMA_TRIG_PERIPH_PARLIO, /*!< GDMA trigger peripheral: PARLIO */
GDMA_TRIG_PERIPH_I3C, /*!< GDMA trigger peripheral: I3C */
} gdma_trigger_peripheral_t;
/**
* @brief Enumeration of GDMA channel direction
*/
typedef enum {
GDMA_CHANNEL_DIRECTION_TX, /*!< GDMA channel direction: TX */
GDMA_CHANNEL_DIRECTION_RX, /*!< GDMA channel direction: RX */
} gdma_channel_direction_t;
/**
* @brief GDMA channel events that supported by the ETM module
*/
typedef enum {
GDMA_ETM_EVENT_EOF, /*!< Event that the GDMA engine meets EOF descriptor */
GDMA_ETM_EVENT_MAX, /*!< Maximum number of events */
} gdma_etm_event_type_t;
/**
* @brief GDMA channel tasks that supported by the ETM module
*/
typedef enum {
GDMA_ETM_TASK_START, /*!< Start the GDMA machine */
GDMA_ETM_TASK_MAX, /*!< Maximum number of events */
} gdma_etm_task_type_t;
#ifdef __cplusplus
}
#endif

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components/hal/include/hal/glitch_filter_types.h
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/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/clk_tree_defs.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER || (SOC_GPIO_FLEX_GLITCH_FILTER_NUM > 0)
typedef soc_periph_glitch_filter_clk_src_t glitch_filter_clock_source_t; // glitch filter clock source
#else
typedef int glitch_filter_clock_source_t; // glitch filter clock source, fallback to integer type
#endif // SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER || (SOC_GPIO_FLEX_GLITCH_FILTER_NUM > 0)
#ifdef __cplusplus
}
#endif

514
components/hal/include/hal/i2s_hal.h
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/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for I2S.
// There is no parameter check in the hal layer, so the caller must ensure the correctness of the parameters.
#pragma once
#include "soc/soc_caps.h"
#if SOC_HAS(I2S)
#include "hal/i2s_types.h"
#include "hal/i2s_ll.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_HAS(I2S)
/**
* @brief General slot configuration information
* @note It is a general purpose struct, not supposed to be used directly by user
*/
typedef struct {
i2s_data_bit_width_t data_bit_width; /*!< I2S sample data bit width (valid data bits per sample) */
i2s_slot_bit_width_t slot_bit_width; /*!< I2S slot bit width (total bits per slot) */
i2s_slot_mode_t slot_mode; /*!< Set mono or stereo mode with I2S_SLOT_MODE_MONO or I2S_SLOT_MODE_STEREO */
union {
/* STD configurations */
struct {
i2s_std_slot_mask_t slot_mask; /*!< Select the left, right or both slot */
uint32_t ws_width; /*!< WS signal width (i.e. the number of bclk ticks that ws signal is high) */
bool ws_pol; /*!< WS signal polarity, set true to enable high lever first */
bool bit_shift; /*!< Set to enable bit shift in Philips mode */
#if SOC_I2S_HW_VERSION_1 // For esp32/esp32-s2
bool msb_right; /*!< Set to place right channel data at the MSB in the FIFO */
#else
bool left_align; /*!< Set to enable left alignment */
bool big_endian; /*!< Set to enable big endian */
bool bit_order_lsb; /*!< Set to enable lsb first */
#endif
} std; /*!< Specific configurations for standard mode */
#if SOC_I2S_SUPPORTS_TDM
/* TDM configurations */
struct {
i2s_tdm_slot_mask_t slot_mask; /*!< Slot mask. Activating slots by setting 1 to corresponding bits. When the activated slots is not consecutive, those data in unactivated slots will be ignored */
uint32_t ws_width; /*!< WS signal width ((i.e. the number of bclk ticks that ws signal is high)) */
bool ws_pol; /*!< WS signal polarity, set true to enable high lever first */
bool bit_shift; /*!< Set true to enable bit shift in Philips mode */
bool left_align; /*!< Set true to enable left alignment */
bool big_endian; /*!< Set true to enable big endian */
bool bit_order_lsb; /*!< Set true to enable lsb first */
bool skip_mask; /*!< Set true to enable skip mask. If it is enabled, only the data of the enabled channels will be sent, otherwise all data stored in DMA TX buffer will be sent */
uint32_t total_slot; /*!< I2S total number of slots. If it is smaller than the biggest activated channel number, it will be set to this number automatically. */
} tdm; /*!< Specific configurations for TDM mode */
#endif
#if SOC_I2S_SUPPORTS_PDM_TX
/* PDM TX configurations */
struct {
#if SOC_I2S_HW_VERSION_1
i2s_pdm_slot_mask_t slot_mask; /*!< Slot mask to choose left or right slot */
#endif
i2s_pdm_data_fmt_t data_fmt; /*!< The data format of PDM TX mode. It determines what kind of data format is written in software.
* Typically, set this field to I2S_PDM_DATA_FMT_PCM when PCM2PDM filter is supported in the hardware,
* so that you can write PCM format data in software, and then the hardware PCM2PDM filter will help to
* convert it into PDM format on the line. Otherwise if this field is set to I2S_PDM_DATA_FMT_RAW,
* The data written in software are supposed to be the raw PDM format.
*/
uint32_t sd_prescale; /*!< Sigma-delta filter prescale */
i2s_pdm_sig_scale_t sd_scale; /*!< Sigma-delta filter scaling value */
i2s_pdm_sig_scale_t hp_scale; /*!< High pass filter scaling value */
i2s_pdm_sig_scale_t lp_scale; /*!< Low pass filter scaling value */
i2s_pdm_sig_scale_t sinc_scale; /*!< Sinc filter scaling value */
#if SOC_I2S_HW_VERSION_2
i2s_pdm_tx_line_mode_t line_mode; /*!< PDM TX line mode, on-line codec, one-line dac, two-line dac mode can be selected */
bool hp_en; /*!< High pass filter enable */
uint32_t hp_cut_off_freq_hzx10; /*!< High pass filter cut-off frequency times 10, cut-off frequency range 23.3Hz ~ 185Hz, see cut-off frequency sheet above
* The freq is timed 10 to use integer type */
uint32_t sd_dither; /*!< Sigma-delta filter dither */
uint32_t sd_dither2; /*!< Sigma-delta filter dither2 */
#endif // SOC_I2S_HW_VERSION_2
} pdm_tx; /*!< Specific configurations for PDM TX mode */
#endif
#if SOC_I2S_SUPPORTS_PDM_RX
/* PDM TX configurations */
struct {
i2s_pdm_slot_mask_t slot_mask; /*!< Choose the slots to activate */
i2s_pdm_data_fmt_t data_fmt; /*!< The data format of PDM RX mode. It determines what kind of data format is read in software.
* Typically, set this field to I2S_PDM_DATA_FMT_PCM when PCM2PDM filter is supported in the hardware,
* so that the hardware PDM2PCM filter will help to convert the raw PDM data on the line into PCM format,
* And then you can read PCM format data in software. Otherwise if this field is set to I2S_PDM_DATA_FMT_RAW,
* The data read in software are still in raw PDM format, you may need to convert the raw PDM data into PCM format manually by a software filter.
*/
#if SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER
bool hp_en; /*!< High pass filter enable */
uint32_t hp_cut_off_freq_hzx10; /*!< High pass filter cut-off frequency times 10, range 23.3Hz ~ 185Hz, see cut-off frequency sheet above */
uint32_t amplify_num; /*!< The amplification number of the final conversion result */
#endif // SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER
} pdm_rx; /*!< Specific configurations for PDM RX mode */
#endif
};
} i2s_hal_slot_config_t;
/**
* @brief I2S clock configuration
*/
typedef struct {
uint32_t sclk; /*!< I2S module clock */
uint32_t mclk; /*!< I2S master clock */
uint32_t bclk; /*!< I2S bit clock */
uint16_t mclk_div; /*!< I2S master clock division */
uint16_t bclk_div; /*!< I2S bit clock division*/
} i2s_hal_clock_info_t;
/**
* Context that should be maintained by both the driver and the HAL
*/
typedef struct {
i2s_dev_t *dev; /*!< I2S instance address */
} i2s_hal_context_t;
/**
* @brief Init I2S hal context
*
* @param hal Context of the HAL layer
* @param port_id The I2S port number, the max port number is (I2S_LL_GET(INST_NUM) -1)
*/
void i2s_hal_init(i2s_hal_context_t *hal, int port_id);
/**
* @brief Helper function for calculating the precise mclk division by sclk and mclk
*
* @param sclk system clock
* @param mclk module clock
* @param mclk_div mclk division coefficients, including integer part and decimal part
*/
void i2s_hal_calc_mclk_precise_division(uint32_t sclk, uint32_t mclk, hal_utils_clk_div_t *mclk_div);
#if SOC_PERIPH_CLK_CTRL_SHARED
/**
* @brief Set tx channel clock
*
* @param hal Context of the HAL layer
* @param clk_info clock information, if it is NULL, only set the clock source
* @param clk_src clock source
*/
void _i2s_hal_set_tx_clock(i2s_hal_context_t *hal, const i2s_hal_clock_info_t *clk_info, i2s_clock_src_t clk_src, hal_utils_clk_div_t *ret_mclk_div);
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define i2s_hal_set_tx_clock(...) do { \
(void)__DECLARE_RCC_ATOMIC_ENV; \
_i2s_hal_set_tx_clock(__VA_ARGS__); \
} while(0)
#else
/**
* @brief Set tx channel clock
*
* @param hal Context of the HAL layer
* @param clk_info clock information, if it is NULL, only set the clock source
* @param clk_src clock source
* @param ret_mclk_div return mclk division coefficients, including integer part and decimal part
*/
void i2s_hal_set_tx_clock(i2s_hal_context_t *hal, const i2s_hal_clock_info_t *clk_info, i2s_clock_src_t clk_src, hal_utils_clk_div_t *ret_mclk_div);
#endif // SOC_PERIPH_CLK_CTRL_SHARED
/**
* @brief Set rx channel clock
*
* @param hal Context of the HAL layer
* @param clk_info clock information, if it is NULL, only set the clock source
* @param clk_src clock source
* @param ret_mclk_div return mclk division coefficients, including integer part and decimal part
*/
void _i2s_hal_set_rx_clock(i2s_hal_context_t *hal, const i2s_hal_clock_info_t *clk_info, i2s_clock_src_t clk_src, hal_utils_clk_div_t *ret_mclk_div);
#if SOC_PERIPH_CLK_CTRL_SHARED
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define i2s_hal_set_rx_clock(...) do { \
(void)__DECLARE_RCC_ATOMIC_ENV; \
_i2s_hal_set_rx_clock(__VA_ARGS__); \
} while(0)
#else
#define i2s_hal_set_rx_clock(...) _i2s_hal_set_rx_clock(__VA_ARGS__)
#endif
/*-------------------------------------------------------------------------
| STD configuration |
-------------------------------------------------------------------------*/
/**
* @brief Set tx slot to standard mode
*
* @param hal Context of the HAL layer
* @param is_slave If is slave role
* @param slot_config General slot configuration pointer, but will specified to i2s standard mode
*/
void i2s_hal_std_set_tx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_hal_slot_config_t *slot_cfg);
/**
* @brief Set rx slot to standard mode
*
* @param hal Context of the HAL layer
* @param is_slave If is slave role
* @param slot_config General slot configuration pointer, but will specified to i2s standard mode
*/
void i2s_hal_std_set_rx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_hal_slot_config_t *slot_cfg);
/**
* @brief Enable tx channel as standard mode
*
* @param hal Context of the HAL layer
*/
void i2s_hal_std_enable_tx_channel(i2s_hal_context_t *hal);
/**
* @brief Enable rx channel as standard mode
*
* @param hal Context of the HAL layer
*/
void i2s_hal_std_enable_rx_channel(i2s_hal_context_t *hal);
/*-------------------------------------------------------------------------
| PDM configuration |
-------------------------------------------------------------------------*/
#if SOC_I2S_SUPPORTS_PDM
#if SOC_I2S_SUPPORTS_PDM_TX
/**
* @brief Set tx slot to pdm mode
*
* @param hal Context of the HAL layer
* @param is_slave If is slave role
* @param slot_config General slot configuration pointer, but will specified to i2s pdm tx mode
*/
void i2s_hal_pdm_set_tx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_hal_slot_config_t *slot_cfg);
/**
* @brief Enable tx channel as pdm mode
*
* @param hal Context of the HAL layer
* @param pcm2pdm_en Enable pcm to pdm conversion
*/
void i2s_hal_pdm_enable_tx_channel(i2s_hal_context_t *hal, bool pcm2pdm_en);
#endif // SOC_I2S_SUPPORTS_PDM_TX
#if SOC_I2S_SUPPORTS_PDM_RX
/**
* @brief Set rx slot to pdm mode
*
* @param hal Context of the HAL layer
* @param is_slave If is slave role
* @param slot_config General slot configuration pointer, but will specified to i2s pdm rx mode
*/
void i2s_hal_pdm_set_rx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_hal_slot_config_t *slot_cfg);
/**
* @brief Enable rx channel as pdm mode
*
* @param hal Context of the HAL layer
* @param pdm2pcm_en Enable pdm to pcm conversion
*/
void i2s_hal_pdm_enable_rx_channel(i2s_hal_context_t *hal, bool pdm2pcm_en);
#endif // SOC_I2S_SUPPORTS_PDM_RX
#endif // SOC_I2S_SUPPORTS_PDM
/*-------------------------------------------------------------------------
| TDM configuration |
-------------------------------------------------------------------------*/
#if SOC_I2S_SUPPORTS_TDM
/**
* @brief Set tx slot to tdm mode
*
* @param hal Context of the HAL layer
* @param is_slave If is slave role
* @param slot_config General slot configuration pointer, but will specified to i2s tdm mode
*/
void i2s_hal_tdm_set_tx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_hal_slot_config_t *slot_cfg);
/**
* @brief Set rx slot to tdm mode
*
* @param hal Context of the HAL layer
* @param is_slave If is slave role
* @param slot_config General slot configuration pointer, but will specified to i2s tdm mode
*/
void i2s_hal_tdm_set_rx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_hal_slot_config_t *slot_cfg);
/**
* @brief Enable tx channel as tdm mode
*
* @param hal Context of the HAL layer
*/
void i2s_hal_tdm_enable_tx_channel(i2s_hal_context_t *hal);
/**
* @brief Enable rx channel as tdm mode
*
* @param hal Context of the HAL layer
*/
void i2s_hal_tdm_enable_rx_channel(i2s_hal_context_t *hal);
#endif
/**
* @brief Start I2S TX channel
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_tx_start(hal) i2s_ll_tx_start((hal)->dev)
/**
* @brief Stop I2S TX channel
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_tx_stop(hal) i2s_ll_tx_stop((hal)->dev)
/**
* @brief Reset I2S TX channel
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_tx_reset(hal) i2s_ll_tx_reset((hal)->dev)
/**
* @brief Reset I2S TX fifo
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_tx_reset_fifo(hal) i2s_ll_tx_reset_fifo((hal)->dev)
/**
* @brief Start I2S RX channel
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_rx_start(hal) i2s_ll_rx_start((hal)->dev)
/**
* @brief Stop I2S RX channel
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_rx_stop(hal) i2s_ll_rx_stop((hal)->dev)
/**
* @brief Reset I2S RX channel
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_rx_reset(hal) i2s_ll_rx_reset((hal)->dev)
/**
* @brief Reset I2S RX fifo
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_rx_reset_fifo(hal) i2s_ll_rx_reset_fifo((hal)->dev)
#if !SOC_GDMA_SUPPORTED
/**
* @brief Enable I2S TX DMA
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_tx_enable_dma(hal) i2s_ll_enable_dma((hal)->dev,true)
/**
* @brief Enable I2S RX DMA
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_rx_enable_dma(hal) i2s_ll_enable_dma((hal)->dev,true)
/**
* @brief Disable I2S TX DMA
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_tx_disable_dma(hal) i2s_ll_enable_dma((hal)->dev,false)
/**
* @brief Disable I2S RX DMA
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_rx_disable_dma(hal) i2s_ll_enable_dma((hal)->dev,false)
/**
* @brief Get I2S interrupt status
*
* @param hal Context of the HAL layer
* @return
* - module interrupt status
*/
#define i2s_hal_get_intr_status(hal) i2s_ll_get_intr_status((hal)->dev)
/**
* @brief Get I2S interrupt status
*
* @param hal Context of the HAL layer
* @param mask Interrupt mask to be cleared.
*/
#define i2s_hal_clear_intr_status(hal, mask) i2s_ll_clear_intr_status((hal)->dev, mask)
/**
* @brief Enable I2S RX interrupt
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_rx_enable_intr(hal) i2s_ll_rx_enable_intr((hal)->dev)
/**
* @brief Disable I2S RX interrupt
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_rx_disable_intr(hal) i2s_ll_rx_disable_intr((hal)->dev)
/**
* @brief Disable I2S TX interrupt
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_tx_disable_intr(hal) i2s_ll_tx_disable_intr((hal)->dev)
/**
* @brief Enable I2S TX interrupt
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_tx_enable_intr(hal) i2s_ll_tx_enable_intr((hal)->dev)
/**
* @brief Configure TX DMA descriptor address and start TX DMA
*
* @param hal Context of the HAL layer
* @param link_addr DMA descriptor link address.
*/
#define i2s_hal_tx_start_link(hal, link_addr) i2s_ll_tx_start_link((hal)->dev, link_addr)
/**
* @brief Configure RX DMA descriptor address and start RX DMA
*
* @param hal Context of the HAL layer
* @param link_addr DMA descriptor link address.
*/
#define i2s_hal_rx_start_link(hal, link_addr) i2s_ll_rx_start_link((hal)->dev, link_addr)
/**
* @brief Stop TX DMA link
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_tx_stop_link(hal) i2s_ll_tx_stop_link((hal)->dev)
/**
* @brief Stop RX DMA link
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_rx_stop_link(hal) i2s_ll_rx_stop_link((hal)->dev)
/**
* @brief Reset RX DMA
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_rx_reset_dma(hal) i2s_ll_rx_reset_dma((hal)->dev)
/**
* @brief Reset TX DMA
*
* @param hal Context of the HAL layer
*/
#define i2s_hal_tx_reset_dma(hal) i2s_ll_tx_reset_dma((hal)->dev)
/**
* @brief Get I2S out eof descriptor address
*
* @param hal Context of the HAL layer
* @param addr Pointer to accept out eof des address
*/
#define i2s_hal_get_out_eof_des_addr(hal, addr) i2s_ll_tx_get_eof_des_addr((hal)->dev, addr)
/**
* @brief Get I2S in suc eof descriptor address
*
* @param hal Context of the HAL layer
* @param addr Pointer to accept in suc eof des address
*/
#define i2s_hal_get_in_eof_des_addr(hal, addr) i2s_ll_rx_get_eof_des_addr((hal)->dev, addr)
#endif
#endif // SOC_I2S_SUPPORTED
#ifdef __cplusplus
}
#endif

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components/hal/include/hal/jpeg_defs.h
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/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdlib.h>
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* @brief Enum to define JPEG marker codes
*/
typedef enum {
JPEG_M_SOF0 = 0xFFC0, ///< Start of Frame 0
JPEG_M_SOF1 = 0xFFC1, ///< Start of Frame 1
JPEG_M_SOF2 = 0xFFC2, ///< Start of Frame 2
JPEG_M_SOF3 = 0xFFC3, ///< Start of Frame 3
JPEG_M_SOF5 = 0xFFC5, ///< Start of Frame 5
JPEG_M_SOF6 = 0xFFC6, ///< Start of Frame 6
JPEG_M_SOF7 = 0xFFC7, ///< Start of Frame 7
JPEG_M_JPG = 0xFFC8, ///< JPEG Extension
JPEG_M_SOF9 = 0xFFC9, ///< Start of Frame 9
JPEG_M_SOF10 = 0xFFCA, ///< Start of Frame 10
JPEG_M_SOF11 = 0xFFCB, ///< Start of Frame 11
JPEG_M_SOF13 = 0xFFCD, ///< Start of Frame 13
JPEG_M_SOF14 = 0xFFCE, ///< Start of Frame 14
JPEG_M_SOF15 = 0xFFCF, ///< Start of Frame 15
JPEG_M_DHT = 0xFFC4, ///< Define Huffman Table
JPEG_M_DAC = 0xFFCC, ///< Define Arithmetic Coding Conditioning
JPEG_M_RST0 = 0xFFD0, ///< Restart with modulo 8 count 0
JPEG_M_RST1 = 0xFFD1, ///< Restart with modulo 8 count 1
JPEG_M_RST2 = 0xFFD2, ///< Restart with modulo 8 count 2
JPEG_M_RST3 = 0xFFD3, ///< Restart with modulo 8 count 3
JPEG_M_RST4 = 0xFFD4, ///< Restart with modulo 8 count 4
JPEG_M_RST5 = 0xFFD5, ///< Restart with modulo 8 count 5
JPEG_M_RST6 = 0xFFD6, ///< Restart with modulo 8 count 6
JPEG_M_RST7 = 0xFFD7, ///< Restart with modulo 8 count 7
JPEG_M_SOI = 0xFFD8, ///< Start of Image
JPEG_M_EOI = 0xFFD9, ///< End of Image
JPEG_M_SOS = 0xFFDA, ///< Start of Scan
JPEG_M_DQT = 0xFFDB, ///< Define Quantization Table
JPEG_M_DNL = 0xFFDC, ///< Define Number of Lines
JPEG_M_DRI = 0xFFDD, ///< Define Restart Interval
JPEG_M_DHP = 0xFFDE, ///< Define Hierarchical Progression
JPEG_M_EXP = 0xFFDF, ///< Expand Reference Component(s)
JPEG_M_APP0 = 0xFFE0, ///< Application Segment 0
JPEG_M_APP1 = 0xFFE1, ///< Application Segment 1
JPEG_M_APP2 = 0xFFE2, ///< Application Segment 2
JPEG_M_APP3 = 0xFFE3, ///< Application Segment 3
JPEG_M_APP4 = 0xFFE4, ///< Application Segment 4
JPEG_M_APP5 = 0xFFE5, ///< Application Segment 5
JPEG_M_APP6 = 0xFFE6, ///< Application Segment 6
JPEG_M_APP7 = 0xFFE7, ///< Application Segment 7
JPEG_M_APP8 = 0xFFE8, ///< Application Segment 8
JPEG_M_APP9 = 0xFFE9, ///< Application Segment 9
JPEG_M_APP10 = 0xFFEA, ///< Application Segment 10
JPEG_M_APP11 = 0xFFEB, ///< Application Segment 11
JPEG_M_APP12 = 0xFFEC, ///< Application Segment 12
JPEG_M_APP13 = 0xFFED, ///< Application Segment 13
JPEG_M_APP14 = 0xFFEE, ///< Application Segment 14
JPEG_M_APP15 = 0xFFEF, ///< Application Segment 15
JPEG_M_JPG0 = 0xFFF0, ///< Reserved for JPEG extension
JPEG_M_JPG13 = 0xFFFD, ///< Reserved for JPEG extension
JPEG_M_COM = 0xFFFE, ///< Comment
JPEG_M_TEM = 0xFF01, ///< Temporary use in arithmetic coding
JPEG_M_INV = 0xFFFF, ///< Invalid marker
} __attribute__((packed)) jpeg_marker_code_t;
#ifdef __cplusplus
}
#endif

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components/hal/include/hal/ldo_types.h
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/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief LDO Unit
*
* @note See datasheet to know LDO, alias includes but not least to `VFB/VOn`
*/
typedef enum {
LDO_UNIT_1 = 1, ///< LDO 1
LDO_UNIT_2, ///< LDO 2
LDO_UNIT_3, ///< LDO 3
LDO_UNIT_4, ///< LDO 4
} ldo_unit_t;
#ifdef __cplusplus
}
#endif

46
components/hal/include/hal/lp_i2s_hal.h
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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
#pragma once
#include <stdint.h>
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_LP_I2S_SUPPORTED
typedef struct lp_i2s_dev_t *lp_i2s_soc_handle_t; // LP I2S SOC layer handle
#else
typedef uint32_t *lp_i2s_soc_handle_t; // LP I2S SOC layer handle
#endif
/**
* Context that should be maintained by both the driver and the HAL
*/
typedef struct {
lp_i2s_soc_handle_t dev; // LP I2S SOC layer handle
} lp_i2s_hal_context_t;
/**
* @brief Init the LP I2S hal and set the LP I2S to the default configuration.
* @note This function should be called first before other hal layer function is called.
*
* @param hal Context of the HAL layer
* @param group_id LP I2S group ID
*/
void lp_i2s_hal_init(lp_i2s_hal_context_t *hal, int group_id);
#ifdef __cplusplus
}
#endif

118
components/hal/include/hal/mcpwm_types.h
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/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/clk_tree_defs.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief MCPWM timer clock source
*/
#if SOC_MCPWM_SUPPORTED
typedef soc_periph_mcpwm_timer_clk_src_t mcpwm_timer_clock_source_t;
#else
typedef int mcpwm_timer_clock_source_t;
#endif // SOC_MCPWM_SUPPORTED
/**
* @brief MCPWM capture clock source
*/
#if SOC_MCPWM_SUPPORTED
typedef soc_periph_mcpwm_capture_clk_src_t mcpwm_capture_clock_source_t;
#else
typedef int mcpwm_capture_clock_source_t;
#endif // SOC_MCPWM_SUPPORTED
/**
* @brief MCPWM carrier clock source
*/
#if SOC_MCPWM_SUPPORTED
typedef soc_periph_mcpwm_carrier_clk_src_t mcpwm_carrier_clock_source_t;
#else
typedef int mcpwm_carrier_clock_source_t;
#endif // SOC_MCPWM_SUPPORTED
/**
* @brief MCPWM timer count direction
*/
typedef enum {
MCPWM_TIMER_DIRECTION_UP, /*!< Counting direction: Increase */
MCPWM_TIMER_DIRECTION_DOWN, /*!< Counting direction: Decrease */
} mcpwm_timer_direction_t;
/**
* @brief MCPWM timer events
*/
typedef enum {
MCPWM_TIMER_EVENT_EMPTY, /*!< MCPWM timer counts to zero (i.e. counter is empty) */
MCPWM_TIMER_EVENT_FULL, /*!< MCPWM timer counts to peak (i.e. counter is full) */
MCPWM_TIMER_EVENT_INVALID, /*!< MCPWM timer invalid event */
} mcpwm_timer_event_t;
/**
* @brief MCPWM timer count modes
*/
typedef enum {
MCPWM_TIMER_COUNT_MODE_PAUSE, /*!< MCPWM timer paused */
MCPWM_TIMER_COUNT_MODE_UP, /*!< MCPWM timer counting up */
MCPWM_TIMER_COUNT_MODE_DOWN, /*!< MCPWM timer counting down */
MCPWM_TIMER_COUNT_MODE_UP_DOWN, /*!< MCPWM timer counting up and down */
} mcpwm_timer_count_mode_t;
/**
* @brief MCPWM timer commands, specify the way to start or stop the timer
*/
typedef enum {
MCPWM_TIMER_STOP_EMPTY, /*!< MCPWM timer stops when next count reaches zero */
MCPWM_TIMER_STOP_FULL, /*!< MCPWM timer stops when next count reaches peak */
MCPWM_TIMER_START_NO_STOP, /*!< MCPWM timer starts counting, and don't stop until received stop command */
MCPWM_TIMER_START_STOP_EMPTY, /*!< MCPWM timer starts counting and stops when next count reaches zero */
MCPWM_TIMER_START_STOP_FULL, /*!< MCPWM timer starts counting and stops when next count reaches peak */
} mcpwm_timer_start_stop_cmd_t;
/**
* @brief MCPWM generator actions
*/
typedef enum {
MCPWM_GEN_ACTION_KEEP, /*!< Generator action: Keep the same level */
MCPWM_GEN_ACTION_LOW, /*!< Generator action: Force to low level */
MCPWM_GEN_ACTION_HIGH, /*!< Generator action: Force to high level */
MCPWM_GEN_ACTION_TOGGLE, /*!< Generator action: Toggle level */
} mcpwm_generator_action_t;
/**
* @brief MCPWM operator brake mode
*/
typedef enum {
MCPWM_OPER_BRAKE_MODE_CBC, /*!< Brake mode: CBC (cycle by cycle)*/
MCPWM_OPER_BRAKE_MODE_OST, /*!< Brake mode: OST (one shot) */
MCPWM_OPER_BRAKE_MODE_INVALID, /*!< MCPWM operator invalid brake mode */
} mcpwm_operator_brake_mode_t;
/**
* @brief MCPWM capture edge
*/
typedef enum {
MCPWM_CAP_EDGE_POS, /*!< Capture on the positive edge */
MCPWM_CAP_EDGE_NEG, /*!< Capture on the negative edge */
} mcpwm_capture_edge_t;
/**
* @brief MCPWM comparator specific events that supported by the ETM module
*/
typedef enum {
MCPWM_CMPR_ETM_EVENT_EQUAL, /*!< The count value equals the value of comparator */
MCPWM_CMPR_ETM_EVENT_MAX, /*!< Maximum number of comparator events */
} mcpwm_comparator_etm_event_type_t;
#ifdef __cplusplus
}
#endif

25
components/hal/include/hal/psram_types.h
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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enumeration of PSRAM command types
*/
typedef enum {
PSRAM_HAL_CMD_QPI, /*!< Quad command for psram command */
PSRAM_HAL_CMD_SPI, /*!< SPI command for psram command */
} psram_cmd_mode_t;
#ifdef __cplusplus
}
#endif

35
components/hal/include/hal/usb_serial_jtag_types.h
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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_USB_SERIAL_JTAG_SUPPORTED
/**
* @brief USJ test mode values
*
* Specifies the logic values of each of the USB FSLS Serial PHY interface
* signals when in test mode.
*/
typedef struct {
bool dp_pu; /**< D+ pull-up resistor enable/disable */
bool dm_pu; /**< D- pull-up resistor enable/disable */
bool dp_pd; /**< D+ pull-down resistor enable/disable */
bool dm_pd; /**< D- pull-down resistor enable/disable */
} usb_serial_jtag_pull_override_vals_t;
#endif // SOC_USB_SERIAL_JTAG_SUPPORTED
#ifdef __cplusplus
}
#endif