mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-02 03:00:34 +03:00
feat(sd): sd host driver layer driver NG
This commit is contained in:
armando
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,588 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdbool.h>
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#include <stddef.h>
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#include <string.h>
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#include <unistd.h>
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#include <sys/param.h>
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#include "esp_log.h"
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#include "esp_intr_alloc.h"
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#include "esp_check.h"
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#include "soc/soc_caps.h"
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#include "driver/sd_host.h"
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#include "esp_private/sd_host_private.h"
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typedef enum {
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SDMMC_IDLE,
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SDMMC_SENDING_CMD,
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SDMMC_SENDING_DATA,
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SDMMC_BUSY,
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SDMMC_SENDING_VOLTAGE_SWITCH,
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SDMMC_WAITING_VOLTAGE_SWITCH,
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} sdmmc_req_state_t;
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static const char *TAG = "SD_TRANS";
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const uint32_t SD_DATA_ERR_MASK =
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SDMMC_INTMASK_DTO | SDMMC_INTMASK_DCRC |
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SDMMC_INTMASK_HTO | SDMMC_INTMASK_SBE |
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SDMMC_INTMASK_EBE;
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const uint32_t SD_DMA_DONE_MASK =
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SDMMC_IDMAC_INTMASK_RI | SDMMC_IDMAC_INTMASK_TI |
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SDMMC_IDMAC_INTMASK_NI;
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const uint32_t SD_CMD_ERR_MASK =
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SDMMC_INTMASK_RTO |
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SDMMC_INTMASK_RCRC |
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SDMMC_INTMASK_RESP_ERR;
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/*---------------------------------------------------------------
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Voltage
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---------------------------------------------------------------*/
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static void handle_voltage_switch_stage1(sd_host_sdmmc_slot_t *slot, sdmmc_command_t* cmd)
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{
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ESP_LOGV(TAG, "%s: enabling clock", __func__);
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sd_host_slot_set_cclk_always_on_internal(slot, true);
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}
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static void handle_voltage_switch_stage2(sd_host_sdmmc_slot_t *slot, sdmmc_command_t* cmd)
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{
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ESP_LOGV(TAG, "%s: disabling clock", __func__);
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sd_host_slot_enable_clk_cmd11(slot, false);
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usleep(100);
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ESP_LOGV(TAG, "%s: switching voltage", __func__);
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esp_err_t err = cmd->volt_switch_cb(cmd->volt_switch_cb_arg, 1800);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "failed to switch voltage (0x%x)", err);
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cmd->error = err;
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}
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ESP_LOGV(TAG, "%s: waiting 10ms", __func__);
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usleep(10000);
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ESP_LOGV(TAG, "%s: enabling clock", __func__);
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sd_host_slot_enable_clk_cmd11(slot, true);
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}
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static void handle_voltage_switch_stage3(sd_host_sdmmc_slot_t *slot, sdmmc_command_t* cmd)
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{
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ESP_LOGV(TAG, "%s: voltage switch complete, clock back to low-power mode", __func__);
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sd_host_slot_set_cclk_always_on_internal(slot, false);
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}
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/*---------------------------------------------------------------
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DMA
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---------------------------------------------------------------*/
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size_t sd_host_get_free_descriptors_count(sd_host_sdmmc_slot_t *slot)
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{
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const size_t next = slot->ctlr->cur_transfer.next_desc;
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size_t count = 0;
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/* Starting with the current DMA descriptor, count the number of
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* descriptors which have 'owned_by_idmac' set to 0. These are the
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* descriptors already processed by the DMA engine.
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*/
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int dma_desc_num = slot->ctlr->dma_desc_num;
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for (size_t i = 0; i < dma_desc_num; ++i) {
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sdmmc_desc_t *desc = slot->ctlr->dma_desc + ((next + i) % dma_desc_num);
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#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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esp_err_t ret = esp_cache_msync((void *)desc, sizeof(sdmmc_desc_t), ESP_CACHE_MSYNC_FLAG_DIR_M2C);
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assert(ret == ESP_OK);
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#endif
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if (desc->owned_by_idmac) {
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break;
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}
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++count;
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if (desc->next_desc_ptr == NULL) {
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/* final descriptor in the chain */
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break;
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}
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}
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return count;
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}
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void sd_host_fill_dma_descriptors(sd_host_sdmmc_slot_t *slot, size_t num_desc)
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{
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sd_host_sdmmc_trans_state_t *cur_trans = &slot->ctlr->cur_transfer;
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for (size_t i = 0; i < num_desc; ++i) {
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if (cur_trans->size_remaining == 0) {
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return;
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}
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const size_t next = cur_trans->next_desc;
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sdmmc_desc_t *desc = slot->ctlr->dma_desc + next;
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assert(!desc->owned_by_idmac);
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size_t size_to_fill =
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(cur_trans->size_remaining < SDMMC_DMA_MAX_BUF_LEN) ?
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cur_trans->size_remaining : SDMMC_DMA_MAX_BUF_LEN;
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bool last = size_to_fill == cur_trans->size_remaining;
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desc->last_descriptor = last;
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desc->second_address_chained = 1;
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desc->owned_by_idmac = 1;
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desc->buffer1_ptr = cur_trans->ptr;
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desc->next_desc_ptr = (last) ? NULL : slot->ctlr->dma_desc + ((next + 1) % num_desc);
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assert(size_to_fill < 4 || size_to_fill % 4 == 0);
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desc->buffer1_size = (size_to_fill + 3) & (~3);
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cur_trans->size_remaining -= size_to_fill;
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cur_trans->ptr += size_to_fill;
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cur_trans->next_desc = (cur_trans->next_desc + 1) % num_desc;
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ESP_LOGV(TAG, "fill %d desc=%d rem=%d next=%d last=%d sz=%d",
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num_desc, next, cur_trans->size_remaining,
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cur_trans->next_desc, desc->last_descriptor, desc->buffer1_size);
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#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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esp_err_t ret = esp_cache_msync((void *)desc, sizeof(sdmmc_desc_t), ESP_CACHE_MSYNC_FLAG_DIR_C2M);
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assert(ret == ESP_OK);
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#endif
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}
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}
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void sd_host_dma_stop(sd_host_sdmmc_slot_t *slot)
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{
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sdmmc_ll_stop_dma(slot->ctlr->hal.dev);
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}
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void sd_host_dma_resume(sd_host_sdmmc_slot_t *slot)
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{
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sdmmc_ll_poll_demand(slot->ctlr->hal.dev);
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}
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void sd_host_dma_prepare(sd_host_sdmmc_slot_t *slot, void *data_ptr, size_t data_size, size_t block_size)
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{
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// this clears "owned by IDMAC" bits
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memset(slot->ctlr->dma_desc, 0, sizeof(sdmmc_desc_t) * slot->ctlr->dma_desc_num);
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// initialize first descriptor
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sdmmc_desc_t *desc = slot->ctlr->dma_desc;
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desc->first_descriptor = 1;
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// save transfer info
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slot->ctlr->cur_transfer.ptr = data_ptr;
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slot->ctlr->cur_transfer.size_remaining = data_size;
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slot->ctlr->cur_transfer.next_desc = 0;
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slot->ctlr->cur_transfer.desc_remaining = (data_size + SDMMC_DMA_MAX_BUF_LEN - 1) / SDMMC_DMA_MAX_BUF_LEN;
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// prepare descriptors
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sd_host_fill_dma_descriptors(slot, slot->ctlr->dma_desc_num);
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// Set size of data and DMA descriptor pointer
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sdmmc_ll_set_data_transfer_len(slot->ctlr->hal.dev, data_size);
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sdmmc_ll_set_block_size(slot->ctlr->hal.dev, block_size);
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sdmmc_ll_set_desc_addr(slot->ctlr->hal.dev, (uint32_t)desc);
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// Enable everything needed to use DMA
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sdmmc_ll_enable_dma(slot->ctlr->hal.dev, true);
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sd_host_dma_resume(slot);
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}
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/*---------------------------------------------------------------
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CMD
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---------------------------------------------------------------*/
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static bool cmd_needs_auto_stop(const sdmmc_command_t *cmd)
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{
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/* SDMMC host needs an "auto stop" flag for the following commands: */
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return cmd->datalen > 0 &&
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(cmd->opcode == MMC_WRITE_BLOCK_MULTIPLE ||
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cmd->opcode == MMC_READ_BLOCK_MULTIPLE ||
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cmd->opcode == MMC_WRITE_DAT_UNTIL_STOP ||
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cmd->opcode == MMC_READ_DAT_UNTIL_STOP);
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}
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static sdmmc_hw_cmd_t make_hw_cmd(sdmmc_command_t *cmd)
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{
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sdmmc_hw_cmd_t res = { 0 };
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res.cmd_index = cmd->opcode;
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if (cmd->opcode == MMC_STOP_TRANSMISSION) {
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res.stop_abort_cmd = 1;
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} else if (cmd->opcode == MMC_GO_IDLE_STATE) {
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res.send_init = 1;
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} else if (cmd->opcode == SD_SWITCH_VOLTAGE) {
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res.volt_switch = 1;
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} else {
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res.wait_complete = 1;
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}
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if (cmd->opcode == MMC_GO_IDLE_STATE) {
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res.send_init = 1;
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}
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if (cmd->flags & SCF_RSP_PRESENT) {
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res.response_expect = 1;
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if (cmd->flags & SCF_RSP_136) {
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res.response_long = 1;
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}
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}
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if (cmd->flags & SCF_RSP_CRC) {
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res.check_response_crc = 1;
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}
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if (cmd->data) {
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res.data_expected = 1;
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if ((cmd->flags & SCF_CMD_READ) == 0) {
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res.rw = 1;
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}
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assert(cmd->datalen % cmd->blklen == 0);
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res.send_auto_stop = cmd_needs_auto_stop(cmd) ? 1 : 0;
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}
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ESP_LOGV(TAG, "%s: opcode=%d, rexp=%d, crc=%d, auto_stop=%d", __func__,
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res.cmd_index, res.response_expect, res.check_response_crc,
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res.send_auto_stop);
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return res;
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}
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static inline bool mask_check_and_clear(uint32_t *state, uint32_t mask)
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{
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bool ret = ((*state) & mask) != 0;
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*state &= ~mask;
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return ret;
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}
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static void process_command_response(sd_host_sdmmc_slot_t *slot, uint32_t status, sdmmc_command_t *cmd)
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{
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if (cmd->flags & SCF_RSP_PRESENT) {
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if (cmd->flags & SCF_RSP_136) {
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/* Destination is 4-byte aligned, can memcopy from peripheral registers */
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memcpy(cmd->response, (uint32_t*) SDMMC.resp, 4 * sizeof(uint32_t));
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} else {
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cmd->response[0] = SDMMC.resp[0];
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cmd->response[1] = 0;
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cmd->response[2] = 0;
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cmd->response[3] = 0;
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}
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}
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esp_err_t err = ESP_OK;
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if (status & SDMMC_INTMASK_RTO) {
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// response timeout is only possible when response is expected
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assert(cmd->flags & SCF_RSP_PRESENT);
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err = ESP_ERR_TIMEOUT;
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} else if ((cmd->flags & SCF_RSP_CRC) && (status & SDMMC_INTMASK_RCRC)) {
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err = ESP_ERR_INVALID_CRC;
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} else if (status & SDMMC_INTMASK_RESP_ERR) {
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err = ESP_ERR_INVALID_RESPONSE;
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}
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if (err != ESP_OK) {
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cmd->error = err;
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if (cmd->data) {
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sd_host_dma_stop(slot);
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}
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ESP_LOGD(TAG, "%s: error 0x%x (status=%08"PRIx32")", __func__, err, status);
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}
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}
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/*---------------------------------------------------------------
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Events
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---------------------------------------------------------------*/
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static esp_err_t sd_host_wait_for_event(sd_host_sdmmc_slot_t *slot, int tick_count, sd_host_sdmmc_event_t *out_event)
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{
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assert(out_event);
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assert(slot->ctlr->event_queue);
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int ret = xQueueReceive(slot->ctlr->event_queue, out_event, tick_count);
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if (ret == pdFALSE) {
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return ESP_ERR_TIMEOUT;
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}
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return ESP_OK;
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}
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static esp_err_t sd_host_handle_idle_state_events(sd_host_sdmmc_slot_t *slot)
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{
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/* Handle any events which have happened in between transfers.
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* Under current assumptions (no SDIO support) only card detect events
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* can happen in the idle state.
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*/
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sd_host_sdmmc_event_t evt;
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while (sd_host_wait_for_event(slot, 0, &evt) == ESP_OK) {
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if (evt.sdmmc_status & SDMMC_INTMASK_CD) {
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ESP_LOGV(TAG, "card detect event");
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evt.sdmmc_status &= ~SDMMC_INTMASK_CD;
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}
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if (evt.sdmmc_status != 0 || evt.dma_status != 0) {
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ESP_LOGE(TAG, "handle_idle_state_events unhandled: %08"PRIx32" %08"PRIx32,
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evt.sdmmc_status, evt.dma_status);
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}
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}
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return ESP_OK;
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}
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static void process_data_status(sd_host_sdmmc_slot_t *slot, uint32_t status, sdmmc_command_t *cmd)
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{
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if (status & SD_DATA_ERR_MASK) {
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if (status & SDMMC_INTMASK_DTO) {
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cmd->error = ESP_ERR_TIMEOUT;
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} else if (status & SDMMC_INTMASK_DCRC) {
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cmd->error = ESP_ERR_INVALID_CRC;
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} else if ((status & SDMMC_INTMASK_EBE) &&
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(cmd->flags & SCF_CMD_READ) == 0) {
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cmd->error = ESP_ERR_TIMEOUT;
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} else {
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cmd->error = ESP_FAIL;
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}
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SDMMC.ctrl.fifo_reset = 1;
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}
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if (cmd->error != 0) {
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if (cmd->data) {
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sd_host_dma_stop(slot);
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}
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ESP_LOGD(TAG, "%s: error 0x%x (status=%08"PRIx32")", __func__, cmd->error, status);
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}
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}
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static esp_err_t process_events(sd_host_sdmmc_slot_t *slot, sd_host_sdmmc_event_t evt, sdmmc_command_t *cmd,
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sdmmc_req_state_t *pstate, sd_host_sdmmc_event_t *unhandled_events)
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{
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const char* const s_state_names[] __attribute__((unused)) = {
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"IDLE",
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"SENDING_CMD",
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"SENDIND_DATA",
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"BUSY",
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"SENDING_VOLTAGE_SWITCH",
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"WAITING_VOLTAGE_SWITCH",
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};
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sd_host_sdmmc_event_t orig_evt = evt;
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ESP_LOGV(TAG, "%s: slot_id=%d state=%s evt=%"PRIx32" dma=%"PRIx32, __func__, slot->slot_id,
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s_state_names[*pstate], evt.sdmmc_status, evt.dma_status);
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sdmmc_req_state_t next_state = *pstate;
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sdmmc_req_state_t state = (sdmmc_req_state_t) -1;
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while (next_state != state) {
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state = next_state;
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switch (state) {
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case SDMMC_IDLE:
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break;
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case SDMMC_SENDING_CMD:
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if (mask_check_and_clear(&evt.sdmmc_status, SD_CMD_ERR_MASK)) {
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process_command_response(slot, orig_evt.sdmmc_status, cmd);
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// In addition to the error interrupt, CMD_DONE will also be
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// reported. It may occur immediately (in the same sd_host_sdmmc_event_t) or
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// be delayed until the next interrupt.
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}
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if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_CMD_DONE)) {
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process_command_response(slot, orig_evt.sdmmc_status, cmd);
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if (cmd->error != ESP_OK) {
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next_state = SDMMC_IDLE;
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break;
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}
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if (cmd->data == NULL) {
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next_state = SDMMC_IDLE;
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} else {
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next_state = SDMMC_SENDING_DATA;
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}
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}
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break;
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case SDMMC_SENDING_VOLTAGE_SWITCH:
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if (mask_check_and_clear(&evt.sdmmc_status, SD_CMD_ERR_MASK)) {
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process_command_response(slot, orig_evt.sdmmc_status, cmd);
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next_state = SDMMC_IDLE;
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}
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if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_VOLT_SW)) {
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handle_voltage_switch_stage2(slot, cmd);
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if (cmd->error != ESP_OK) {
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next_state = SDMMC_IDLE;
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} else {
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next_state = SDMMC_WAITING_VOLTAGE_SWITCH;
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}
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}
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break;
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case SDMMC_WAITING_VOLTAGE_SWITCH:
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if (mask_check_and_clear(&evt.sdmmc_status, SD_CMD_ERR_MASK)) {
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process_command_response(slot, orig_evt.sdmmc_status, cmd);
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next_state = SDMMC_IDLE;
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}
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if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_VOLT_SW)) {
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handle_voltage_switch_stage3(slot, cmd);
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next_state = SDMMC_IDLE;
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}
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break;
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case SDMMC_SENDING_DATA:
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if (mask_check_and_clear(&evt.sdmmc_status, SD_DATA_ERR_MASK)) {
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||||
process_data_status(slot, orig_evt.sdmmc_status, cmd);
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||||
sd_host_dma_stop(slot);
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}
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||||
if (mask_check_and_clear(&evt.dma_status, SD_DMA_DONE_MASK)) {
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||||
next_state = SDMMC_BUSY;
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||||
}
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||||
if (orig_evt.sdmmc_status & (SDMMC_INTMASK_SBE | SDMMC_INTMASK_DATA_OVER)) {
|
||||
// On start bit error, DATA_DONE interrupt will not be generated
|
||||
next_state = SDMMC_IDLE;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case SDMMC_BUSY:
|
||||
if (!mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_DATA_OVER)) {
|
||||
break;
|
||||
}
|
||||
process_data_status(slot, orig_evt.sdmmc_status, cmd);
|
||||
next_state = SDMMC_IDLE;
|
||||
break;
|
||||
}
|
||||
ESP_LOGV(TAG, "%s state=%s next_state=%s", __func__, s_state_names[state], s_state_names[next_state]);
|
||||
}
|
||||
*pstate = state;
|
||||
*unhandled_events = evt;
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static esp_err_t handle_event(sd_host_sdmmc_slot_t *slot, sdmmc_command_t* cmd, sdmmc_req_state_t *state,
|
||||
sd_host_sdmmc_event_t *unhandled_events)
|
||||
{
|
||||
sd_host_sdmmc_event_t event;
|
||||
esp_err_t err = sd_host_wait_for_event(slot, cmd->timeout_ms / portTICK_PERIOD_MS, &event);
|
||||
if (err != ESP_OK) {
|
||||
ESP_LOGE(TAG, "sd_host_wait_for_event returned 0x%x", err);
|
||||
if (err == ESP_ERR_TIMEOUT) {
|
||||
sd_host_dma_stop(slot);
|
||||
}
|
||||
return err;
|
||||
}
|
||||
ESP_LOGV(TAG, "sdmmc_handle_event: slot_id %d event %08"PRIx32" %08"PRIx32", unhandled %08"PRIx32" %08"PRIx32,
|
||||
slot->slot_id, event.sdmmc_status, event.dma_status,
|
||||
unhandled_events->sdmmc_status, unhandled_events->dma_status);
|
||||
event.sdmmc_status |= unhandled_events->sdmmc_status;
|
||||
event.dma_status |= unhandled_events->dma_status;
|
||||
process_events(slot, event, cmd, state, unhandled_events);
|
||||
ESP_LOGV(TAG, "sdmmc_handle_event: slot_id %d events unhandled: %08"PRIx32" %08"PRIx32, slot->slot_id, unhandled_events->sdmmc_status, unhandled_events->dma_status);
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
static bool sd_host_card_busy(sd_host_sdmmc_slot_t *slot)
|
||||
{
|
||||
return sdmmc_ll_is_card_data_busy(slot->ctlr->hal.dev);
|
||||
}
|
||||
|
||||
static bool wait_for_busy_cleared(sd_host_sdmmc_slot_t *slot, uint32_t timeout_ms)
|
||||
{
|
||||
if (timeout_ms == 0) {
|
||||
return !sd_host_card_busy(slot);
|
||||
}
|
||||
|
||||
/* It would have been nice to do this without polling, however the peripheral
|
||||
* can only generate Busy Clear Interrupt for data write commands, and waiting
|
||||
* for busy clear is mostly needed for other commands such as MMC_SWITCH.
|
||||
*/
|
||||
uint32_t timeout_ticks = (timeout_ms + portTICK_PERIOD_MS - 1) / portTICK_PERIOD_MS;
|
||||
while (timeout_ticks-- > 0) {
|
||||
if (!sd_host_card_busy(slot)) {
|
||||
return true;
|
||||
}
|
||||
vTaskDelay(1);
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Public API Impl
|
||||
---------------------------------------------------------------*/
|
||||
esp_err_t sd_host_slot_sdmmc_do_transaction(sd_host_slot_handle_t slot, sdmmc_command_t *cmdinfo)
|
||||
{
|
||||
esp_err_t ret = ESP_FAIL;
|
||||
ESP_RETURN_ON_FALSE(slot && cmdinfo, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
|
||||
sd_host_sdmmc_slot_t *slot_ctx = __containerof(slot, sd_host_sdmmc_slot_t, drv);
|
||||
|
||||
xSemaphoreTake(slot_ctx->ctlr->mutex, portMAX_DELAY);
|
||||
if (slot_ctx->ctlr->pm_lock) {
|
||||
ESP_GOTO_ON_ERROR(esp_pm_lock_acquire(slot_ctx->ctlr->pm_lock), out, TAG, "acquire pm_lock failed");
|
||||
}
|
||||
slot_ctx->ctlr->cur_slot_id = slot_ctx->slot_id;
|
||||
|
||||
// By default, set probing frequency (400kHz) and 1-bit bus
|
||||
if (slot_ctx->freq.freq_state != SD_HOST_SLOT_STATE_READY) {
|
||||
ESP_GOTO_ON_ERROR(sd_host_slot_set_card_clk(slot_ctx), out, TAG, "failed to set clk");
|
||||
} else {
|
||||
int real_freq_khz = 0;
|
||||
ret = sd_host_slot_get_real_freq(slot_ctx, &real_freq_khz);
|
||||
assert(ret == ESP_OK);
|
||||
if (real_freq_khz != (slot_ctx->freq.freq_hz / 1000)) {
|
||||
ESP_GOTO_ON_ERROR(sd_host_slot_set_card_clk(slot_ctx), out, TAG, "failed to set clk");
|
||||
}
|
||||
}
|
||||
ESP_GOTO_ON_ERROR(sd_host_slot_set_bus_width(slot_ctx), out, TAG, "failed to set width");
|
||||
ESP_GOTO_ON_ERROR(sd_host_slot_set_bus_sampling_mode(slot_ctx), out, TAG, "failed to set sampling mode");
|
||||
ESP_GOTO_ON_ERROR(sd_host_set_delay_phase(slot_ctx), out, TAG, "failed to set delay phase");
|
||||
ESP_GOTO_ON_ERROR(sd_host_set_delay_line(slot_ctx), out, TAG, "failed to set delay line");
|
||||
|
||||
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
|
||||
// cache sync related
|
||||
size_t cache_sync_len = 0;
|
||||
#endif
|
||||
|
||||
// dispose of any events which happened asynchronously
|
||||
sd_host_handle_idle_state_events(slot_ctx);
|
||||
|
||||
// special handling for voltage switch command
|
||||
if (cmdinfo->opcode == SD_SWITCH_VOLTAGE) {
|
||||
handle_voltage_switch_stage1(slot_ctx, cmdinfo);
|
||||
}
|
||||
|
||||
// convert cmdinfo to hardware register value
|
||||
sdmmc_hw_cmd_t hw_cmd = make_hw_cmd(cmdinfo);
|
||||
if (cmdinfo->data) {
|
||||
// Length should be either <4 or >=4 and =0 (mod 4).
|
||||
if (cmdinfo->datalen >= 4 && cmdinfo->datalen % 4 != 0) {
|
||||
ESP_LOGE(TAG, "%s: invalid size: total=%d",
|
||||
__func__, cmdinfo->datalen);
|
||||
ret = ESP_ERR_INVALID_SIZE;
|
||||
goto out;
|
||||
}
|
||||
|
||||
bool is_aligned = sd_host_check_buffer_alignment(slot_ctx, cmdinfo->data, cmdinfo->buflen);
|
||||
if (!is_aligned) {
|
||||
ESP_LOGE(TAG, "%s: buffer %p can not be used for DMA", __func__, cmdinfo->data);
|
||||
ret = ESP_ERR_INVALID_ARG;
|
||||
goto out;
|
||||
}
|
||||
|
||||
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
|
||||
cache_sync_len = cmdinfo->buflen;
|
||||
ret = esp_cache_msync((void *)cmdinfo->data, cache_sync_len, ESP_CACHE_MSYNC_FLAG_DIR_C2M);
|
||||
if (ret != ESP_OK) {
|
||||
goto out;
|
||||
}
|
||||
#endif
|
||||
// write transfer info into hardware
|
||||
sd_host_dma_prepare(slot_ctx, cmdinfo->data, cmdinfo->datalen, cmdinfo->blklen);
|
||||
}
|
||||
// write command into hardware, this also sends the command to the card
|
||||
ret = sd_host_slot_start_command(slot_ctx, hw_cmd, cmdinfo->arg);
|
||||
if (ret != ESP_OK) {
|
||||
goto out;
|
||||
}
|
||||
// process events until transfer is complete
|
||||
cmdinfo->error = ESP_OK;
|
||||
sdmmc_req_state_t state = SDMMC_SENDING_CMD;
|
||||
if (cmdinfo->opcode == SD_SWITCH_VOLTAGE) {
|
||||
state = SDMMC_SENDING_VOLTAGE_SWITCH;
|
||||
}
|
||||
sd_host_sdmmc_event_t unhandled_events = {};
|
||||
while (state != SDMMC_IDLE) {
|
||||
ret = handle_event(slot_ctx, cmdinfo, &state, &unhandled_events);
|
||||
if (ret != ESP_OK) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (ret == ESP_OK && (cmdinfo->flags & SCF_WAIT_BUSY)) {
|
||||
if (!wait_for_busy_cleared(slot_ctx, cmdinfo->timeout_ms)) {
|
||||
ret = ESP_ERR_TIMEOUT;
|
||||
}
|
||||
}
|
||||
slot_ctx->ctlr->is_app_cmd = (ret == ESP_OK && cmdinfo->opcode == MMC_APP_CMD);
|
||||
|
||||
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
|
||||
if (cmdinfo->data) {
|
||||
ret = esp_cache_msync((void *)cmdinfo->data, cache_sync_len, ESP_CACHE_MSYNC_FLAG_DIR_M2C);
|
||||
if (ret != ESP_OK) {
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
out:
|
||||
if (slot_ctx->ctlr->pm_lock) {
|
||||
ESP_RETURN_ON_ERROR(esp_pm_lock_release(slot_ctx->ctlr->pm_lock), TAG, "release pm_lock failed");
|
||||
}
|
||||
xSemaphoreGive(slot_ctx->ctlr->mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
Reference in New Issue
Block a user