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Merge branch 'bugfix/clear_ledc_gamma_ram_v5.3' into 'release/v5.3'

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fix(ledc): left-off gamma ram registers should be cleared (v5.3)

See merge request espressif/esp-idf!37573
This commit is contained in:
morris
2025-04-16 10:19:51 +08:00
parent aa9900290a 0ced5fbd21
commit 3f9d5cac2a
10 changed files with 83 additions and 25 deletions
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components/hal/esp32c6/include/hal/ledc_ll.h
+3 -1
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@@ -16,6 +16,7 @@
#include "soc/clk_tree_defs.h"
#include "hal/assert.h"
#include "esp_rom_sys.h" //for sync issue workaround
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
@@ -442,6 +443,7 @@ static inline void ledc_ll_set_duty_range_wr_addr(ledc_dev_t *hw, ledc_mode_t sp
*/
static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step)
{
HAL_ASSERT(range < SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX);
// To workaround sync issue
// This is to ensure the fade param write to the gamma_wr register would not mess up the last wr_addr
ledc_ll_set_duty_range_wr_addr(hw, speed_mode, channel_num, range);
@@ -539,7 +541,7 @@ static inline void ledc_ll_get_fade_param(ledc_dev_t *hw, ledc_mode_t speed_mode
static inline void ledc_ll_get_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t *dir, uint32_t *cycle, uint32_t *scale, uint32_t *step)
{
// On ESP32C6/H2, gamma ram read/write has the APB and LEDC clock domain sync issue
// To make sure the parameter read is from the correct gamma ram addr, add a delay in between to ensure syncronization
// To make sure the parameter read is from the correct gamma ram addr, add a delay in between to ensure synchronization
ledc_ll_set_duty_range_rd_addr(hw, speed_mode, channel_num, range);
esp_rom_delay_us(5);
ledc_ll_get_fade_param(hw, speed_mode, channel_num, dir, cycle, scale, step);