From 3f6957450f9ad64a58f071a5ea17f5d9ef2932e3 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Mon, 27 Apr 2026 20:11:59 +0800 Subject: [PATCH] feat(esp_hw_support): support psram PD_TOP retention --- .../esp32s31/include/hal/clk_tree_ll.h | 2 + .../esp32p4/include/hal/mspi_ll.h | 4 +- .../esp32s31/include/hal/mspi_ll.h | 40 ++++++++++++++++++ components/esp_hw_support/Kconfig | 2 +- .../esp_hw_support/port/esp32p4/pmu_sleep.c | 4 +- .../esp_hw_support/port/esp32s31/pmu_param.c | 4 +- .../esp_hw_support/port/esp32s31/pmu_sleep.c | 42 +++++++++++++++++++ .../port/esp32s31/private_include/pmu_param.h | 4 +- .../esp_pm/test_apps/.build-test-rules.yml | 4 +- components/esp_pm/test_apps/esp_pm/README.md | 4 +- .../esp_pm/test_apps/esp_pm/pytest_esp_pm.py | 1 - .../esp_system_unity_tests/main/test_sleep.c | 2 +- .../esp32s31/include/soc/Kconfig.soc_caps.in | 4 ++ .../soc/esp32s31/include/soc/soc_caps.h | 1 + .../include/soc/system_periph_retention.h | 4 +- .../soc/esp32s31/system_retention_periph.c | 28 ++++++------- 16 files changed, 119 insertions(+), 31 deletions(-) diff --git a/components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h index e01cb2b81bf..eaa36ca3a0f 100644 --- a/components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h @@ -153,6 +153,7 @@ static inline __attribute__((always_inline)) void clk_ll_mpll_enable(void) SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_HIGH_GLOBAL_MPLL_ICG) ; SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_HIGH_XPD_MPLL | PMU_TIE_HIGH_XPD_MPLL_I2C); SET_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN); + SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_CK_POWER_REG, PMU_HP_ACTIVE_XPD_MPLL_I2C | PMU_HP_ACTIVE_XPD_MPLL); } /** @@ -163,6 +164,7 @@ static inline __attribute__((always_inline)) void clk_ll_mpll_disable(void) SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_LOW_GLOBAL_MPLL_ICG) ; SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_1_REG, PMU_TIE_LOW_XPD_MPLL | PMU_TIE_LOW_XPD_MPLL_I2C); CLEAR_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN); + CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_CK_POWER_REG, PMU_HP_ACTIVE_XPD_MPLL_I2C | PMU_HP_ACTIVE_XPD_MPLL); } /** diff --git a/components/esp_hal_mspi/esp32p4/include/hal/mspi_ll.h b/components/esp_hal_mspi/esp32p4/include/hal/mspi_ll.h index 7e87504bf2d..03e37cfe96d 100644 --- a/components/esp_hal_mspi/esp32p4/include/hal/mspi_ll.h +++ b/components/esp_hal_mspi/esp32p4/include/hal/mspi_ll.h @@ -802,7 +802,7 @@ static inline void mspi_ll_unhold_all_flash_pins(void) * Sets all PSRAM pins (pin_group0, dqs0, pin_group1, dqs1) to hold status */ __attribute__((always_inline)) -static inline void mspi_ll_hold_all_psram_pins(void) +static inline void mspi_ll_psram_hold_all_pins(void) { #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 // Only rev3+ chips support mspi pad holding. LP_SYS.ded_pad_rtc_hold_ctrl.ded_pad_rtc_hold_ctrl |= 0x3FFFFC0; @@ -814,7 +814,7 @@ static inline void mspi_ll_hold_all_psram_pins(void) * Releases hold status for all PSRAM pins (pin_group0, dqs0, pin_group1, dqs1) */ __attribute__((always_inline)) -static inline void mspi_ll_unhold_all_psram_pins(void) +static inline void mspi_ll_psram_unhold_all_pins(void) { #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 // Only rev3+ chips support mspi pad holding. LP_SYS.ded_pad_rtc_hold_ctrl.ded_pad_rtc_hold_ctrl &= ~0x3FFFFC0; diff --git a/components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h b/components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h index 0cf056203fb..d58f5f8fad5 100644 --- a/components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h +++ b/components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h @@ -304,6 +304,46 @@ static inline void mspi_ll_psram_enable_axi_access(uint8_t spi_num, bool enable) SPIMEM2.mem_cache_fctrl.close_axi_inf_en = !enable; } +/** + * @brief Hold all PSRAM pins + * Sets all PSRAM pins (pin_group0, dqs0, pin_group1, dqs1) to hold status + */ +__attribute__((always_inline)) +static inline void mspi_ll_psram_hold_all_pins(void) +{ + MSPI_IOMUX.psram_pin_group.pin_group0[0].reg_psram_pin_hold = 1; + MSPI_IOMUX.psram_pin_group.pin_group0[1].reg_psram_pin_hold = 1; + MSPI_IOMUX.psram_pin_group.pin_group0[2].reg_psram_pin_hold = 1; + MSPI_IOMUX.psram_pin_group.pin_group0[3].reg_psram_pin_hold = 1; + MSPI_IOMUX.psram_pin_group.pin_group0[4].reg_psram_pin_hold = 1; + MSPI_IOMUX.psram_pin_group.pin_group0[5].reg_psram_pin_hold = 1; + MSPI_IOMUX.psram_pin_group.pin_group0[6].reg_psram_pin_hold = 1; + MSPI_IOMUX.psram_pin_group.pin_group0[7].reg_psram_pin_hold = 1; + MSPI_IOMUX.psram_pin_group.dqs0.reg_psram_dqs_hold = 1; + MSPI_IOMUX.psram_pin_group.pin_clk.reg_psram_pin_hold = 1; + MSPI_IOMUX.psram_pin_group.pin_cs.reg_psram_pin_hold = 1; +} + +/** + * @brief Unhold all PSRAM pins + * Releases hold status for all PSRAM pins (pin_group0, dqs0, pin_group1, dqs1) + */ +__attribute__((always_inline)) +static inline void mspi_ll_psram_unhold_all_pins(void) +{ + MSPI_IOMUX.psram_pin_group.pin_group0[0].reg_psram_pin_hold = 0; + MSPI_IOMUX.psram_pin_group.pin_group0[1].reg_psram_pin_hold = 0; + MSPI_IOMUX.psram_pin_group.pin_group0[2].reg_psram_pin_hold = 0; + MSPI_IOMUX.psram_pin_group.pin_group0[3].reg_psram_pin_hold = 0; + MSPI_IOMUX.psram_pin_group.pin_group0[4].reg_psram_pin_hold = 0; + MSPI_IOMUX.psram_pin_group.pin_group0[5].reg_psram_pin_hold = 0; + MSPI_IOMUX.psram_pin_group.pin_group0[6].reg_psram_pin_hold = 0; + MSPI_IOMUX.psram_pin_group.pin_group0[7].reg_psram_pin_hold = 0; + MSPI_IOMUX.psram_pin_group.dqs0.reg_psram_dqs_hold = 0; + MSPI_IOMUX.psram_pin_group.pin_clk.reg_psram_pin_hold = 0; + MSPI_IOMUX.psram_pin_group.pin_cs.reg_psram_pin_hold = 0; +} + #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig index f6769fd8d09..7cbca55944e 100644 --- a/components/esp_hw_support/Kconfig +++ b/components/esp_hw_support/Kconfig @@ -82,7 +82,7 @@ menu "Hardware Settings" select PM_SLP_IRAM_OPT select ESP_PERIPH_CTRL_FUNC_IN_IRAM select ESP_REGI2C_CTRL_FUNC_IN_IRAM - depends on !SPIRAM || ESP_LDO_RESERVE_PSRAM + depends on !SPIRAM || ESP_LDO_RESERVE_PSRAM || SOC_PSRAM_HAS_DEDICATED_LDO depends on !(IDF_TARGET_ESP32P4 && (ESP32P4_REV_MIN_FULL < 100)) default n help diff --git a/components/esp_hw_support/port/esp32p4/pmu_sleep.c b/components/esp_hw_support/port/esp32p4/pmu_sleep.c index 1d7bca046f5..e8a108d14db 100644 --- a/components/esp_hw_support/port/esp32p4/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32p4/pmu_sleep.c @@ -422,7 +422,7 @@ SPM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, #if CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED esp_psram_impl_enter_halfsleep_mode(); #endif - mspi_ll_hold_all_psram_pins(); + mspi_ll_psram_hold_all_pins(); #endif s_mpll_freq_mhz_before_sleep = rtc_clk_mpll_get_freq(); if (s_mpll_freq_mhz_before_sleep) { @@ -519,7 +519,7 @@ SPM_IRAM_ATTR bool pmu_sleep_finish(bool dslp) #endif } #if CONFIG_SPIRAM - mspi_ll_unhold_all_psram_pins(); + mspi_ll_psram_unhold_all_pins(); #if CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED esp_psram_impl_exit_halfsleep_mode(); #endif diff --git a/components/esp_hw_support/port/esp32s31/pmu_param.c b/components/esp_hw_support/port/esp32s31/pmu_param.c index 2fc17e5e225..eccb737e869 100644 --- a/components/esp_hw_support/port/esp32s31/pmu_param.c +++ b/components/esp_hw_support/port/esp32s31/pmu_param.c @@ -42,11 +42,11 @@ ESP_HW_LOG_ATTR_TAG(TAG, "pmu_param"); .xpd_cpll_i2c = 1, \ .xpd_bbpll_i2c = 1, \ .xpd_apll_i2c = 0, \ - .xpd_mpll_i2c = 0, \ + .xpd_mpll_i2c = 1, \ .xpd_cpll = 1, \ .xpd_bbpll = 1, \ .xpd_apll = 0, \ - .xpd_mpll = 0, \ + .xpd_mpll = 1, \ }, \ .xtal = { \ .xpd_xtal = 1 \ diff --git a/components/esp_hw_support/port/esp32s31/pmu_sleep.c b/components/esp_hw_support/port/esp32s31/pmu_sleep.c index 29e61e36958..a13585a6bd7 100644 --- a/components/esp_hw_support/port/esp32s31/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32s31/pmu_sleep.c @@ -16,10 +16,21 @@ #include "soc/pmu_struct.h" #include "esp_private/esp_pmu.h" #include "pmu_param.h" +#include "hal/clk_tree_hal.h" #include "hal/lp_aon_hal.h" #include "hal/efuse_ll.h" #include "hal/efuse_hal.h" +#include "hal/mspi_ll.h" #include "esp_hw_log.h" +#if CONFIG_SPIRAM +#include "esp_private/esp_psram_impl.h" +#include "hal/psram_ctrlr_ll.h" +#endif +#if !SOC_APM_SUPPORTED +#include "hal/apm_hal.h" +#endif + +#include "esp_private/rtc_clk.h" ESP_HW_LOG_ATTR_TAG(TAG, "pmu_sleep"); @@ -28,6 +39,7 @@ ESP_HW_LOG_ATTR_TAG(TAG, "pmu_sleep"); static bool s_pmu_sleep_regdma_backup_enabled; +static uint32_t s_mpll_freq_mhz_before_sleep = 0; void pmu_sleep_enable_regdma_backup(void) { @@ -320,6 +332,16 @@ void pmu_sleep_init(const pmu_sleep_config_t *config, bool dslp) IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp) { + if (!dslp) { +#if CONFIG_SPIRAM + psram_ctrlr_ll_wait_all_transaction_done(); +#if CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED + esp_psram_impl_enter_halfsleep_mode(); +#endif + mspi_ll_psram_hold_all_pins(); +#endif + s_mpll_freq_mhz_before_sleep = rtc_clk_mpll_get_freq(); + } lp_aon_hal_inform_wakeup_type(dslp); pmu_ll_hp_set_wakeup_enable(&PMU, wakeup_opt); @@ -354,6 +376,26 @@ IRAM_ATTR bool pmu_sleep_finish(bool dslp) // Wait eFuse memory update done. while(efuse_ll_get_controller_state() != EFUSE_CONTROLLER_STATE_IDLE); #endif + + if (!dslp) { + if (s_mpll_freq_mhz_before_sleep) { + rtc_clk_mpll_enable(); + rtc_clk_mpll_configure(clk_hal_xtal_get_freq_mhz(), s_mpll_freq_mhz_before_sleep, false); + } +#if CONFIG_SPIRAM + mspi_ll_psram_unhold_all_pins(); +#if CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED + esp_psram_impl_exit_halfsleep_mode(); +#endif +#endif + } + +#if !SOC_APM_SUPPORTED + apm_hal_enable_ctrl_filter_all(false); +#else + ESP_STATIC_ASSERT(0, "TEE/APM retention need to be supported!"); +#endif + return pmu_ll_hp_is_sleep_reject(&PMU); } diff --git a/components/esp_hw_support/port/esp32s31/private_include/pmu_param.h b/components/esp_hw_support/port/esp32s31/private_include/pmu_param.h index 48b4555cd97..cb8f5c1f0e1 100644 --- a/components/esp_hw_support/port/esp32s31/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32s31/private_include/pmu_param.h @@ -360,7 +360,7 @@ typedef struct { .hp_sys = { \ .analog = { \ .drv_b = PMU_HP_DRVB_LIGHTSLEEP, \ - .pd_cur = PMU_PD_CUR_SLEEP_DEFAULT, \ + .pd_cur = PMU_PD_CUR_SLEEP_ON, \ .bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \ .xpd = PMU_HP_XPD_LIGHTSLEEP, \ .dbg_atten = PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT, \ @@ -370,7 +370,7 @@ typedef struct { .lp_sys[PMU_MODE_LP_SLEEP] = { \ .analog = { \ .drv_b = PMU_LP_DRVB_LIGHTSLEEP, \ - .pd_cur = PMU_PD_CUR_SLEEP_DEFAULT, \ + .pd_cur = PMU_PD_CUR_SLEEP_ON, \ .bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \ .slp_xpd = PMU_LP_SLP_XPD_SLEEP_DEFAULT, \ .slp_dbias = PMU_LP_SLP_DBIAS_SLEEP_DEFAULT, \ diff --git a/components/esp_pm/test_apps/.build-test-rules.yml b/components/esp_pm/test_apps/.build-test-rules.yml index bfdf55d31ac..bed18a701bc 100644 --- a/components/esp_pm/test_apps/.build-test-rules.yml +++ b/components/esp_pm/test_apps/.build-test-rules.yml @@ -5,9 +5,9 @@ components/esp_pm/test_apps: - if: INCLUDE_DEFAULT == 1 disable: - if: CONFIG_NAME == "pm_pd_top_sleep" and IDF_TARGET not in ["esp32c5", "esp32c6", "esp32h2", "esp32p4"] - - if: IDF_TARGET in ["esp32h21", "esp32h4", "esp32s31"] + - if: IDF_TARGET in ["esp32h21", "esp32h4"] temporary: true - reason: not support yet # TODO: [ESP32H21] IDF-11522, [ESP32H4] IDF-12286 [ESP32S31] IDF-14645 + reason: not support yet # TODO: [ESP32H21] IDF-11522, [ESP32H4] IDF-12286 depends_components: - *common_components - esp_pm diff --git a/components/esp_pm/test_apps/esp_pm/README.md b/components/esp_pm/test_apps/esp_pm/README.md index 7b96141437e..be7ab2904d9 100644 --- a/components/esp_pm/test_apps/esp_pm/README.md +++ b/components/esp_pm/test_apps/esp_pm/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- | diff --git a/components/esp_pm/test_apps/esp_pm/pytest_esp_pm.py b/components/esp_pm/test_apps/esp_pm/pytest_esp_pm.py index d7a65e69174..51a0b28ef1e 100644 --- a/components/esp_pm/test_apps/esp_pm/pytest_esp_pm.py +++ b/components/esp_pm/test_apps/esp_pm/pytest_esp_pm.py @@ -17,7 +17,6 @@ from pytest_embedded_idf.utils import idf_parametrize indirect=True, ) @idf_parametrize('target', ['supported_targets'], indirect=['target']) -@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done') def test_esp_pm(dut: Dut) -> None: dut.run_all_single_board_cases() diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c index 8bc4e4973e5..2f6f74e1cef 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in index 2399a115845..ca45cf59db6 100644 --- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in @@ -727,6 +727,10 @@ config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR bool default y +config SOC_PSRAM_HAS_DEDICATED_LDO + bool + default y + config SOC_MEMSPI_IS_INDEPENDENT bool default y diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h index ee6401d6a26..988dfe2a0da 100644 --- a/components/soc/esp32s31/include/soc/soc_caps.h +++ b/components/soc/esp32s31/include/soc/soc_caps.h @@ -294,6 +294,7 @@ #define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1) #define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1) +#define SOC_PSRAM_HAS_DEDICATED_LDO 1 #define SOC_MEMSPI_IS_INDEPENDENT 1 #define SOC_PSRAM_MEMSPI_IS_INDEPENDENT 1 diff --git a/components/soc/esp32s31/include/soc/system_periph_retention.h b/components/soc/esp32s31/include/soc/system_periph_retention.h index 345955df495..29b30a18efd 100644 --- a/components/soc/esp32s31/include/soc/system_periph_retention.h +++ b/components/soc/esp32s31/include/soc/system_periph_retention.h @@ -62,7 +62,7 @@ extern const regdma_entries_config_t hp_system_regs_retention[HP_SYSTEM_RETENTIO * This is an internal function of the sleep retention driver, and is not * useful for external use. */ -#define IOMUX_RETENTION_LINK_LEN 5 +#define IOMUX_RETENTION_LINK_LEN 4 extern const regdma_entries_config_t iomux_regs_retention[IOMUX_RETENTION_LINK_LEN]; /** @@ -82,7 +82,7 @@ extern const regdma_entries_config_t flash_spimem_regs_retention[SPIMEM_FLASH_RE * This is an internal function of the sleep retention driver, and is not * useful for external use. */ -#define SPIMEM_PSRAM_RETENTION_LINK_LEN 5 +#define SPIMEM_PSRAM_RETENTION_LINK_LEN 15 extern const regdma_entries_config_t psram_spimem_regs_retention[SPIMEM_PSRAM_RETENTION_LINK_LEN]; /** diff --git a/components/soc/esp32s31/system_retention_periph.c b/components/soc/esp32s31/system_retention_periph.c index 2627754605b..3876a816785 100644 --- a/components/soc/esp32s31/system_retention_periph.c +++ b/components/soc/esp32s31/system_retention_periph.c @@ -19,7 +19,6 @@ #include "soc/spi1_mem_s_reg.h" #include "soc/systimer_reg.h" #include "soc/timer_group_reg.h" -// #include "soc/timer_periph.h" #include "soc/uart_reg.h" #include "esp32s31/rom/cache.h" #include "soc/hp_apm_reg.h" @@ -52,7 +51,6 @@ const regdma_entries_config_t cache_regs_retention[] = { }; _Static_assert(ARRAY_SIZE(cache_regs_retention) == CACHE_RETENTION_LINK_LEN, "Inconsistent L2 CACHE retention link length definitions"); -#if SOC_APM_SUPPORTED /* TEE APM Registers Context */ #define N_REGS_TEE_0() (((TEE_M87_MODE_CTRL_REG - TEE_M0_MODE_CTRL_REG) / 4) + 1) #define N_REGS_TEE_1() (((TEE_SUPERVISOR_PRIV_SEL_REG - TEE_SUPERVISOR_PRIV_SEL_REG) / 4) + 1) @@ -87,7 +85,6 @@ const regdma_entries_config_t tee_apm_regs_retention[] = { [13] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TEEAPM_LINK(0x0d), HP_PERI1_PMS_BUS_ERR_CONF_REG, HP_PERI1_PMS_BUS_ERR_CONF_REG, N_REGS_PMS1_2(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, }; _Static_assert(ARRAY_SIZE(tee_apm_regs_retention) == TEE_APM_RETENTION_LINK_LEN, "Inconsistent HP_SYSTEM retention link length definitions"); -#endif /* HP System Registers Context */ #define N_REGS_HP_SYSTEM() (((HP_SYSTEM_GMAC1_PAD_BIST_INT_ENA_REG - DR_REG_HP_SYS_BASE) / 4) + 1) @@ -98,7 +95,6 @@ _Static_assert(ARRAY_SIZE(hp_system_regs_retention) == HP_SYSTEM_RETENTION_LINK_ /* IO MUX Registers Context */ #define N_REGS_IOMUX() (((IO_MUX_GPIO62_REG - REG_IO_MUX_BASE) / 4) + 1) -#define N_REGS_MSPI_IOMUX() (((IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG - IOMUX_MSPI_PIN_CLK_EN0_REG) / 4) + 1) #define N_REGS_GPIO_PINx() (((GPIO_PIN62_REG - GPIO_PIN0_REG) / 4) + 1) #define N_REGS_GPIO_FUNC_IN() (((GPIO_FUNC255_IN_SEL_CFG_REG - GPIO_FUNC0_IN_SEL_CFG_REG) / 4) + 1) #define N_REGS_GPIO_FUNC_OUT() (((GPIO_FUNC62_OUT_SEL_CFG_REG - GPIO_FUNC0_OUT_SEL_CFG_REG) / 4) + 1) @@ -106,13 +102,11 @@ _Static_assert(ARRAY_SIZE(hp_system_regs_retention) == HP_SYSTEM_RETENTION_LINK_ const regdma_entries_config_t iomux_regs_retention[] = { /* IO_MUX */ [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x00), REG_IO_MUX_BASE, REG_IO_MUX_BASE, N_REGS_IOMUX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - /* MSPI IOMUX */ - [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x01), IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG, IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG, N_REGS_MSPI_IOMUX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* GPIO_PIN0_REG ~ GPIO_PIN62_REG*/ - [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x02), GPIO_PIN0_REG, GPIO_PIN0_REG, N_REGS_GPIO_PINx(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x01), GPIO_PIN0_REG, GPIO_PIN0_REG, N_REGS_GPIO_PINx(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, /* GPIO_FUNC0_IN_SEL_CFG_REG ~ GPIO_FUNC255_IN_SEL_CFG_REG & GPIO_FUNC0_OUT_SEL_CFG_REG ~ GPIO_FUNC0_IN_SEL_CFG_REG */ - [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x03), GPIO_FUNC0_IN_SEL_CFG_REG, GPIO_FUNC0_IN_SEL_CFG_REG, N_REGS_GPIO_FUNC_IN(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, - [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x04), GPIO_FUNC0_OUT_SEL_CFG_REG, GPIO_FUNC0_OUT_SEL_CFG_REG, N_REGS_GPIO_FUNC_OUT(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x02), GPIO_FUNC0_IN_SEL_CFG_REG, GPIO_FUNC0_IN_SEL_CFG_REG, N_REGS_GPIO_FUNC_IN(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, + [3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_IOMUX_LINK(0x03), GPIO_FUNC0_OUT_SEL_CFG_REG, GPIO_FUNC0_OUT_SEL_CFG_REG, N_REGS_GPIO_FUNC_OUT(), 0, 0), .owner = ENTRY(0) | ENTRY(2) }, }; _Static_assert(ARRAY_SIZE(iomux_regs_retention) == IOMUX_RETENTION_LINK_LEN, "Inconsistent IOMUX retention link length definitions"); @@ -139,11 +133,17 @@ const regdma_entries_config_t flash_spimem_regs_retention[] = { _Static_assert(ARRAY_SIZE(flash_spimem_regs_retention) == SPIMEM_FLASH_RETENTION_LINK_LEN, "Inconsistent Flash SPI Mem retention link length definitions"); #if CONFIG_SPIRAM -#define N_REGS_SPI0_S_MEM_0() (((SPI_MEM_S_INT_ENA_REG - SPI_MEM_S_CTRL_REG) / 4) + 1) -#define N_REGS_SPI0_S_MEM_1() (((SPI_MEM_S_CLOCK_GATE_REG - SPI_MEM_S_DDR_REG) / 4) + 1) -#define N_REGS_SPI1_S_MEM_0() (((SPI1_MEM_S_INT_ENA_REG - SPI1_MEM_S_CMD_REG) / 4) + 1) -#define N_REGS_SPI1_S_MEM_1() (((SPI1_MEM_S_DDR_REG - SPI1_MEM_S_DDR_REG) / 4) + 1) -#define N_REGS_SPI1_S_MEM_2() (((SPI1_MEM_S_TIMING_CALI_REG - SPI1_MEM_S_TIMING_CALI_REG) / 4) + 1) +#define N_REGS_SPI0_S_MEM_0() (((SPI_MEM_S_USER2_REG - SPI_MEM_S_CTRL_REG) / 4) + 1) +#define N_REGS_SPI0_S_MEM_1() (((SPI_MEM_S_FSM_REG - SPI_MEM_S_MISC_REG) / 4) + 1) +#define N_REGS_SPI0_S_MEM_2() (((SPI_SMEM_S_DDR_REG - SPI_MEM_S_INT_ENA_REG) / 4) + 1) +#define N_REGS_SPI0_S_MEM_3() (((SPI_SMEM_S_DOUT_HEX_MODE_REG - SPI_MEM_S_ECC_CTRL_REG) / 4) + 1) +#define N_REGS_SPI0_S_MEM_4() (((SPI_MEM_S_DPA_CTRL_REG - SPI_MEM_S_MMU_POWER_CTRL_REG) / 4) + 1) +#define N_REGS_SPI1_S_MEM_0() ((SPI1_MEM_S_CACHE_FCTRL_REG - SPI1_MEM_S_CMD_REG) / 4 + 1) +#define N_REGS_SPI1_S_MEM_1() (((SPI1_MEM_S_SUS_STATUS_REG - SPI1_MEM_S_FLASH_WAITI_CTRL_REG) / 4) + 1) +#define N_REGS_SPI1_S_MEM_2() (((SPI1_MEM_S_DDR_REG - SPI1_MEM_S_INT_ENA_REG) / 4) + 1) +#define N_REGS_SPI1_S_MEM_3() (1) +#define N_REGS_SPI1_S_MEM_4() (1) +#define N_REGS_MSPI1_IOMUX() (((IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG - IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG) / 4) + 1) const regdma_entries_config_t psram_spimem_regs_retention[SPIMEM_PSRAM_RETENTION_LINK_LEN] = { [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_SPIMEM_LINK(0x07), HP_SYS_CLKRST_PSRAM_CTRL0_REG, HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN, HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN_M, 1, 0), .owner = ENTRY(0) | ENTRY(2) }, // Enable PSRAM mspi core clock on restore