mirror of
https://github.com/espressif/esp-idf.git
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Merge branch 'refactor/make_mspi_hal_independent' into 'master'
refactor(mspi): Make mspi hal layer independent See merge request espressif/esp-idf!42035
This commit is contained in:
C.S.M
@@ -1,19 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* Background
|
||||
*
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||||
* This file is for the MSPI related, but not Flash driver related registers, these registers:
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||||
* - may influence both Flash and PSRAM
|
||||
* - not related or directly related to Flash controller driver
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||||
*
|
||||
* Some hints for naming convention:
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||||
* - For MSPI timing tuning related registers, the LL should start with `mspi_timing_ll_`
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||||
* - For others, the LL should start with `mspi_ll_`
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*/
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||||
|
||||
//For compatibility
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||||
@@ -1,112 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
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||||
* The ll is not public api, don't use in application code.
|
||||
* See readme.md in hal/include/hal/readme.md
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||||
******************************************************************************/
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||||
|
||||
// The Lowlevel layer for SPI Flash Encryption.
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||||
#pragma once
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||||
|
||||
#include "soc/dport_reg.h"
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||||
#include "soc/flash_encryption_reg.h"
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||||
#include <stdbool.h>
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||||
|
||||
#ifdef __cplusplus
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||||
extern "C" {
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||||
#endif
|
||||
|
||||
/**
|
||||
* Enable encryption in flash
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||||
*/
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||||
static inline void spi_flash_encrypt_ll_enable(void)
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||||
{
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||||
DPORT_REG_SET_BIT(DPORT_SLAVE_SPI_CONFIG_REG, DPORT_SLAVE_SPI_MASK_PRO | DPORT_SPI_ENCRYPT_ENABLE);
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||||
}
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||||
|
||||
/**
|
||||
* Disable encryption in flash
|
||||
*/
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||||
static inline void spi_flash_encrypt_ll_disable(void)
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||||
{
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||||
DPORT_REG_CLR_BIT(DPORT_SLAVE_SPI_CONFIG_REG, DPORT_SLAVE_SPI_MASK_PRO | DPORT_SPI_ENCRYPT_ENABLE);
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}
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|
||||
/**
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* Copy the flash address to physical address
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*
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* @param flash_addr The flash address.
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*
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* @note the address must be 8-byte aligned
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*/
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static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
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{
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REG_WRITE(FLASH_ENCRYPTION_ADDRESS_REG, flash_addr);
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}
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|
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/**
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* Wait for flash encryption operation completeness.
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*/
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static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
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{
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while(!(REG_READ(FLASH_ENCRYPTION_DONE_REG) & BIT(0))) {
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}
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}
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|
||||
/**
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* Start encryption on data buffer.
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*/
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static inline void spi_flash_encrypt_ll_calculate_start(void)
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{
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REG_WRITE(FLASH_ENCRYPTION_START_REG, BIT(0));
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}
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/**
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* Save the plaintext for encryption
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*
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* @param address address of the partition to be written.
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* @param buffer Buffer to store the input data.
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* @param size Buffer size.
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*/
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static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size)
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{
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for (int i = 0; i < 8; i++) {
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REG_WRITE(FLASH_ENCRYPTION_BUFFER_REG + (i << 2), buffer[i]);
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}
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}
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/**
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* Finish the flash encryption and make encrypted result accessible to SPI.
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*/
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static inline void spi_flash_encrypt_ll_done(void)
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||||
{
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||||
// Do nothing on ESP32
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||||
}
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||||
|
||||
/**
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||||
* Set to destroy encrypted result
|
||||
*/
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static inline void spi_flash_encrypt_ll_destroy(void)
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||||
{
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// Do nothing on ESP32
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||||
}
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||||
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||||
/**
|
||||
* Check if is qualified to encrypt the buffer
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||||
*
|
||||
* @param address the address of written flash partition.
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||||
* @param length Buffer size.
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||||
*/
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||||
static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length)
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||||
{
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||||
return ((address % 16) == 0) ? true : false;
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||||
}
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||||
|
||||
#ifdef __cplusplus
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||||
}
|
||||
#endif
|
||||
@@ -1,527 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
* The ll is not public api, don't use in application code.
|
||||
* See readme.md in hal/include/hal/readme.md
|
||||
******************************************************************************/
|
||||
|
||||
// The Lowlevel layer for SPI Flash
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|
||||
#pragma once
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|
||||
#include <stdlib.h>
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#include "soc/spi_periph.h"
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||||
#include "soc/spi_struct.h"
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#include "hal/spi_types.h"
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||||
#include "hal/spi_flash_types.h"
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||||
#include <sys/param.h> // For MIN/MAX
|
||||
#include <stdbool.h>
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||||
#include <string.h>
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||||
#include "hal/misc.h"
|
||||
|
||||
#ifdef __cplusplus
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||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define SPI_FLASH_LL_CLOCK_FREQUENCY_MHZ (80)
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/// Get the start address of SPI peripheral registers by the host ID
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#define spi_flash_ll_get_hw(host_id) ( ((host_id)==SPI1_HOST) ? &SPI1 :(\
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((host_id)==SPI2_HOST) ? &SPI2 :(\
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((host_id)==SPI3_HOST) ? &SPI3 :(\
|
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{abort();(spi_dev_t*)0;}\
|
||||
))) )
|
||||
#define spi_flash_ll_hw_get_id(dev) ( ((dev) == &SPI1) ? SPI1_HOST :(\
|
||||
((dev) == &SPI2) ? SPI2_HOST :(\
|
||||
((dev) == &SPI3) ? SPI3_HOST :(\
|
||||
-1\
|
||||
))) )
|
||||
|
||||
/// Empty function to be compatible with new version chips.
|
||||
#define spi_flash_ll_set_dummy_out(dev, out_en, out_lev)
|
||||
|
||||
// On ESP32, we extent 4 bits to occupy `Continuous Read Mode` bits. (same to origin code.)
|
||||
#define SPI_FLASH_LL_CONTINUOUS_MODE_BIT_NUMS (4)
|
||||
|
||||
#define SPIMEM_LL_APB SPI1
|
||||
#define SPIMEM_LL_CACHE SPI0
|
||||
|
||||
/// type to store pre-calculated register value in above layers
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||||
typedef typeof(SPI1.clock.val) spi_flash_ll_clock_reg_t;
|
||||
|
||||
/*------------------------------------------------------------------------------
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||||
* Control
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||||
*----------------------------------------------------------------------------*/
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||||
/**
|
||||
* Reset peripheral registers before configuration and starting control
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||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
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||||
*/
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static inline void spi_flash_ll_reset(spi_dev_t *dev)
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||||
{
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||||
dev->user.val = 0;
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||||
dev->ctrl.val = 0;
|
||||
}
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||||
|
||||
/**
|
||||
* Check whether the previous operation is done.
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||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
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*
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* @return true if last command is done, otherwise false.
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*/
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static inline bool spi_flash_ll_cmd_is_done(const spi_dev_t *dev)
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{
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return (dev->cmd.val == 0);
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||||
}
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||||
|
||||
/**
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||||
* Erase the flash chip.
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||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_flash_ll_erase_chip(spi_dev_t *dev)
|
||||
{
|
||||
dev->cmd.flash_ce = 1;
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||||
}
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||||
|
||||
/**
|
||||
* Erase the sector, the address should be set by spi_flash_ll_set_address.
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||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
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||||
*/
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||||
static inline void spi_flash_ll_erase_sector(spi_dev_t *dev)
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{
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||||
dev->ctrl.val = 0;
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dev->cmd.flash_se = 1;
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||||
}
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||||
|
||||
/**
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* Erase the block, the address should be set by spi_flash_ll_set_address.
|
||||
*
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||||
* @param dev Beginning address of the peripheral registers.
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||||
*/
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||||
static inline void spi_flash_ll_erase_block(spi_dev_t *dev)
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||||
{
|
||||
dev->cmd.flash_be = 1;
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||||
}
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||||
|
||||
/**
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||||
* Enable/disable write protection for the flash chip.
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||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
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||||
* @param wp true to enable the protection, false to disable (write enable).
|
||||
*/
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||||
static inline void spi_flash_ll_set_write_protect(spi_dev_t *dev, bool wp)
|
||||
{
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||||
if (wp) {
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||||
dev->cmd.flash_wrdi = 1;
|
||||
} else {
|
||||
dev->cmd.flash_wren = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the read data from the buffer after ``spi_flash_ll_read`` is done.
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*
|
||||
* @param dev Beginning address of the peripheral registers.
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||||
* @param buffer Buffer to hold the output data
|
||||
* @param read_len Length to get out of the buffer
|
||||
*/
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||||
__attribute__((always_inline))
|
||||
static inline void spi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len)
|
||||
{
|
||||
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
|
||||
// If everything is word-aligned, do a faster memcpy
|
||||
memcpy(buffer, (void *)dev->data_buf, read_len);
|
||||
} else {
|
||||
// Otherwise, slow(er) path copies word by word
|
||||
int copy_len = read_len;
|
||||
for (size_t i = 0; i < (read_len + 3) / 4; i++) {
|
||||
int word_len = MIN(sizeof(uint32_t), copy_len);
|
||||
uint32_t word = dev->data_buf[i];
|
||||
memcpy(buffer, &word, word_len);
|
||||
buffer = (void *)((intptr_t)buffer + word_len);
|
||||
copy_len -= word_len;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Write a word to the data buffer.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param word Data to write at address 0.
|
||||
*/
|
||||
static inline void spi_flash_ll_write_word(spi_dev_t *dev, uint32_t word)
|
||||
{
|
||||
dev->data_buf[0] = word;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the data to be written in the data buffer.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param buffer Buffer holding the data
|
||||
* @param length Length of data in bytes.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void spi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *buffer, uint32_t length)
|
||||
{
|
||||
// Load data registers, word at a time
|
||||
int num_words = (length + 3) >> 2;
|
||||
for (int i = 0; i < num_words; i++) {
|
||||
uint32_t word = 0;
|
||||
uint32_t word_len = MIN(length, sizeof(word));
|
||||
memcpy(&word, buffer, word_len);
|
||||
dev->data_buf[i] = word;
|
||||
length -= word_len;
|
||||
buffer = (void *)((intptr_t)buffer + word_len);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Program a page of the flash chip. Call ``spi_flash_ll_set_address`` before
|
||||
* this to set the address to program.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param buffer Buffer holding the data to program
|
||||
* @param length Length to program.
|
||||
*/
|
||||
static inline void spi_flash_ll_program_page(spi_dev_t *dev, const void *buffer, uint32_t length)
|
||||
{
|
||||
dev->user.usr_dummy = 0;
|
||||
spi_flash_ll_set_buffer_data(dev, buffer, length);
|
||||
dev->cmd.flash_pp = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Trigger a user defined transaction. All phases, including command, address, dummy, and the data phases,
|
||||
* should be configured before this is called.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_flash_ll_user_start(spi_dev_t *dev, bool pe_ops)
|
||||
{
|
||||
dev->cmd.usr = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Check whether the host is idle to perform new commands.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*
|
||||
* @return true if the host is idle, otherwise false
|
||||
*/
|
||||
static inline bool spi_flash_ll_host_idle(const spi_dev_t *dev)
|
||||
{
|
||||
return dev->ext2.st == 0;
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Configs
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Select which pin to use for the flash
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins.
|
||||
*/
|
||||
static inline void spi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
|
||||
{
|
||||
dev->pin.cs0_dis = (pin != 0);
|
||||
dev->pin.cs1_dis = (pin != 1);
|
||||
dev->pin.cs2_dis = (pin != 2);
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the read io mode.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param read_mode I/O mode to use in the following transactions.
|
||||
*/
|
||||
static inline void spi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
|
||||
{
|
||||
typeof (dev->ctrl) ctrl;
|
||||
ctrl.val = dev->ctrl.val;
|
||||
ctrl.val = ctrl.val & ~(SPI_FREAD_QIO_M | SPI_FREAD_QUAD_M | SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M);
|
||||
ctrl.val = ctrl.val | SPI_FASTRD_MODE_M;
|
||||
switch (read_mode) {
|
||||
case SPI_FLASH_FASTRD:
|
||||
//the default option
|
||||
break;
|
||||
case SPI_FLASH_QIO:
|
||||
ctrl.fread_qio = 1;
|
||||
break;
|
||||
case SPI_FLASH_QOUT:
|
||||
ctrl.fread_quad = 1;
|
||||
break;
|
||||
case SPI_FLASH_DIO:
|
||||
ctrl.fread_dio = 1;
|
||||
break;
|
||||
case SPI_FLASH_DOUT:
|
||||
ctrl.fread_dual = 1;
|
||||
break;
|
||||
case SPI_FLASH_SLOWRD:
|
||||
ctrl.fastrd_mode = 0;
|
||||
break;
|
||||
default:
|
||||
abort();
|
||||
}
|
||||
dev->ctrl.val = ctrl.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set clock frequency to work at.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param clock_val pointer to the clock value to set
|
||||
*/
|
||||
static inline void spi_flash_ll_set_clock(spi_dev_t *dev, spi_flash_ll_clock_reg_t *clock_val)
|
||||
{
|
||||
dev->clock.val = *clock_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the input length, in bits.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param bitlen Length of input, in bits.
|
||||
*/
|
||||
static inline void spi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
dev->user.usr_miso = bitlen > 0;
|
||||
dev->miso_dlen.usr_miso_dbitlen = bitlen ? (bitlen - 1) : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the output length, in bits (not including command, address and dummy
|
||||
* phases)
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param bitlen Length of output, in bits.
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void spi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
dev->user.usr_mosi = bitlen > 0;
|
||||
dev->mosi_dlen.usr_mosi_dbitlen = bitlen ? (bitlen - 1) : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the command.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param command Command to send
|
||||
* @param bitlen Length of the command
|
||||
*/
|
||||
static inline void spi_flash_ll_set_command(spi_dev_t *dev, uint8_t command, uint32_t bitlen)
|
||||
{
|
||||
dev->user.usr_command = 1;
|
||||
typeof(dev->user2) user2 = {
|
||||
.usr_command_value = command,
|
||||
.reserved16 = 0,
|
||||
.usr_command_bitlen = (bitlen - 1),
|
||||
};
|
||||
dev->user2.val = user2.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the address length that is set in register, in bits.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
*
|
||||
*/
|
||||
static inline int spi_flash_ll_get_addr_bitlen(spi_dev_t *dev)
|
||||
{
|
||||
return dev->user.usr_addr ? dev->user1.usr_addr_bitlen + 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the address length to send, in bits. Should be called before commands that requires the address e.g. erase sector, read, write...
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param bitlen Length of the address, in bits
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void spi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitlen)
|
||||
{
|
||||
dev->user1.usr_addr_bitlen = (bitlen - 1);
|
||||
dev->user.usr_addr = bitlen ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the address to send in user command mode. Should be called before commands that requires the address e.g. erase sector, read, write...
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param addr Address to send
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void spi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, int bit_len)
|
||||
{
|
||||
// The blank region should be all ones
|
||||
if (bit_len >= 32) {
|
||||
dev->addr = addr;
|
||||
dev->slv_wr_status = UINT32_MAX;
|
||||
} else {
|
||||
uint32_t padding_ones = UINT32_MAX >> bit_len;
|
||||
if (bit_len != 0) {
|
||||
dev->addr = (addr << (32 - bit_len)) | padding_ones;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the address to send. Should be called before commands that requires the address e.g. erase sector, read, write...
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param addr Address to send
|
||||
*/
|
||||
static inline void spi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
|
||||
{
|
||||
dev->addr = addr;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the length of dummy cycles.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param dummy_n Cycles of dummy phases
|
||||
*/
|
||||
static inline void spi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
|
||||
{
|
||||
dev->user.usr_dummy = dummy_n ? 1 : 0;
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
|
||||
}
|
||||
|
||||
static inline void spi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n)
|
||||
{
|
||||
dev->ctrl2.hold_time = hold_n;
|
||||
dev->user.cs_hold = (hold_n > 0? 1: 0);
|
||||
}
|
||||
|
||||
static inline void spi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
|
||||
{
|
||||
dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
|
||||
dev->ctrl2.setup_time = cs_setup_time - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the spi flash source clock frequency. Used for calculating
|
||||
* the divider parameters.
|
||||
*
|
||||
* @param host_id SPI host id. Not used in this function, but to keep
|
||||
* compatibility with other targets.
|
||||
*
|
||||
* @return the frequency of spi flash clock source.(MHz)
|
||||
*/
|
||||
static inline uint32_t spi_flash_ll_get_source_clock_freq_mhz(uint8_t host_id)
|
||||
{
|
||||
return SPI_FLASH_LL_CLOCK_FREQUENCY_MHZ;
|
||||
}
|
||||
|
||||
/**
|
||||
* Calculate spi_flash clock frequency division parameters for register.
|
||||
*
|
||||
* @param host_id SPI host id. Not used in this function, but to keep
|
||||
* compatibility with other targets.
|
||||
* @param clkdiv frequency division factor
|
||||
*
|
||||
* @return Register setting for the given clock division factor.
|
||||
*/
|
||||
static inline uint32_t spi_flash_ll_calculate_clock_reg(uint8_t host_id, uint8_t clkdiv)
|
||||
{
|
||||
uint32_t div_parameter;
|
||||
// See comments of `clock` in `spi_struct.h`
|
||||
if (clkdiv == 1) {
|
||||
div_parameter = (1 << 31);
|
||||
} else {
|
||||
div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12));
|
||||
}
|
||||
return div_parameter;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set extra address for bits M0-M7 in DIO/QIO mode.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param extra_addr extra address(M0-M7) to send.
|
||||
*/
|
||||
static inline void spi_flash_ll_set_extra_address(spi_dev_t *dev, uint32_t extra_addr)
|
||||
{
|
||||
// Not supported on ESP32.
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write protect signal output when SPI is idle
|
||||
|
||||
* @param level 1: 1: output high, 0: output low
|
||||
*/
|
||||
static inline void spi_flash_ll_set_wp_level(spi_dev_t *dev, bool level)
|
||||
{
|
||||
dev->ctrl.wp = level;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the ctrl value of mspi
|
||||
*
|
||||
* @return uint32_t The value of ctrl register
|
||||
*/
|
||||
static inline uint32_t spi_flash_ll_get_ctrl_val(spi_dev_t *dev)
|
||||
{
|
||||
return dev->ctrl.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset whole memory spi
|
||||
*/
|
||||
static inline void spi_flash_ll_sync_reset(void)
|
||||
{
|
||||
SPI1.slave.sync_reset = 0;
|
||||
SPI0.slave.sync_reset = 0;
|
||||
SPI1.slave.sync_reset = 1;
|
||||
SPI0.slave.sync_reset = 1;
|
||||
SPI1.slave.sync_reset = 0;
|
||||
SPI0.slave.sync_reset = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get common command related registers
|
||||
*
|
||||
* @param ctrl_reg ctrl_reg
|
||||
* @param user_reg user_reg
|
||||
* @param user1_reg user1_reg
|
||||
* @param user2_reg user2_reg
|
||||
*/
|
||||
static inline void spi_flash_ll_get_common_command_register_info(spi_dev_t *dev, uint32_t *ctrl_reg, uint32_t *user_reg, uint32_t *user1_reg, uint32_t *user2_reg)
|
||||
{
|
||||
*ctrl_reg = dev->ctrl.val;
|
||||
*user_reg = dev->user.val;
|
||||
*user1_reg = dev->user1.val;
|
||||
*user2_reg = dev->user2.val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set common command related registers
|
||||
*
|
||||
* @param ctrl_reg ctrl_reg
|
||||
* @param user_reg user_reg
|
||||
* @param user1_reg user1_reg
|
||||
* @param user2_reg user2_reg
|
||||
*/
|
||||
static inline void spi_flash_ll_set_common_command_register_info(spi_dev_t *dev, uint32_t ctrl_reg, uint32_t user_reg, uint32_t user1_reg, uint32_t user2_reg)
|
||||
{
|
||||
dev->ctrl.val = ctrl_reg;
|
||||
dev->user.val = user_reg;
|
||||
dev->user1.val = user1_reg;
|
||||
dev->user2.val = user2_reg;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user