From 3e32f8bb54354b364b5d7a1172c117fb58f1c88b Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Mon, 24 Aug 2026 11:12:01 +0800 Subject: [PATCH] feat(esp32h4): update rom.ld files for esp32h4 eco2 --- .../port/esp32h4/Kconfig.hw_support | 6 +- components/esp_libc/src/system_libs.lf | 2 + components/esp_rom/CMakeLists.txt | 13 +- components/esp_rom/esp32/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32/esp_rom_caps.h | 1 + .../esp_rom/esp32c2/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32c2/esp_rom_caps.h | 1 + .../esp_rom/esp32c3/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32c3/esp_rom_caps.h | 1 + .../esp_rom/esp32c5/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32c5/esp_rom_caps.h | 1 + .../esp_rom/esp32c6/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32c6/esp_rom_caps.h | 1 + .../esp_rom/esp32c61/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32c61/esp_rom_caps.h | 1 + .../esp_rom/esp32h2/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32h2/esp_rom_caps.h | 1 + .../esp_rom/esp32h21/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32h21/esp_rom_caps.h | 1 + .../esp_rom/esp32h4/ld/esp32h4.rom.eco0_1.ld | 403 ++++++++++++++++++ components/esp_rom/esp32h4/ld/esp32h4.rom.ld | 12 +- .../esp_rom/esp32h4/ld/esp32h4.rom.libgcc.ld | 95 ----- .../esp_rom/esp32p4/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32p4/esp_rom_caps.h | 1 + .../esp_rom/esp32s2/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32s2/esp_rom_caps.h | 1 + .../esp_rom/esp32s3/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32s3/esp_rom_caps.h | 1 + .../esp_rom/esp32s31/Kconfig.soc_caps.in | 4 + components/esp_rom/esp32s31/esp_rom_caps.h | 1 + 30 files changed, 483 insertions(+), 108 deletions(-) create mode 100644 components/esp_rom/esp32h4/ld/esp32h4.rom.eco0_1.ld delete mode 100644 components/esp_rom/esp32h4/ld/esp32h4.rom.libgcc.ld diff --git a/components/esp_hw_support/port/esp32h4/Kconfig.hw_support b/components/esp_hw_support/port/esp32h4/Kconfig.hw_support index 674b8004aac..55c5dfd4ebe 100644 --- a/components/esp_hw_support/port/esp32h4/Kconfig.hw_support +++ b/components/esp_hw_support/port/esp32h4/Kconfig.hw_support @@ -1,6 +1,3 @@ -comment "NOTE! Support of ESP32-H4 MP is mutually exclusive" -comment "Read the help text of the option below for explanation" - choice ESP32H4_REV_MIN prompt "Minimum Supported ESP32-H4 Revision" default ESP32H4_REV_MIN_0 @@ -14,11 +11,14 @@ choice ESP32H4_REV_MIN config ESP32H4_REV_MIN_0 bool "Rev v0.0" + config ESP32H4_REV_MIN_2 + bool "Rev v0.2" endchoice config ESP32H4_REV_MIN_FULL int default 0 if ESP32H4_REV_MIN_0 + default 2 if ESP32H4_REV_MIN_2 config ESP_REV_MIN_FULL int diff --git a/components/esp_libc/src/system_libs.lf b/components/esp_libc/src/system_libs.lf index 9c22bbfd475..a21bb32bc19 100644 --- a/components/esp_libc/src/system_libs.lf +++ b/components/esp_libc/src/system_libs.lf @@ -6,6 +6,8 @@ entries: _divsf3 (noflash) if IDF_TARGET_ARCH_RISCV: save-restore (noflash) + if !ESP_ROM_HAS_LIBGCC: + * (noflash) [mapping:clang_rt_builtins] archive: libclang_rt.builtins.a diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index 878c4c0fa30..af008a04c60 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -103,6 +103,9 @@ if(target STREQUAL "linux") else() if(CONFIG_ESP32P4_SELECTS_REV_LESS_V3) target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.eco0_4.ld") + elseif(CONFIG_IDF_TARGET_ESP32H4 AND CONFIG_ESP32H4_REV_MIN_FULL LESS 2) + # TODO(IDF-16110): Remove ESP32-H4 revision < 0.2 ROM compatibility support. + target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.eco0_1.ld") else() target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.ld") endif() @@ -114,10 +117,12 @@ else() endif() if(CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB) - if(CONFIG_ESP32P4_SELECTS_REV_LESS_V3) - rom_linker_script("eco0_4.libgcc") - else() - rom_linker_script("libgcc") + if(CONFIG_ESP_ROM_HAS_LIBGCC) + if(CONFIG_ESP32P4_SELECTS_REV_LESS_V3) + rom_linker_script("eco0_4.libgcc") + else() + rom_linker_script("libgcc") + endif() endif() else() if(CONFIG_ESP32P4_SELECTS_REV_LESS_V3) diff --git a/components/esp_rom/esp32/Kconfig.soc_caps.in b/components/esp_rom/esp32/Kconfig.soc_caps.in index 69f835455dd..4b138af237e 100644 --- a/components/esp_rom/esp32/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32/Kconfig.soc_caps.in @@ -39,6 +39,10 @@ config ESP_ROM_HAS_NEWLIB_32BIT_TIME bool default y +config ESP_ROM_HAS_LIBGCC + bool + default y + config ESP_ROM_HAS_SW_FLOAT bool default y diff --git a/components/esp_rom/esp32/esp_rom_caps.h b/components/esp_rom/esp32/esp_rom_caps.h index 04e311a2a8a..215a0a0d45e 100644 --- a/components/esp_rom/esp32/esp_rom_caps.h +++ b/components/esp_rom/esp32/esp_rom_caps.h @@ -15,6 +15,7 @@ #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions #define ESP_ROM_HAS_NEWLIB_32BIT_TIME (1) // ROM was compiled with 32 bit time_t +#define ESP_ROM_HAS_LIBGCC (1) // ROM has libgcc functions included #define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions #define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage. #define ESP_ROM_USB_SERIAL_DEVICE_NUM (-1) // No USB_SERIAL_JTAG in the ROM, set -1 for Kconfig usage. diff --git a/components/esp_rom/esp32c2/Kconfig.soc_caps.in b/components/esp_rom/esp32c2/Kconfig.soc_caps.in index 1e1d74eb493..de344a0807f 100644 --- a/components/esp_rom/esp32c2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c2/Kconfig.soc_caps.in @@ -67,6 +67,10 @@ config ESP_ROM_HAS_NEWLIB_NANO_FORMAT bool default y +config ESP_ROM_HAS_LIBGCC + bool + default y + config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE bool default y diff --git a/components/esp_rom/esp32c2/esp_rom_caps.h b/components/esp_rom/esp32c2/esp_rom_caps.h index 8b8653526ac..26f6f8fa22e 100644 --- a/components/esp_rom/esp32c2/esp_rom_caps.h +++ b/components/esp_rom/esp32c2/esp_rom_caps.h @@ -22,6 +22,7 @@ #define ESP_ROM_HAS_SPI_FLASH_MMAP (1) // ROM has the implementation of SPI Flash mmap driver #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions +#define ESP_ROM_HAS_LIBGCC (1) // ROM has libgcc functions included #define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init #define ESP_ROM_HAS_MBEDTLS_CRYPTO_LIB (1) // ROM has the mbedtls crypto algorithm lib diff --git a/components/esp_rom/esp32c3/Kconfig.soc_caps.in b/components/esp_rom/esp32c3/Kconfig.soc_caps.in index be2fb4402c6..3d4131e81b8 100644 --- a/components/esp_rom/esp32c3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c3/Kconfig.soc_caps.in @@ -75,6 +75,10 @@ config ESP_ROM_HAS_NEWLIB_32BIT_TIME bool default y +config ESP_ROM_HAS_LIBGCC + bool + default y + config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE bool default y diff --git a/components/esp_rom/esp32c3/esp_rom_caps.h b/components/esp_rom/esp32c3/esp_rom_caps.h index 578e0aac53c..130988adb78 100644 --- a/components/esp_rom/esp32c3/esp_rom_caps.h +++ b/components/esp_rom/esp32c3/esp_rom_caps.h @@ -24,6 +24,7 @@ #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions #define ESP_ROM_HAS_NEWLIB_32BIT_TIME (1) // ROM was compiled with 32 bit time_t +#define ESP_ROM_HAS_LIBGCC (1) // ROM has libgcc functions included #define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init #define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions diff --git a/components/esp_rom/esp32c5/Kconfig.soc_caps.in b/components/esp_rom/esp32c5/Kconfig.soc_caps.in index 85394c8c99d..8059c61a3bf 100644 --- a/components/esp_rom/esp32c5/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c5/Kconfig.soc_caps.in @@ -75,6 +75,10 @@ config ESP_ROM_HAS_NEWLIB_NANO_FORMAT bool default y +config ESP_ROM_HAS_LIBGCC + bool + default y + config ESP_ROM_WDT_INIT_PATCH bool default y diff --git a/components/esp_rom/esp32c5/esp_rom_caps.h b/components/esp_rom/esp32c5/esp_rom_caps.h index 8b3200b61eb..60eca90655f 100644 --- a/components/esp_rom/esp32c5/esp_rom_caps.h +++ b/components/esp_rom/esp32c5/esp_rom_caps.h @@ -24,6 +24,7 @@ #define ESP_ROM_HAS_SPI_FLASH_MMAP (1) // ROM has the implementation of SPI Flash mmap driver #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions +#define ESP_ROM_HAS_LIBGCC (1) // ROM has libgcc functions included #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock #define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init diff --git a/components/esp_rom/esp32c6/Kconfig.soc_caps.in b/components/esp_rom/esp32c6/Kconfig.soc_caps.in index 4ac69b2d7f0..dd898f28813 100644 --- a/components/esp_rom/esp32c6/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c6/Kconfig.soc_caps.in @@ -75,6 +75,10 @@ config ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT bool default y +config ESP_ROM_HAS_LIBGCC + bool + default y + config ESP_ROM_REV0_HAS_NO_ECDSA_INTERFACE bool default y diff --git a/components/esp_rom/esp32c6/esp_rom_caps.h b/components/esp_rom/esp32c6/esp_rom_caps.h index 00d8b2138dc..61404abf6b3 100644 --- a/components/esp_rom/esp32c6/esp_rom_caps.h +++ b/components/esp_rom/esp32c6/esp_rom_caps.h @@ -24,6 +24,7 @@ #define ESP_ROM_HAS_SPI_FLASH_MMAP (1) // ROM has the implementation of SPI Flash mmap driver #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions) +#define ESP_ROM_HAS_LIBGCC (1) // ROM has libgcc functions included #define ESP_ROM_REV0_HAS_NO_ECDSA_INTERFACE (1) // ECO 0 does not have ets_ecdsa_verify symbol, future revision will have it #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock #define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap diff --git a/components/esp_rom/esp32c61/Kconfig.soc_caps.in b/components/esp_rom/esp32c61/Kconfig.soc_caps.in index 199ba7765a7..528df11804a 100644 --- a/components/esp_rom/esp32c61/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c61/Kconfig.soc_caps.in @@ -79,6 +79,10 @@ config ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG bool default y +config ESP_ROM_HAS_LIBGCC + bool + default y + config ESP_ROM_HAS_VERSION bool default y diff --git a/components/esp_rom/esp32c61/esp_rom_caps.h b/components/esp_rom/esp32c61/esp_rom_caps.h index ad8a90120b6..0d829fca26f 100644 --- a/components/esp_rom/esp32c61/esp_rom_caps.h +++ b/components/esp_rom/esp32c61/esp_rom_caps.h @@ -25,6 +25,7 @@ #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions #define ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG (1) // ROM has the printf float bug with newlib nano version +#define ESP_ROM_HAS_LIBGCC (1) // ROM has libgcc functions included #define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init diff --git a/components/esp_rom/esp32h2/Kconfig.soc_caps.in b/components/esp_rom/esp32h2/Kconfig.soc_caps.in index 4a5f0c20c80..12d3835995c 100644 --- a/components/esp_rom/esp32h2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32h2/Kconfig.soc_caps.in @@ -71,6 +71,10 @@ config ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG bool default y +config ESP_ROM_HAS_LIBGCC + bool + default y + config ESP_ROM_WDT_INIT_PATCH bool default y diff --git a/components/esp_rom/esp32h2/esp_rom_caps.h b/components/esp_rom/esp32h2/esp_rom_caps.h index 0cf8cb293e7..b0b5464a176 100644 --- a/components/esp_rom/esp32h2/esp_rom_caps.h +++ b/components/esp_rom/esp32h2/esp_rom_caps.h @@ -23,6 +23,7 @@ #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano versions of formatting functions #define ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG (1) // ROM has the printf float bug with newlib nano version +#define ESP_ROM_HAS_LIBGCC (1) // ROM has libgcc functions included #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock #define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init diff --git a/components/esp_rom/esp32h21/Kconfig.soc_caps.in b/components/esp_rom/esp32h21/Kconfig.soc_caps.in index c9ff00cd838..ba40811b4f3 100644 --- a/components/esp_rom/esp32h21/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32h21/Kconfig.soc_caps.in @@ -67,6 +67,10 @@ config ESP_ROM_HAS_NEWLIB_NANO_FORMAT bool default y +config ESP_ROM_HAS_LIBGCC + bool + default y + config ESP_ROM_WDT_INIT_PATCH bool default y diff --git a/components/esp_rom/esp32h21/esp_rom_caps.h b/components/esp_rom/esp32h21/esp_rom_caps.h index 9557f00e70a..b687beab782 100644 --- a/components/esp_rom/esp32h21/esp_rom_caps.h +++ b/components/esp_rom/esp32h21/esp_rom_caps.h @@ -22,6 +22,7 @@ #define ESP_ROM_HAS_SPI_FLASH_MMAP (1) // ROM has the implementation of SPI Flash mmap driver #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano versions of formatting functions +#define ESP_ROM_HAS_LIBGCC (1) // ROM has libgcc functions included #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init #define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions diff --git a/components/esp_rom/esp32h4/ld/esp32h4.rom.eco0_1.ld b/components/esp_rom/esp32h4/ld/esp32h4.rom.eco0_1.ld new file mode 100644 index 00000000000..44b02fa5e3d --- /dev/null +++ b/components/esp_rom/esp32h4/ld/esp32h4.rom.eco0_1.ld @@ -0,0 +1,403 @@ +/* + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* ROM function interface esp32h4.rom.ld for esp32h4 + * + * + * Generated from ../../rom/target/esp32h4/interface-esp32h4.yml md5sum bb9ee317148d3c5b10610936a3675a65 + * + * Compatible with ROM where ECO version equal or greater to 0. + * + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + */ + +/*************************************** + Group common + ***************************************/ + +/* Functions */ +rtc_get_reset_reason = 0x40000018; +rtc_get_wakeup_cause = 0x4000001c; +pmu_enable_unhold_pads = 0x40000020; +ets_printf = 0x40000024; +ets_install_putc1 = 0x40000028; +ets_install_putc2 = 0x4000002c; +ets_install_uart_printf = 0x40000030; +ets_install_usb_printf = 0x40000034; +ets_get_printf_channel = 0x40000038; +ets_delay_us = 0x4000003c; +ets_get_cpu_frequency = 0x40000040; +ets_update_cpu_frequency = 0x40000044; +ets_install_lock = 0x40000048; +UartRxString = 0x4000004c; +UartGetCmdLn = 0x40000050; +uart_tx_one_char = 0x40000054; +uart_tx_one_char2 = 0x40000058; +uart_tx_one_char3 = 0x4000005c; +uart_rx_one_char = 0x40000060; +uart_rx_one_char_block = 0x40000064; +uart_rx_intr_handler = 0x40000068; +uart_rx_readbuff = 0x4000006c; +uartAttach = 0x40000070; +uart_tx_flush = 0x40000074; +uart_tx_wait_idle = 0x40000078; +uart_div_modify = 0x4000007c; +ets_write_char_uart = 0x40000080; +uart_tx_switch = 0x40000084; +uart_buff_switch = 0x40000088; +roundup2 = 0x4000008c; +multofup = 0x40000090; +software_reset = 0x40000094; +software_reset_cpu = 0x40000098; +ets_clk_assist_debug_clock_enable = 0x4000009c; +clear_super_wdt_reset_flag = 0x400000a0; +disable_default_watchdog = 0x400000a4; +ets_set_appcpu_boot_addr = 0x400000a8; +send_packet = 0x400000ac; +recv_packet = 0x400000b0; +GetUartDevice = 0x400000b4; +UartDwnLdProc = 0x400000b8; +GetSecurityInfoProc = 0x400000bc; +Uart_Init = 0x400000c0; +ets_set_user_start = 0x400000c4; +/* Data (.data, .bss, .rodata) */ +ets_rom_layout_p = 0x4001fffc; +ets_ops_table_ptr = 0x4085fff4; +g_saved_pc = 0x4085fff8; + + +/*************************************** + Group miniz + ***************************************/ + +/* Functions */ +mz_adler32 = 0x400000c8; +mz_free = 0x400000cc; +tdefl_compress = 0x400000d0; +tdefl_compress_buffer = 0x400000d4; +tdefl_compress_mem_to_heap = 0x400000d8; +tdefl_compress_mem_to_mem = 0x400000dc; +tdefl_compress_mem_to_output = 0x400000e0; +tdefl_get_adler32 = 0x400000e4; +tdefl_get_prev_return_status = 0x400000e8; +tdefl_init = 0x400000ec; +tdefl_write_image_to_png_file_in_memory = 0x400000f0; +tdefl_write_image_to_png_file_in_memory_ex = 0x400000f4; +tinfl_decompress = 0x400000f8; +tinfl_decompress_mem_to_callback = 0x400000fc; +tinfl_decompress_mem_to_heap = 0x40000100; +tinfl_decompress_mem_to_mem = 0x40000104; + + +/*************************************** + Group spi_extmem_common + ***************************************/ + +/* Functions */ +esp_rom_spi_cmd_config = 0x40000108; +esp_rom_spi_cmd_start = 0x4000010c; +esp_rom_spi_set_op_mode = 0x40000110; + + +/*************************************** + Group spiflash_legacy + ***************************************/ + +/* Functions */ +esp_rom_spiflash_wait_idle = 0x40000114; +esp_rom_spiflash_write_encrypted = 0x40000118; +esp_rom_spiflash_write_encrypted_dest = 0x4000011c; +esp_rom_spiflash_write_encrypted_enable = 0x40000120; +esp_rom_spiflash_write_encrypted_disable = 0x40000124; +esp_rom_spiflash_erase_chip = 0x40000128; +_esp_rom_spiflash_erase_sector = 0x4000012c; +_esp_rom_spiflash_erase_block = 0x40000130; +_esp_rom_spiflash_write = 0x40000134; +_esp_rom_spiflash_read = 0x40000138; +_esp_rom_spiflash_unlock = 0x4000013c; +_SPIEraseArea = 0x40000140; +_SPI_write_enable = 0x40000144; +esp_rom_spiflash_erase_sector = 0x40000148; +esp_rom_spiflash_erase_block = 0x4000014c; +esp_rom_spiflash_write = 0x40000150; +esp_rom_spiflash_read = 0x40000154; +esp_rom_spiflash_unlock = 0x40000158; +SPIEraseArea = 0x4000015c; +SPI_write_enable = 0x40000160; +esp_rom_spiflash_config_param = 0x40000164; +esp_rom_spiflash_read_user_cmd = 0x40000168; +esp_rom_spiflash_select_qio_pins = 0x4000016c; +esp_rom_spi_flash_auto_sus_res = 0x40000170; +esp_rom_spi_flash_send_resume = 0x40000174; +esp_rom_spi_flash_update_id = 0x40000178; +esp_rom_spiflash_config_clk = 0x4000017c; +esp_rom_spiflash_config_readmode = 0x40000180; +esp_rom_spiflash_read_status = 0x40000184; +esp_rom_spiflash_read_statushigh = 0x40000188; +esp_rom_spiflash_write_status = 0x4000018c; +esp_rom_spiflash_write_disable = 0x40000190; +spi_cache_mode_switch = 0x40000194; +spi_common_set_dummy_output = 0x40000198; +spi_common_set_flash_cs_timing = 0x4000019c; +esp_rom_spi_set_address_bit_len = 0x400001a0; +SPILock = 0x400001a4; +SPIMasterReadModeCnfig = 0x400001a8; +SPI_Common_Command = 0x400001ac; +SPI_WakeUp = 0x400001b0; +SPI_block_erase = 0x400001b4; +SPI_chip_erase = 0x400001b8; +SPI_init = 0x400001bc; +SPI_page_program = 0x400001c0; +SPI_read_data = 0x400001c4; +SPI_sector_erase = 0x400001c8; +SelectSpiFunction = 0x400001cc; +SetSpiDrvs = 0x400001d0; +Wait_SPI_Idle = 0x400001d4; +spi_dummy_len_fix = 0x400001d8; +Disable_QMode = 0x400001dc; +Enable_QMode = 0x400001e0; +spi_flash_attach = 0x400001e4; +spi_flash_get_chip_size = 0x400001e8; +spi_flash_guard_set = 0x400001ec; +spi_flash_guard_get = 0x400001f0; +spi_flash_read_encrypted = 0x400001f4; +/* Data (.data, .bss, .rodata) */ +rom_spiflash_legacy_funcs = 0x4085ffec; +rom_spiflash_legacy_data = 0x4085ffe8; +g_flash_guard_ops = 0x4085fff0; + + +/*************************************** + Group cache + ***************************************/ + +/* Functions */ +Cache_Get_Line_Size = 0x400005a8; +Cache_Get_Mode = 0x400005ac; +Cache_Address_Through_Cache = 0x400005b0; +ROM_Boot_Cache_Init = 0x400005b4; +Cache_Sync_Items = 0x400005b8; +Cache_Op_Addr = 0x400005bc; +Cache_Invalidate_Addr = 0x400005c0; +Cache_Clean_Addr = 0x400005c4; +PROVIDE( Cache_WriteBack_Addr = 0x400005c8 ); +PROVIDE( Cache_WriteBack_Invalidate_Addr = 0x400005cc ); +Cache_Invalidate_All = 0x400005d0; +Cache_Clean_All = 0x400005d4; +PROVIDE( Cache_WriteBack_All = 0x400005d8 ); +PROVIDE( Cache_WriteBack_Invalidate_All = 0x400005dc ); +Cache_Mask_All = 0x400005e0; +Cache_UnMask_Dram0 = 0x400005e4; +Cache_Suspend_Autoload = 0x400005e8; +Cache_Resume_Autoload = 0x400005ec; +Cache_Start_Preload = 0x400005f0; +Cache_Preload_Done = 0x400005f4; +Cache_End_Preload = 0x400005f8; +Cache_Config_Autoload = 0x400005fc; +Cache_Enable_Autoload = 0x40000600; +Cache_Disable_Autoload = 0x40000604; +Cache_Enable_PreLock = 0x40000608; +Cache_Disable_PreLock = 0x4000060c; +Cache_Lock_Items = 0x40000610; +Cache_Lock_Addr = 0x40000614; +Cache_Unlock_Addr = 0x40000618; +Cache_Disable_Cache = 0x4000061c; +Cache_Enable_Cache = 0x40000620; +Cache_Suspend_Cache = 0x40000624; +Cache_Resume_Cache = 0x40000628; +Cache_Freeze_Enable = 0x4000062c; +Cache_Freeze_Disable = 0x40000630; +Cache_Set_IDROM_MMU_Size = 0x40000634; +Cache_Get_IROM_MMU_End = 0x40000638; +Cache_Get_DROM_MMU_End = 0x4000063c; +Cache_MMU_Init = 0x40000640; +Cache_MSPI_MMU_Set = 0x40000644; +Cache_MSPI_MMU_Set_Secure = 0x40000648; +Cache_Count_Flash_Pages = 0x4000064c; +flash2spiram_instruction_offset = 0x40000650; +flash2spiram_rodata_offset = 0x40000654; +flash_instr_rodata_start_page = 0x40000658; +flash_instr_rodata_end_page = 0x4000065c; +Cache_Set_IDROM_MMU_Info = 0x40000660; +Cache_Flash_To_SPIRAM_Copy = 0x40000664; +/* Data (.data, .bss, .rodata) */ +rom_cache_op_cb = 0x4085ffc8; +rom_cache_internal_table_ptr = 0x4085ffc4; + + +/*************************************** + Group clock + ***************************************/ + +/* Functions */ +ets_clk_get_xtal_freq = 0x40000668; +ets_clk_get_cpu_freq = 0x4000066c; + + +/*************************************** + Group gpio + ***************************************/ + +/* Functions */ +rom_gpio_set_output_level = 0x40000670; +rom_gpio_get_input_level = 0x40000674; +rom_gpio_matrix_in = 0x40000678; +rom_gpio_matrix_out = 0x4000067c; +rom_gpio_bypass_matrix_in = 0x40000680; +rom_gpio_output_disable = 0x40000684; +rom_gpio_output_enable = 0x40000688; +rom_gpio_pad_input_disable = 0x4000068c; +rom_gpio_pad_input_enable = 0x40000690; +rom_gpio_pad_pulldown = 0x40000694; +rom_gpio_pad_pullup = 0x40000698; +rom_gpio_pad_select_gpio = 0x4000069c; +rom_gpio_pad_set_drv = 0x400006a0; +rom_gpio_pad_unhold = 0x400006a4; +rom_gpio_pad_hold = 0x400006a8; + + +/*************************************** + Group interrupts + ***************************************/ + +/* Functions */ +esprv_intc_int_set_priority = 0x400006ac; +esprv_intc_int_set_threshold = 0x400006b0; +esprv_intc_int_enable = 0x400006b4; +esprv_intc_int_disable = 0x400006b8; +esprv_intc_int_set_type = 0x400006bc; +PROVIDE( intr_handler_set = 0x400006c0 ); +intr_matrix_set = 0x400006c4; +ets_intr_register_ctx = 0x400006c8; +ets_intr_lock = 0x400006cc; +ets_intr_unlock = 0x400006d0; +ets_isr_attach = 0x400006d4; +ets_isr_mask = 0x400006d8; +ets_isr_unmask = 0x400006dc; + + +/*************************************** + Group crc + ***************************************/ + +/* Functions */ +crc32_le = 0x400006e0; +crc16_le = 0x400006e4; +crc8_le = 0x400006e8; +crc32_be = 0x400006ec; +crc16_be = 0x400006f0; +crc8_be = 0x400006f4; +esp_crc8 = 0x400006f8; +/* Data (.data, .bss, .rodata) */ +crc32_le_table_ptr = 0x4001fff8; +crc16_le_table_ptr = 0x4001fff4; +crc8_le_table_ptr = 0x4001fff0; +crc32_be_table_ptr = 0x4001ffec; +crc16_be_table_ptr = 0x4001ffe8; +crc8_be_table_ptr = 0x4001ffe4; + + +/*************************************** + Group md5 + ***************************************/ + +/* Functions */ +md5_vector = 0x400006fc; +MD5Init = 0x40000700; +MD5Update = 0x40000704; +MD5Final = 0x40000708; + + +/*************************************** + Group hwcrypto + ***************************************/ + +/* Functions */ +ets_sha_enable = 0x4000070c; +ets_sha_disable = 0x40000710; +ets_sha_get_state = 0x40000714; +ets_sha_init = 0x40000718; +ets_sha_process = 0x4000071c; +ets_sha_starts = 0x40000720; +ets_sha_update = 0x40000724; +ets_sha_finish = 0x40000728; +ets_sha_clone = 0x4000072c; +ets_hmac_enable = 0x40000730; +ets_hmac_disable = 0x40000734; +ets_hmac_calculate_message = 0x40000738; +ets_hmac_calculate_downstream = 0x4000073c; +ets_hmac_invalidate_downstream = 0x40000740; +ets_aes_enable = 0x40000744; +ets_aes_disable = 0x40000748; +ets_aes_setkey = 0x4000074c; +ets_aes_block = 0x40000750; +ets_aes_setkey_dec = 0x40000754; +ets_aes_setkey_enc = 0x40000758; + + +/*************************************** + Group efuse + ***************************************/ + +/* Functions */ +ets_efuse_read = 0x4000075c; +ets_efuse_program = 0x40000760; +ets_efuse_clear_program_registers = 0x40000764; +ets_efuse_write_key = 0x40000768; +ets_efuse_get_read_register_address = 0x4000076c; +ets_efuse_get_key_purpose = 0x40000770; +ets_efuse_key_block_unused = 0x40000774; +ets_efuse_find_unused_key_block = 0x40000778; +ets_efuse_rs_calculate = 0x4000077c; +ets_efuse_count_unused_key_blocks = 0x40000780; +ets_efuse_secure_boot_enabled = 0x40000784; +ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000788; +ets_efuse_cache_encryption_enabled = 0x4000078c; +ets_efuse_download_modes_disabled = 0x40000790; +ets_efuse_find_purpose = 0x40000794; +ets_efuse_force_send_resume = 0x40000798; +ets_efuse_get_flash_delay_us = 0x4000079c; +ets_efuse_get_uart_print_control = 0x400007a0; +ets_efuse_direct_boot_mode_disabled = 0x400007a4; +ets_efuse_security_download_modes_enabled = 0x400007a8; +ets_efuse_jtag_disabled = 0x400007ac; +ets_efuse_usb_print_is_disabled = 0x400007b0; +ets_efuse_usb_download_mode_disabled = 0x400007b4; +ets_efuse_usb_device_disabled = 0x400007b8; +ets_jtag_enable_temporarily = 0x400007bc; + + +/*************************************** + Group key_mgr + ***************************************/ + +/* Functions */ +esp_rom_check_recover_key = 0x400007c0; +esp_rom_km_huk_conf = 0x400007c4; +esp_rom_km_huk_risk = 0x400007c8; +esp_rom_recover_key = 0x400007cc; + + +/*************************************** + Group secureboot + ***************************************/ + +/* Functions */ +ets_ecdsa_verify = 0x400007d0; +ets_secure_boot_verify_bootloader_with_keys = 0x400007d4; +ets_secure_boot_verify_signature = 0x400007d8; +ets_secure_boot_read_key_digests = 0x400007dc; +ets_secure_boot_revoke_public_key_digest = 0x400007e0; + + +/*************************************** + Group usb_device_uart + ***************************************/ + +/* Functions */ +usb_serial_device_rx_one_char = 0x40000910; +usb_serial_device_rx_one_char_block = 0x40000914; +usb_serial_device_tx_flush = 0x40000918; +usb_serial_device_tx_one_char = 0x4000091c; diff --git a/components/esp_rom/esp32h4/ld/esp32h4.rom.ld b/components/esp_rom/esp32h4/ld/esp32h4.rom.ld index 44b02fa5e3d..6bfc66660b9 100644 --- a/components/esp_rom/esp32h4/ld/esp32h4.rom.ld +++ b/components/esp_rom/esp32h4/ld/esp32h4.rom.ld @@ -6,9 +6,9 @@ /* ROM function interface esp32h4.rom.ld for esp32h4 * * - * Generated from ../../rom/target/esp32h4/interface-esp32h4.yml md5sum bb9ee317148d3c5b10610936a3675a65 + * Generated from ../../rom/target/esp32h4/interface-esp32h4.yml md5sum 5996da6c5ce799e55c4cf85b5d2ae712 * - * Compatible with ROM where ECO version equal or greater to 0. + * Compatible with ROM where ECO version equal or greater to 2. * * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. */ @@ -397,7 +397,7 @@ ets_secure_boot_revoke_public_key_digest = 0x400007e0; ***************************************/ /* Functions */ -usb_serial_device_rx_one_char = 0x40000910; -usb_serial_device_rx_one_char_block = 0x40000914; -usb_serial_device_tx_flush = 0x40000918; -usb_serial_device_tx_one_char = 0x4000091c; +usb_serial_device_rx_one_char = 0x400007e4; +usb_serial_device_rx_one_char_block = 0x400007e8; +usb_serial_device_tx_flush = 0x400007ec; +usb_serial_device_tx_one_char = 0x400007f0; diff --git a/components/esp_rom/esp32h4/ld/esp32h4.rom.libgcc.ld b/components/esp_rom/esp32h4/ld/esp32h4.rom.libgcc.ld deleted file mode 100644 index 23a382adc8b..00000000000 --- a/components/esp_rom/esp32h4/ld/esp32h4.rom.libgcc.ld +++ /dev/null @@ -1,95 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -/* ROM function interface esp32h4.rom.libgcc.ld for esp32h4 - * - * - * Generated from ../../rom/target/esp32h4/interface-esp32h4.yml md5sum bb9ee317148d3c5b10610936a3675a65 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group libgccdf - ***************************************/ - -/* Functions */ -__absvdi2 = 0x400007e4; -__absvsi2 = 0x400007e8; -__adddf3 = 0x400007ec; -__addvdi3 = 0x400007f0; -__addvsi3 = 0x400007f4; -__ashldi3 = 0x400007f8; -__ashrdi3 = 0x400007fc; -__bswapdi2 = 0x40000800; -__bswapsi2 = 0x40000804; -__clear_cache = 0x40000808; -__clrsbdi2 = 0x4000080c; -__clrsbsi2 = 0x40000810; -__clzdi2 = 0x40000814; -__clzsi2 = 0x40000818; -__cmpdi2 = 0x4000081c; -__ctzdi2 = 0x40000820; -__ctzsi2 = 0x40000824; -__divdc3 = 0x40000828; -__divdf3 = 0x4000082c; -__divdi3 = 0x40000830; -__divsc3 = 0x40000834; -__divsi3 = 0x40000838; -__eqdf2 = 0x4000083c; -__extendsfdf2 = 0x40000840; -__ffsdi2 = 0x40000844; -__ffssi2 = 0x40000848; -__fixdfdi = 0x4000084c; -__fixdfsi = 0x40000850; -__fixsfdi = 0x40000854; -__fixunsdfsi = 0x40000858; -__fixunssfdi = 0x4000085c; -__fixunssfsi = 0x40000860; -__floatdidf = 0x40000864; -__floatdisf = 0x40000868; -__floatsidf = 0x4000086c; -__floatundidf = 0x40000870; -__floatundisf = 0x40000874; -__floatunsidf = 0x40000878; -__gcc_bcmp = 0x4000087c; -__gedf2 = 0x40000880; -__gtdf2 = 0x40000884; -__ledf2 = 0x40000888; -__lshrdi3 = 0x4000088c; -__ltdf2 = 0x40000890; -__moddi3 = 0x40000894; -__modsi3 = 0x40000898; -__muldc3 = 0x4000089c; -__muldf3 = 0x400008a0; -__muldi3 = 0x400008a4; -__mulsc3 = 0x400008a8; -__mulsi3 = 0x400008ac; -__mulvdi3 = 0x400008b0; -__mulvsi3 = 0x400008b4; -__nedf2 = 0x400008b8; -__negdf2 = 0x400008bc; -__negdi2 = 0x400008c0; -__negvdi2 = 0x400008c4; -__negvsi2 = 0x400008c8; -__paritysi2 = 0x400008cc; -__popcountdi2 = 0x400008d0; -__popcountsi2 = 0x400008d4; -__powidf2 = 0x400008d8; -__subdf3 = 0x400008dc; -__subvdi3 = 0x400008e0; -__subvsi3 = 0x400008e4; -__ucmpdi2 = 0x400008e8; -__udivdi3 = 0x400008ec; -__udivmoddi4 = 0x400008f0; -__udivsi3 = 0x400008f4; -__udiv_w_sdiv = 0x400008f8; -__umoddi3 = 0x400008fc; -__umodsi3 = 0x40000900; -__unorddf2 = 0x40000904; -__extenddftf2 = 0x40000908; -__trunctfdf2 = 0x4000090c; diff --git a/components/esp_rom/esp32p4/Kconfig.soc_caps.in b/components/esp_rom/esp32p4/Kconfig.soc_caps.in index 989040149be..abbfd5d68b4 100644 --- a/components/esp_rom/esp32p4/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32p4/Kconfig.soc_caps.in @@ -71,6 +71,10 @@ config ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG bool default y +config ESP_ROM_HAS_LIBGCC + bool + default y + config ESP_ROM_HAS_VERSION bool default y diff --git a/components/esp_rom/esp32p4/esp_rom_caps.h b/components/esp_rom/esp32p4/esp_rom_caps.h index febf3eac42e..a40b806f128 100644 --- a/components/esp_rom/esp32p4/esp_rom_caps.h +++ b/components/esp_rom/esp32p4/esp_rom_caps.h @@ -23,6 +23,7 @@ #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions #define ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG (1) // ROM has the printf float bug with newlib nano version +#define ESP_ROM_HAS_LIBGCC (1) // ROM has libgcc functions included #define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information #define ESP_ROM_CLIC_INT_TYPE_PATCH (1) // ROM api esprv_intc_int_set_type configuring edge type interrupt (old revisions) #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) diff --git a/components/esp_rom/esp32s2/Kconfig.soc_caps.in b/components/esp_rom/esp32s2/Kconfig.soc_caps.in index 16eeaf0e20a..5b645af86cb 100644 --- a/components/esp_rom/esp32s2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s2/Kconfig.soc_caps.in @@ -31,6 +31,10 @@ config ESP_ROM_HAS_NEWLIB_32BIT_TIME bool default y +config ESP_ROM_HAS_LIBGCC + bool + default y + config ESP_ROM_USB_OTG_NUM int default 3 diff --git a/components/esp_rom/esp32s2/esp_rom_caps.h b/components/esp_rom/esp32s2/esp_rom_caps.h index 298c63ab543..8f9268b28e2 100644 --- a/components/esp_rom/esp32s2/esp_rom_caps.h +++ b/components/esp_rom/esp32s2/esp_rom_caps.h @@ -14,6 +14,7 @@ #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions #define ESP_ROM_HAS_NEWLIB_32BIT_TIME (1) // ROM was compiled with 32 bit time_t +#define ESP_ROM_HAS_LIBGCC (1) // ROM has libgcc functions included #define ESP_ROM_USB_OTG_NUM (3) // The serial port ID (UART, USB, ...) of USB_OTG CDC in the ROM. #define ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG (1) // ROM api Cache_Count_Flash_Pages will return unexpected value #define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions diff --git a/components/esp_rom/esp32s3/Kconfig.soc_caps.in b/components/esp_rom/esp32s3/Kconfig.soc_caps.in index e7b3599dada..055704ea34b 100644 --- a/components/esp_rom/esp32s3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s3/Kconfig.soc_caps.in @@ -83,6 +83,10 @@ config ESP_ROM_HAS_NEWLIB_32BIT_TIME bool default y +config ESP_ROM_HAS_LIBGCC + bool + default y + config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE bool default y diff --git a/components/esp_rom/esp32s3/esp_rom_caps.h b/components/esp_rom/esp32s3/esp_rom_caps.h index d8752460318..ccf9eb015cc 100644 --- a/components/esp_rom/esp32s3/esp_rom_caps.h +++ b/components/esp_rom/esp32s3/esp_rom_caps.h @@ -26,6 +26,7 @@ #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions #define ESP_ROM_HAS_NEWLIB_32BIT_TIME (1) // ROM was compiled with 32 bit time_t +#define ESP_ROM_HAS_LIBGCC (1) // ROM has libgcc functions included #define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init #define ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG (1) // ROM api Cache_Count_Flash_Pages will return unexpected value diff --git a/components/esp_rom/esp32s31/Kconfig.soc_caps.in b/components/esp_rom/esp32s31/Kconfig.soc_caps.in index bf9685344c0..01d4d65544e 100644 --- a/components/esp_rom/esp32s31/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s31/Kconfig.soc_caps.in @@ -79,6 +79,10 @@ config ESP_ROM_HAS_NEWLIB_NANO_FORMAT bool default y +config ESP_ROM_HAS_LIBGCC + bool + default y + config ESP_ROM_HAS_VERSION bool default y diff --git a/components/esp_rom/esp32s31/esp_rom_caps.h b/components/esp_rom/esp32s31/esp_rom_caps.h index 99a0312f9fc..5f912f24886 100644 --- a/components/esp_rom/esp32s31/esp_rom_caps.h +++ b/components/esp_rom/esp32s31/esp_rom_caps.h @@ -26,6 +26,7 @@ #define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library #define ESP_ROM_HAS_NEWLIB (1) // ROM has newlib (at least parts of it) functions included #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions +#define ESP_ROM_HAS_LIBGCC (1) // ROM has libgcc functions included #define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) #define ESP_ROM_PRINTS_LOCKUP_STATUS (1) // ROM bootloader already prints CPU lockup diagnostic status