feat(esp32h21): ci enable public header check (stage7)

components/hal/include/hal/clk_tree_hal.h

@@ -8,9 +8,12 @@
 
 #include <stdint.h>
 #include "soc/clk_tree_defs.h"
-#include "soc/clkout_channel.h"
 #include "soc/soc_caps.h"
 
+#if SOC_GPIO_CLOCKOUT_CHANNEL_NUM > 0 //TODO: [ESP32H21] IDF-11582
+#include "soc/clkout_channel.h"
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -61,6 +64,7 @@ uint32_t clk_hal_xtal_get_freq_mhz(void);
 uint32_t clk_hal_apll_get_freq_hz(void);
 #endif //SOC_CLK_APLL_SUPPORTED
 
+#if SOC_GPIO_CLOCKOUT_CHANNEL_NUM > 0 //TODO: [ESP32H21] IDF-11582
 /**
  * @brief Set up clock output channel
  * @param clk_sig    The clock signal source to be mapped to GPIOs
@@ -82,6 +86,7 @@ void clk_hal_clock_output_set_divider(clock_out_channel_t channel_id, uint32_t d
  * @param channel_id The clock output channel to teardown
  */
 void clk_hal_clock_output_teardown(clock_out_channel_t channel_id);
+#endif
 
 #ifdef __cplusplus
 }

components/hal/include/hal/ledc_types.h

@@ -35,6 +35,7 @@ typedef enum {
     LEDC_DUTY_DIR_MAX,
 } ledc_duty_direction_t;
 
+#if SOC_LEDC_SUPPORTED
 /**
  * @brief LEDC global clock sources
  */
@@ -81,6 +82,10 @@ typedef enum  {
     LEDC_SCLK = LEDC_USE_PLL_DIV_CLK, /*!< Selecting this value for LEDC_TICK_SEL_TIMER let the hardware take its source clock from LEDC_CLK_SEL */
 #endif
 } ledc_clk_src_t;
+#else
+typedef int ledc_clk_cfg_t;
+typedef int ledc_clk_src_t;
+#endif
 
 typedef enum {
     LEDC_TIMER_0 = 0, /*!< LEDC timer 0 */

components/hal/include/hal/sha_types.h

@@ -27,6 +27,8 @@
 #include "esp32c5/rom/sha.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/sha.h"
+#elif CONFIG_IDF_TARGET_ESP32H21
+#include "esp32h21/rom/sha.h"
 #elif CONFIG_IDF_TARGET_ESP32P4
 #include "esp32p4/rom/sha.h"
 #endif