feat(esp_riscv_trace): add ESP32-S31 support

ESP32-S31 uses the same trace encoder IP as ESP32-P4. Of the E-Trace v2.0
parameters the two targets report, only privilege_width_p differs (1 on P4,
2 on S31), and it affects both the sync packet layout and the filter's
privilege selector.

- Add the SOC_RISCV_TRACE_* caps for ESP32-S31 along with the esp32s31 LL, and
  declare TRACE0/TRACE1 in the target's trace_struct.h.
- Carry privilege_width_p as SOC_RISCV_TRACE_PRIV_WIDTH so the sync packet
  decoder can locate the address field, which starts one bit later on targets
  that implement supervisor mode.
- Use the RISC-V architectural privilege encoding (0 user, 1 supervisor,
  3 machine) in the public filter enum so the values do not change per target,
  and let each LL narrow them to its own register field.
- Add riscv_trace_ll_priv_is_supported() per target, so a privilege level the
  selector cannot represent is rejected with ESP_ERR_NOT_SUPPORTED rather than
  being silently narrowed to a different level. It lives next to the narrowing
  code so the two cannot drift apart.
- Fix trace buffer allocation on targets whose internal RAM is not reached
  through a cache. esp_cache_get_alignment() reports 0 there, which underflowed
  the size check and failed every allocation. Align base and size to the larger
  of the reported cache line and the encoder's 4-byte write granularity.

components/esp_hal_debug_assist/include/hal/riscv_trace_hal.h

@@ -53,7 +53,7 @@ typedef struct {
     bool match_privilege;          /*!< Gate matching on the privilege level (match_privilege) */
     bool match_ecause;             /*!< Match from an exception cause (match_ecause) */
     bool match_interrupt;          /*!< Match from an interrupt trap (match_interrupt) */
-    bool privilege_machine;        /*!< match_choice_privilege: true = machine, false = user */
+    uint32_t privilege;            /*!< match_choice_privilege (riscv_trace_priv_t) */
     bool interrupt_itype2;         /*!< match_value_interrupt: true = itype 2, false = itype 1 */
     uint32_t ecause;               /*!< match_choice_ecause (6-bit exception cause code) */
     riscv_trace_hal_comparator_t primary;   /*!< Primary comparator */

components/esp_hal_debug_assist/include/hal/riscv_trace_types.h

@@ -21,6 +21,19 @@ typedef enum {
     RISCV_TRACE_INTR_MEM_FULL      = BIT(1), /*!< Trace memory region became full. */
 } riscv_trace_intr_t;
 
+/**
+ * @brief Privilege level selected by the filter privilege qualifier.
+ *
+ * Values are the RISC-V architectural privilege encoding. Targets whose
+ * match_choice_privilege field is narrower implement only a subset, and their
+ * LL narrows the value when writing the register.
+ */
+typedef enum {
+    RISCV_TRACE_PRIV_USER       = 0, /*!< User mode */
+    RISCV_TRACE_PRIV_SUPERVISOR = 1, /*!< Supervisor mode */
+    RISCV_TRACE_PRIV_MACHINE    = 3, /*!< Machine mode */
+} riscv_trace_priv_t;
+
 /**
  * @brief Trace encoder work-status field.
  *