feat(esp_riscv_trace): add ESP32-S31 support

ESP32-S31 uses the same trace encoder IP as ESP32-P4. Of the E-Trace v2.0
parameters the two targets report, only privilege_width_p differs (1 on P4,
2 on S31), and it affects both the sync packet layout and the filter's
privilege selector.

- Add the SOC_RISCV_TRACE_* caps for ESP32-S31 along with the esp32s31 LL, and
  declare TRACE0/TRACE1 in the target's trace_struct.h.
- Carry privilege_width_p as SOC_RISCV_TRACE_PRIV_WIDTH so the sync packet
  decoder can locate the address field, which starts one bit later on targets
  that implement supervisor mode.
- Use the RISC-V architectural privilege encoding (0 user, 1 supervisor,
  3 machine) in the public filter enum so the values do not change per target,
  and let each LL narrow them to its own register field.
- Add riscv_trace_ll_priv_is_supported() per target, so a privilege level the
  selector cannot represent is rejected with ESP_ERR_NOT_SUPPORTED rather than
  being silently narrowed to a different level. It lives next to the narrowing
  code so the two cannot drift apart.
- Fix trace buffer allocation on targets whose internal RAM is not reached
  through a cache. esp_cache_get_alignment() reports 0 there, which underflowed
  the size check and failed every allocation. Align base and size to the larger
  of the reported cache line and the encoder's 4-byte write granularity.

components/esp_hal_debug_assist/esp32p4/include/hal/riscv_trace_ll.h

@@ -13,6 +13,7 @@
 #include "soc/trace_struct.h"
 #include "soc/hp_sys_clkrst_struct.h"
 #include "hal/assert.h"
+#include "hal/riscv_trace_types.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -217,10 +218,15 @@ static inline void riscv_trace_ll_set_filter_control(trace_dev_t *hw, bool match
     hw->filter_control.match_interrupt = match_interrupt;
 }
 
-static inline void riscv_trace_ll_set_filter_match_control(trace_dev_t *hw, bool priv_choice,
+static inline bool riscv_trace_ll_priv_is_supported(uint32_t priv)
+{
+    return priv == RISCV_TRACE_PRIV_USER || priv == RISCV_TRACE_PRIV_MACHINE;
+}
+
+static inline void riscv_trace_ll_set_filter_match_control(trace_dev_t *hw, uint32_t priv_choice,
                                                            bool intr_value, uint32_t ecause_choice)
 {
-    hw->filter_match_control.match_choice_privilege = priv_choice;
+    hw->filter_match_control.match_choice_privilege = (priv_choice == RISCV_TRACE_PRIV_MACHINE);
     hw->filter_match_control.match_value_interrupt = intr_value;
     hw->filter_match_control.match_choice_ecause = ecause_choice;
 }