mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-01 18:50:34 +03:00
feat(esp_riscv_trace): add ESP32-S31 support
ESP32-S31 uses the same trace encoder IP as ESP32-P4. Of the E-Trace v2.0 parameters the two targets report, only privilege_width_p differs (1 on P4, 2 on S31), and it affects both the sync packet layout and the filter's privilege selector. - Add the SOC_RISCV_TRACE_* caps for ESP32-S31 along with the esp32s31 LL, and declare TRACE0/TRACE1 in the target's trace_struct.h. - Carry privilege_width_p as SOC_RISCV_TRACE_PRIV_WIDTH so the sync packet decoder can locate the address field, which starts one bit later on targets that implement supervisor mode. - Use the RISC-V architectural privilege encoding (0 user, 1 supervisor, 3 machine) in the public filter enum so the values do not change per target, and let each LL narrow them to its own register field. - Add riscv_trace_ll_priv_is_supported() per target, so a privilege level the selector cannot represent is rejected with ESP_ERR_NOT_SUPPORTED rather than being silently narrowed to a different level. It lives next to the narrowing code so the two cannot drift apart. - Fix trace buffer allocation on targets whose internal RAM is not reached through a cache. esp_cache_get_alignment() reports 0 there, which underflowed the size check and failed every allocation. Align base and size to the larger of the reported cache line and the encoder's 4-byte write granularity.
This commit is contained in:
Erhan Kurubas
BOT
@@ -13,6 +13,7 @@
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#include "soc/trace_struct.h"
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#include "soc/hp_sys_clkrst_struct.h"
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#include "hal/assert.h"
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#include "hal/riscv_trace_types.h"
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#ifdef __cplusplus
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extern "C" {
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@@ -217,10 +218,15 @@ static inline void riscv_trace_ll_set_filter_control(trace_dev_t *hw, bool match
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hw->filter_control.match_interrupt = match_interrupt;
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}
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static inline void riscv_trace_ll_set_filter_match_control(trace_dev_t *hw, bool priv_choice,
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static inline bool riscv_trace_ll_priv_is_supported(uint32_t priv)
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{
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return priv == RISCV_TRACE_PRIV_USER || priv == RISCV_TRACE_PRIV_MACHINE;
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}
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static inline void riscv_trace_ll_set_filter_match_control(trace_dev_t *hw, uint32_t priv_choice,
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bool intr_value, uint32_t ecause_choice)
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{
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hw->filter_match_control.match_choice_privilege = priv_choice;
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hw->filter_match_control.match_choice_privilege = (priv_choice == RISCV_TRACE_PRIV_MACHINE);
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hw->filter_match_control.match_value_interrupt = intr_value;
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hw->filter_match_control.match_choice_ecause = ecause_choice;
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}
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@@ -0,0 +1,265 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "soc/trace_reg.h"
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#include "soc/trace_struct.h"
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#include "soc/hp_sys_clkrst_struct.h"
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#include "hal/assert.h"
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#include "hal/riscv_trace_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @brief Return the register block for the given core. */
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static inline trace_dev_t *riscv_trace_ll_get_hw(int core)
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{
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HAL_ASSERT(core == 0 || core == 1);
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return core == 0 ? &TRACE0 : &TRACE1;
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}
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/*---------------------------------------------------------------------------
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* Clock and reset
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*--------------------------------------------------------------------------*/
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static inline void _riscv_trace_ll_enable_bus_clock(bool enable)
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{
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HP_SYS_CLKRST.trace_ctrl0.reg_trace_cpu_clk_en = enable;
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HP_SYS_CLKRST.trace_ctrl0.reg_trace_sys_clk_en = enable;
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}
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#define riscv_trace_ll_enable_bus_clock(...) do { \
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(void)__DECLARE_RCC_ATOMIC_ENV; \
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_riscv_trace_ll_enable_bus_clock(__VA_ARGS__); \
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} while (0)
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static inline void _riscv_trace_ll_reset_register(int core)
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{
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if (core == 0) {
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HP_SYS_CLKRST.trace_ctrl0.reg_trace0_rst_en = 1;
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HP_SYS_CLKRST.trace_ctrl0.reg_trace0_rst_en = 0;
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} else {
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HP_SYS_CLKRST.trace_ctrl0.reg_trace1_rst_en = 1;
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HP_SYS_CLKRST.trace_ctrl0.reg_trace1_rst_en = 0;
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}
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}
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#define riscv_trace_ll_reset_register(...) do { \
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(void)__DECLARE_RCC_ATOMIC_ENV; \
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_riscv_trace_ll_reset_register(__VA_ARGS__); \
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} while (0)
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/** @brief Enable the per-module register clock gate. */
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static inline void riscv_trace_ll_enable_module_clock(trace_dev_t *hw, bool enable)
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{
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hw->clock_gate.clk_en = enable;
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}
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/*---------------------------------------------------------------------------
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* Memory configuration
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*--------------------------------------------------------------------------*/
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static inline void riscv_trace_ll_set_mem_start_addr(trace_dev_t *hw, uint32_t addr)
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{
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hw->mem_start_addr.mem_start_addr = addr;
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}
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static inline void riscv_trace_ll_set_mem_end_addr(trace_dev_t *hw, uint32_t addr)
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{
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hw->mem_end_addr.mem_end_addr = addr;
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}
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static inline uint32_t riscv_trace_ll_get_mem_current_addr(trace_dev_t *hw)
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{
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return hw->mem_current_addr.mem_current_addr;
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}
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/** @brief Reload the current address from the start address. */
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static inline void riscv_trace_ll_update_mem_current_addr(trace_dev_t *hw)
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{
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hw->mem_addr_update.mem_current_addr_update = 1;
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}
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/*---------------------------------------------------------------------------
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* Status
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*--------------------------------------------------------------------------*/
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static inline uint32_t riscv_trace_ll_get_fifo_status(trace_dev_t *hw)
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{
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return hw->fifo_status.val;
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}
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/*---------------------------------------------------------------------------
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* Trigger, loop mode and restart
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*--------------------------------------------------------------------------*/
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static inline void riscv_trace_ll_trigger_on(trace_dev_t *hw)
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{
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hw->trigger.trigger_on = 1;
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}
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static inline void riscv_trace_ll_trigger_off(trace_dev_t *hw)
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{
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hw->trigger.trigger_off = 1;
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}
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static inline void riscv_trace_ll_set_mem_loop(trace_dev_t *hw, bool loop)
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{
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hw->trigger.mem_loop = loop;
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}
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static inline void riscv_trace_ll_set_restart_ena(trace_dev_t *hw, bool enable)
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{
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hw->trigger.restart_ena = enable;
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}
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/*---------------------------------------------------------------------------
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* Encoder options (config register)
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*--------------------------------------------------------------------------*/
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static inline void riscv_trace_ll_set_full_address(trace_dev_t *hw, bool full)
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{
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hw->config.full_address = full;
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}
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static inline void riscv_trace_ll_set_stall_ena(trace_dev_t *hw, bool enable)
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{
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hw->config.stall_ena = enable;
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}
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static inline void riscv_trace_ll_set_halt_ena(trace_dev_t *hw, bool enable)
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{
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hw->config.halt_ena = enable;
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}
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static inline void riscv_trace_ll_set_reset_ena(trace_dev_t *hw, bool enable)
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{
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hw->config.reset_ena = enable;
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}
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static inline void riscv_trace_ll_set_dm_trigger_ena(trace_dev_t *hw, bool enable)
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{
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hw->config.dm_trigger_ena = enable;
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}
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/*---------------------------------------------------------------------------
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* Resynchronization
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*--------------------------------------------------------------------------*/
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static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode)
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{
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hw->resync_prolonged.resync_mode = mode;
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}
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static inline void riscv_trace_ll_set_resync_threshold(trace_dev_t *hw, uint32_t threshold)
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{
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hw->resync_prolonged.resync_prolonged = threshold;
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}
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/*---------------------------------------------------------------------------
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* AHB configuration
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*--------------------------------------------------------------------------*/
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static inline void riscv_trace_ll_set_ahb_burst(trace_dev_t *hw, uint32_t hburst)
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{
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hw->ahb_config.hburst = hburst;
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}
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static inline void riscv_trace_ll_set_ahb_max_incr(trace_dev_t *hw, uint32_t max_incr)
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{
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hw->ahb_config.max_incr = max_incr;
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}
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/*---------------------------------------------------------------------------
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* Interrupts
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*--------------------------------------------------------------------------*/
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static inline void riscv_trace_ll_set_intr_ena(trace_dev_t *hw, uint32_t mask)
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{
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hw->intr_ena.val = mask;
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}
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static inline uint32_t riscv_trace_ll_get_intr_raw(trace_dev_t *hw)
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{
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return hw->intr_raw.val;
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}
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static inline void riscv_trace_ll_clear_intr(trace_dev_t *hw, uint32_t mask)
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{
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hw->intr_clr.val = mask;
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}
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/*---------------------------------------------------------------------------
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* Filter unit
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*--------------------------------------------------------------------------*/
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static inline void riscv_trace_ll_set_filter_en(trace_dev_t *hw, bool enable)
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{
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hw->filter_control.filter_en = enable;
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}
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static inline void riscv_trace_ll_set_filter_control(trace_dev_t *hw, bool match_comp,
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bool match_privilege, bool match_ecause,
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bool match_interrupt)
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{
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hw->filter_control.match_comp = match_comp;
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hw->filter_control.match_privilege = match_privilege;
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hw->filter_control.match_ecause = match_ecause;
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hw->filter_control.match_interrupt = match_interrupt;
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}
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static inline bool riscv_trace_ll_priv_is_supported(uint32_t priv)
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{
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return priv == RISCV_TRACE_PRIV_USER || priv == RISCV_TRACE_PRIV_SUPERVISOR ||
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priv == RISCV_TRACE_PRIV_MACHINE;
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}
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static inline void riscv_trace_ll_set_filter_match_control(trace_dev_t *hw, uint32_t priv_choice,
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bool intr_value, uint32_t ecause_choice)
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{
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// This target implements the full architectural encoding, so no narrowing is needed.
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hw->filter_match_control.match_choice_privilege = priv_choice;
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hw->filter_match_control.match_value_interrupt = intr_value;
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hw->filter_match_control.match_choice_ecause = ecause_choice;
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}
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static inline void riscv_trace_ll_set_p_comparator(trace_dev_t *hw, uint32_t input,
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uint32_t function, bool notify)
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{
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hw->filter_comparator_control.p_input = input;
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hw->filter_comparator_control.p_function = function;
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hw->filter_comparator_control.p_notify = notify;
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}
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static inline void riscv_trace_ll_set_s_comparator(trace_dev_t *hw, uint32_t input,
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uint32_t function, bool notify)
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{
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hw->filter_comparator_control.s_input = input;
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hw->filter_comparator_control.s_function = function;
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hw->filter_comparator_control.s_notify = notify;
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}
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static inline void riscv_trace_ll_set_match_mode(trace_dev_t *hw, uint32_t mode)
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{
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hw->filter_comparator_control.match_mode = mode;
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}
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static inline void riscv_trace_ll_set_p_match_value(trace_dev_t *hw, uint32_t value)
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{
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hw->filter_p_comparator_match.p_match = value;
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}
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static inline void riscv_trace_ll_set_s_match_value(trace_dev_t *hw, uint32_t value)
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{
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hw->filter_s_comparator_match.s_match = value;
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}
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#ifdef __cplusplus
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}
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#endif
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@@ -53,7 +53,7 @@ typedef struct {
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bool match_privilege; /*!< Gate matching on the privilege level (match_privilege) */
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bool match_ecause; /*!< Match from an exception cause (match_ecause) */
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bool match_interrupt; /*!< Match from an interrupt trap (match_interrupt) */
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bool privilege_machine; /*!< match_choice_privilege: true = machine, false = user */
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uint32_t privilege; /*!< match_choice_privilege (riscv_trace_priv_t) */
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bool interrupt_itype2; /*!< match_value_interrupt: true = itype 2, false = itype 1 */
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uint32_t ecause; /*!< match_choice_ecause (6-bit exception cause code) */
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riscv_trace_hal_comparator_t primary; /*!< Primary comparator */
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@@ -21,6 +21,19 @@ typedef enum {
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RISCV_TRACE_INTR_MEM_FULL = BIT(1), /*!< Trace memory region became full. */
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} riscv_trace_intr_t;
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/**
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* @brief Privilege level selected by the filter privilege qualifier.
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*
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* Values are the RISC-V architectural privilege encoding. Targets whose
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* match_choice_privilege field is narrower implement only a subset, and their
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* LL narrows the value when writing the register.
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*/
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typedef enum {
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RISCV_TRACE_PRIV_USER = 0, /*!< User mode */
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RISCV_TRACE_PRIV_SUPERVISOR = 1, /*!< Supervisor mode */
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RISCV_TRACE_PRIV_MACHINE = 3, /*!< Machine mode */
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} riscv_trace_priv_t;
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/**
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* @brief Trace encoder work-status field.
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*
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@@ -163,7 +163,7 @@ void riscv_trace_hal_set_filter(riscv_trace_hal_context_t *ctx, const riscv_trac
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riscv_trace_ll_set_filter_control(ctx->dev, config->match_comparators, config->match_privilege,
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config->match_ecause, config->match_interrupt);
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riscv_trace_ll_set_filter_match_control(ctx->dev, config->privilege_machine,
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riscv_trace_ll_set_filter_match_control(ctx->dev, config->privilege,
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config->interrupt_itype2, config->ecause);
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riscv_trace_ll_set_p_comparator(ctx->dev, config->primary.input, config->primary.function,
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