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Merge branch 'fix/hmac-ds-reset-corrupts-concurrent-mpi_v5.5' into 'release/v5.5'
fix(esp_security): don't reset DS peripheral in esp_hmac_calculate (v5.5) See merge request espressif/esp-idf!52204
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@@ -70,13 +70,11 @@ esp_err_t esp_hmac_calculate(hmac_key_id_t key_id,
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esp_crypto_hmac_lock_acquire();
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esp_crypto_hmac_lock_acquire();
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// We also enable SHA and DS here. SHA is used by HMAC, DS will otherwise hold SHA in reset state.
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// SHA is used by HMAC, so enable it here.
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esp_crypto_hmac_enable_periph_clk(true);
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esp_crypto_hmac_enable_periph_clk(true);
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esp_crypto_sha_enable_periph_clk(true);
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esp_crypto_sha_enable_periph_clk(true);
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esp_crypto_ds_enable_periph_clk(true);
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#if SOC_KEY_MANAGER_HMAC_KEY_DEPLOY
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#if SOC_KEY_MANAGER_HMAC_KEY_DEPLOY
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/* Key Manager holds the key usage selector register(efuse vs own key).
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/* Key Manager holds the key usage selector register(efuse vs own key).
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Thus, we need to enable the Key Manager peripheral clock to ensure
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Thus, we need to enable the Key Manager peripheral clock to ensure
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@@ -149,8 +147,6 @@ esp_err_t esp_hmac_calculate(hmac_key_id_t key_id,
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esp_crypto_key_mgr_enable_periph_clk(false);
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esp_crypto_key_mgr_enable_periph_clk(false);
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#endif /* SOC_KEY_MANAGER_HMAC_KEY_DEPLOY */
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#endif /* SOC_KEY_MANAGER_HMAC_KEY_DEPLOY */
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esp_crypto_ds_enable_periph_clk(false);
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esp_crypto_sha_enable_periph_clk(false);
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esp_crypto_sha_enable_periph_clk(false);
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esp_crypto_hmac_enable_periph_clk(false);
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esp_crypto_hmac_enable_periph_clk(false);
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