From 3d8d8126621d935ff5921720a9240093591f651a Mon Sep 17 00:00:00 2001
From: wanckl <wanlei@espressif.com>
Date: Wed, 2 Sep 2026 14:41:26 +0800
Subject: [PATCH] feat(driver_gpio): add esp32h4 gpio hysterisys filter support

---
 .../esp32h4/include/hal/gpio_ll.h             | 28 +++++++++++++++++++
 .../esp32h4/include/soc/Kconfig.soc_caps.in   |  4 +++
 components/soc/esp32h4/include/soc/soc_caps.h |  1 +
 3 files changed, 33 insertions(+)

diff --git a/components/esp_hal_gpio/esp32h4/include/hal/gpio_ll.h b/components/esp_hal_gpio/esp32h4/include/hal/gpio_ll.h
index 71ee5f9ce4c..817b6a73f93 100644
--- a/components/esp_hal_gpio/esp32h4/include/hal/gpio_ll.h
+++ b/components/esp_hal_gpio/esp32h4/include/hal/gpio_ll.h
@@ -277,6 +277,34 @@ static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
     IO_MUX.gpio[gpio_num].filter_en = 0;
 }
 
+/**
+ * @brief Enable GPIO hysteresis
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number
+ */
+static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    // On ESP32H4, there is an efuse bit that controls the hysteresis enable or not for all IOs.
+    // We are not going to use the hardware control for H4.
+    // Therefore, we need to always switch to use software control first.
+    // i.e. Swt hys_sel to 1, so that hys_en determines whether hysteresis is enabled or not
+    IO_MUX.gpio[gpio_num].hys_sel = 1;
+    IO_MUX.gpio[gpio_num].hys_en = 1;
+}
+
+/**
+ * @brief Disable GPIO hysteresis
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number
+ */
+static inline void gpio_ll_pin_input_hysteresis_disable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    IO_MUX.gpio[gpio_num].hys_sel = 1;
+    IO_MUX.gpio[gpio_num].hys_en = 0;
+}
+
 /**
   * @brief Disable output mode on GPIO.
   *
diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
index d3699d96549..edfe0efd9f8 100644
--- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
@@ -495,6 +495,10 @@ config SOC_GPIO_FLEX_GLITCH_FILTER_NUM
     int
     default 8
 
+config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
+    bool
+    default y
+
 config SOC_GPIO_SUPPORT_ETM
     bool
     default y
diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h
index aa81befb9d4..3105bf4f510 100644
--- a/components/soc/esp32h4/include/soc/soc_caps.h
+++ b/components/soc/esp32h4/include/soc/soc_caps.h
@@ -206,6 +206,7 @@
 
 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
 #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM    8
+#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER    1
 
 // GPIO peripheral has the ETM extension
 #define SOC_GPIO_SUPPORT_ETM          1