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fix(drivers): sleep retention failure on esp32s31

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This commit is contained in:
morris
2026-05-13 11:12:08 +08:00
parent 4384743750
commit 3d452de7a3
14 changed files with 320 additions and 154 deletions
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components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+8
View File
@@ -759,6 +759,10 @@ config SOC_TIMER_SUPPORT_ETM
bool
default y
config SOC_TIMER_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_MWDT_SUPPORT_XTAL
bool
default y
@@ -1259,6 +1263,10 @@ config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
bool
default y
config SOC_MCPWM_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_JPEG_DECODE_SUPPORTED
bool
default y
components/soc/esp32s31/include/soc/soc.h
-1
View File
@@ -17,7 +17,6 @@
#define PRO_CPU_NUM (0)
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) // UART0 and UART1
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)
components/soc/esp32s31/include/soc/soc_caps.h
+2 -2
View File
@@ -306,7 +306,7 @@
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_SUPPORT_ETM (1)
// #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1) // TODO: [ESP32S31] IDF-14746
#define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
#define SOC_MWDT_SUPPORT_XTAL (1)
@@ -497,7 +497,7 @@
#define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
#define SOC_MCPWM_SUPPORT_EVENT_COMPARATOR (1) ///< Support event comparator (based on ETM)
#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
// #define SOC_MCPWM_SUPPORT_SLEEP_RETENTION (1) ///< Support back up registers before sleep
#define SOC_MCPWM_SUPPORT_SLEEP_RETENTION (1) ///< Support back up registers before sleep
/*--------------------------- JPEG --------------------------------*/
#define SOC_JPEG_DECODE_SUPPORTED (1)
components/soc/esp32s31/register/soc/mcpwm_reg.h
+94 -92
View File
@@ -1,22 +1,24 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#include "soc/soc.h"
#define REG_MCPWM_BASE(i) (DR_REG_MCPWM0_BASE + (i) * 0x1000)
#include "soc/reg_base.h"
#ifdef __cplusplus
extern "C" {
#endif
// MCPWM base address macro for multi-group support
#define REG_MCPWM_BASE(i) (DR_REG_MCPWM0_BASE + (i) * 0x1000)
/** MCPWM_TIMER0_CFG0_REG register
* PWM timer0 period and update method configuration register.
*/
#define MCPWM_TIMER0_CFG0_REG (DR_REG_MCPWM_BASE + 0x0)
#define MCPWM_TIMER0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0)
/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
* Configures the prescaler value of timer0, so that the period of PT0_clk = Period of
* PWM_clk * (PWM_TIMER0_PRESCALE + 1)
@@ -48,7 +50,7 @@ extern "C" {
/** MCPWM_TIMER0_CFG1_REG register
* PWM timer0 working mode and start/stop control register.
*/
#define MCPWM_TIMER0_CFG1_REG (DR_REG_MCPWM_BASE + 0x4)
#define MCPWM_TIMER0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x4)
/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0;
* Configures whether or not to start/stop PWM timer0.
* 0: If PWM timer0 starts, then stops at TEZ
@@ -77,7 +79,7 @@ extern "C" {
/** MCPWM_TIMER0_SYNC_REG register
* PWM timer0 sync function configuration register.
*/
#define MCPWM_TIMER0_SYNC_REG (DR_REG_MCPWM_BASE + 0x8)
#define MCPWM_TIMER0_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x8)
/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable timer0 reloading with phase on sync input event
* is enabled.
@@ -127,7 +129,7 @@ extern "C" {
/** MCPWM_TIMER0_STATUS_REG register
* PWM timer0 status register.
*/
#define MCPWM_TIMER0_STATUS_REG (DR_REG_MCPWM_BASE + 0xc)
#define MCPWM_TIMER0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xc)
/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0;
* Represents current PWM timer0 counter value.
*/
@@ -148,7 +150,7 @@ extern "C" {
/** MCPWM_TIMER1_CFG0_REG register
* PWM timer1 period and update method configuration register.
*/
#define MCPWM_TIMER1_CFG0_REG (DR_REG_MCPWM_BASE + 0x10)
#define MCPWM_TIMER1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x10)
/** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0;
* Configures the prescaler value of timer1, so that the period of PT0_clk = Period of
* PWM_clk * (PWM_TIMER1_PRESCALE + 1)
@@ -180,7 +182,7 @@ extern "C" {
/** MCPWM_TIMER1_CFG1_REG register
* PWM timer1 working mode and start/stop control register.
*/
#define MCPWM_TIMER1_CFG1_REG (DR_REG_MCPWM_BASE + 0x14)
#define MCPWM_TIMER1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x14)
/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0;
* Configures whether or not to start/stop PWM timer1.
* 0: If PWM timer1 starts, then stops at TEZ
@@ -209,7 +211,7 @@ extern "C" {
/** MCPWM_TIMER1_SYNC_REG register
* PWM timer1 sync function configuration register.
*/
#define MCPWM_TIMER1_SYNC_REG (DR_REG_MCPWM_BASE + 0x18)
#define MCPWM_TIMER1_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x18)
/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable timer1 reloading with phase on sync input event
* is enabled.
@@ -259,7 +261,7 @@ extern "C" {
/** MCPWM_TIMER1_STATUS_REG register
* PWM timer1 status register.
*/
#define MCPWM_TIMER1_STATUS_REG (DR_REG_MCPWM_BASE + 0x1c)
#define MCPWM_TIMER1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x1c)
/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0;
* Represents current PWM timer1 counter value.
*/
@@ -280,7 +282,7 @@ extern "C" {
/** MCPWM_TIMER2_CFG0_REG register
* PWM timer2 period and update method configuration register.
*/
#define MCPWM_TIMER2_CFG0_REG (DR_REG_MCPWM_BASE + 0x20)
#define MCPWM_TIMER2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x20)
/** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0;
* Configures the prescaler value of timer2, so that the period of PT0_clk = Period of
* PWM_clk * (PWM_TIMER2_PRESCALE + 1)
@@ -312,7 +314,7 @@ extern "C" {
/** MCPWM_TIMER2_CFG1_REG register
* PWM timer2 working mode and start/stop control register.
*/
#define MCPWM_TIMER2_CFG1_REG (DR_REG_MCPWM_BASE + 0x24)
#define MCPWM_TIMER2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x24)
/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0;
* Configures whether or not to start/stop PWM timer2.
* 0: If PWM timer2 starts, then stops at TEZ
@@ -341,7 +343,7 @@ extern "C" {
/** MCPWM_TIMER2_SYNC_REG register
* PWM timer2 sync function configuration register.
*/
#define MCPWM_TIMER2_SYNC_REG (DR_REG_MCPWM_BASE + 0x28)
#define MCPWM_TIMER2_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x28)
/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable timer2 reloading with phase on sync input event
* is enabled.
@@ -391,7 +393,7 @@ extern "C" {
/** MCPWM_TIMER2_STATUS_REG register
* PWM timer2 status register.
*/
#define MCPWM_TIMER2_STATUS_REG (DR_REG_MCPWM_BASE + 0x2c)
#define MCPWM_TIMER2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x2c)
/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0;
* Represents current PWM timer2 counter value.
*/
@@ -412,7 +414,7 @@ extern "C" {
/** MCPWM_TIMER_SYNCI_CFG_REG register
* Synchronization input selection register for PWM timers.
*/
#define MCPWM_TIMER_SYNCI_CFG_REG (DR_REG_MCPWM_BASE + 0x30)
#define MCPWM_TIMER_SYNCI_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x30)
/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0;
* Configures the selection of sync input for PWM timer0.
* 1: PWM timer0 sync_out
@@ -486,7 +488,7 @@ extern "C" {
/** MCPWM_OPERATOR_TIMERSEL_REG register
* PWM operator's timer select register
*/
#define MCPWM_OPERATOR_TIMERSEL_REG (DR_REG_MCPWM_BASE + 0x34)
#define MCPWM_OPERATOR_TIMERSEL_REG(i) (REG_MCPWM_BASE(i) + 0x34)
/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0;
* Configures which PWM timer will be the timing reference for PWM operator0.
* 0: Timer0
@@ -524,7 +526,7 @@ extern "C" {
/** MCPWM_GEN0_STMP_CFG_REG register
* Generator0 time stamp registers A and B transfer status and update method register
*/
#define MCPWM_GEN0_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x38)
#define MCPWM_GEN0_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x38)
/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
* Configures the update method for PWM generator 0 time stamp A's active register.
* 0: Immediately
@@ -571,7 +573,7 @@ extern "C" {
/** MCPWM_GEN0_TSTMP_A_REG register
* Generator0 time stamp A's shadow register
*/
#define MCPWM_GEN0_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x3c)
#define MCPWM_GEN0_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x3c)
/** MCPWM_CMPR0_A : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator 0 time stamp A's shadow register.
*/
@@ -583,7 +585,7 @@ extern "C" {
/** MCPWM_GEN0_TSTMP_B_REG register
* Generator0 time stamp B's shadow register
*/
#define MCPWM_GEN0_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x40)
#define MCPWM_GEN0_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x40)
/** MCPWM_CMPR0_B : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator 0 time stamp B's shadow register.
*/
@@ -595,7 +597,7 @@ extern "C" {
/** MCPWM_GEN0_CFG0_REG register
* Generator0 fault event T0 and T1 configuration register
*/
#define MCPWM_GEN0_CFG0_REG (DR_REG_MCPWM_BASE + 0x44)
#define MCPWM_GEN0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x44)
/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
* Configures update method for PWM generator 0's active register.
* 0: Immediately
@@ -636,7 +638,7 @@ extern "C" {
/** MCPWM_GEN0_FORCE_REG register
* Generator0 output signal force mode register.
*/
#define MCPWM_GEN0_FORCE_REG (DR_REG_MCPWM_BASE + 0x48)
#define MCPWM_GEN0_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x48)
/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
* Configures update method for continuous software force of PWM generator0.
* 0: Immediately
@@ -716,7 +718,7 @@ extern "C" {
/** MCPWM_GEN0_A_REG register
* PWM0 output signal A actions configuration register
*/
#define MCPWM_GEN0_A_REG (DR_REG_MCPWM_BASE + 0x4c)
#define MCPWM_GEN0_A_REG(i) (REG_MCPWM_BASE(i) + 0x4c)
/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
* Configures action on PWM0 A triggered by event TEZ when timer increasing.
* 0: No change
@@ -853,7 +855,7 @@ extern "C" {
/** MCPWM_GEN0_B_REG register
* PWM0 output signal B actions configuration register
*/
#define MCPWM_GEN0_B_REG (DR_REG_MCPWM_BASE + 0x50)
#define MCPWM_GEN0_B_REG(i) (REG_MCPWM_BASE(i) + 0x50)
/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
* Configures action on PWM0 B triggered by event TEZ when timer increasing.
* 0: No change
@@ -990,7 +992,7 @@ extern "C" {
/** MCPWM_DT0_CFG_REG register
* Dead time configuration register
*/
#define MCPWM_DT0_CFG_REG (DR_REG_MCPWM_BASE + 0x54)
#define MCPWM_DT0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x54)
/** MCPWM_DB0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
* Configures update method for FED (Falling edge delay) active register.
* 0: Immediate
@@ -1093,7 +1095,7 @@ extern "C" {
/** MCPWM_DT0_FED_CFG_REG register
* Falling edge delay (FED) shadow register
*/
#define MCPWM_DT0_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x58)
#define MCPWM_DT0_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x58)
/** MCPWM_DB0_FED : R/W; bitpos: [15:0]; default: 0;
* Configures shadow register for FED.
*/
@@ -1105,7 +1107,7 @@ extern "C" {
/** MCPWM_DT0_RED_CFG_REG register
* Rising edge delay (RED) shadow register
*/
#define MCPWM_DT0_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x5c)
#define MCPWM_DT0_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x5c)
/** MCPWM_DB0_RED : R/W; bitpos: [15:0]; default: 0;
* Configures shadow register for RED.
*/
@@ -1117,7 +1119,7 @@ extern "C" {
/** MCPWM_CARRIER0_CFG_REG register
* Carrier0 configuration register
*/
#define MCPWM_CARRIER0_CFG_REG (DR_REG_MCPWM_BASE + 0x60)
#define MCPWM_CARRIER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x60)
/** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable carrier0.
* 0: Bypassed
@@ -1173,7 +1175,7 @@ extern "C" {
/** MCPWM_FH0_CFG0_REG register
* PWM0 A and PWM0 B trip events actions configuration register
*/
#define MCPWM_FH0_CFG0_REG (DR_REG_MCPWM_BASE + 0x64)
#define MCPWM_FH0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x64)
/** MCPWM_TZ0_SW_CBC : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable software force cycle-by-cycle mode action.
* 0: Disable
@@ -1346,7 +1348,7 @@ extern "C" {
/** MCPWM_FH0_CFG1_REG register
* Software triggers for fault handler actions configuration register
*/
#define MCPWM_FH0_CFG1_REG (DR_REG_MCPWM_BASE + 0x68)
#define MCPWM_FH0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x68)
/** MCPWM_TZ0_CLR_OST : R/W; bitpos: [0]; default: 0;
* Configures the generation of software one-shot mode action clear. A toggle
* (software negate its value) triggers a clear for on going one-shot mode action.
@@ -1385,7 +1387,7 @@ extern "C" {
/** MCPWM_FH0_STATUS_REG register
* Fault events status register
*/
#define MCPWM_FH0_STATUS_REG (DR_REG_MCPWM_BASE + 0x6c)
#define MCPWM_FH0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x6c)
/** MCPWM_TZ0_CBC_ON : RO; bitpos: [0]; default: 0;
* Represents whether or not an cycle-by-cycle mode action is on going.
* 0:No action
@@ -1408,7 +1410,7 @@ extern "C" {
/** MCPWM_GEN1_STMP_CFG_REG register
* Generator1 time stamp registers A and B transfer status and update method register
*/
#define MCPWM_GEN1_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x70)
#define MCPWM_GEN1_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x70)
/** MCPWM_CMPR1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
* Configures the update method for PWM generator 1 time stamp A's active register.
* 0: Immediately
@@ -1455,7 +1457,7 @@ extern "C" {
/** MCPWM_GEN1_TSTMP_A_REG register
* Generator1 time stamp A's shadow register
*/
#define MCPWM_GEN1_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x74)
#define MCPWM_GEN1_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x74)
/** MCPWM_CMPR1_A : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator 1 time stamp A's shadow register.
*/
@@ -1467,7 +1469,7 @@ extern "C" {
/** MCPWM_GEN1_TSTMP_B_REG register
* Generator1 time stamp B's shadow register
*/
#define MCPWM_GEN1_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x78)
#define MCPWM_GEN1_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x78)
/** MCPWM_CMPR1_B : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator 1 time stamp B's shadow register.
*/
@@ -1479,7 +1481,7 @@ extern "C" {
/** MCPWM_GEN1_CFG0_REG register
* Generator1 fault event T0 and T1 configuration register
*/
#define MCPWM_GEN1_CFG0_REG (DR_REG_MCPWM_BASE + 0x7c)
#define MCPWM_GEN1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x7c)
/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
* Configures update method for PWM generator 1's active register.
* 0: Immediately
@@ -1520,7 +1522,7 @@ extern "C" {
/** MCPWM_GEN1_FORCE_REG register
* Generator1 output signal force mode register.
*/
#define MCPWM_GEN1_FORCE_REG (DR_REG_MCPWM_BASE + 0x80)
#define MCPWM_GEN1_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x80)
/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
* Configures update method for continuous software force of PWM generator1.
* 0: Immediately
@@ -1600,7 +1602,7 @@ extern "C" {
/** MCPWM_GEN1_A_REG register
* PWM1 output signal A actions configuration register
*/
#define MCPWM_GEN1_A_REG (DR_REG_MCPWM_BASE + 0x84)
#define MCPWM_GEN1_A_REG(i) (REG_MCPWM_BASE(i) + 0x84)
/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
* Configures action on PWM1 A triggered by event TEZ when timer increasing.
* 0: No change
@@ -1737,7 +1739,7 @@ extern "C" {
/** MCPWM_GEN1_B_REG register
* PWM1 output signal B actions configuration register
*/
#define MCPWM_GEN1_B_REG (DR_REG_MCPWM_BASE + 0x88)
#define MCPWM_GEN1_B_REG(i) (REG_MCPWM_BASE(i) + 0x88)
/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
* Configures action on PWM1 B triggered by event TEZ when timer increasing.
* 0: No change
@@ -1874,7 +1876,7 @@ extern "C" {
/** MCPWM_DT1_CFG_REG register
* Dead time configuration register
*/
#define MCPWM_DT1_CFG_REG (DR_REG_MCPWM_BASE + 0x8c)
#define MCPWM_DT1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x8c)
/** MCPWM_DB1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
* Configures update method for FED (Falling edge delay) active register.
* 0: Immediate
@@ -1977,7 +1979,7 @@ extern "C" {
/** MCPWM_DT1_FED_CFG_REG register
* Falling edge delay (FED) shadow register
*/
#define MCPWM_DT1_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x90)
#define MCPWM_DT1_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x90)
/** MCPWM_DB1_FED : R/W; bitpos: [15:0]; default: 0;
* Configures shadow register for FED.
*/
@@ -1989,7 +1991,7 @@ extern "C" {
/** MCPWM_DT1_RED_CFG_REG register
* Rising edge delay (RED) shadow register
*/
#define MCPWM_DT1_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x94)
#define MCPWM_DT1_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x94)
/** MCPWM_DB1_RED : R/W; bitpos: [15:0]; default: 0;
* Configures shadow register for RED.
*/
@@ -2001,7 +2003,7 @@ extern "C" {
/** MCPWM_CARRIER1_CFG_REG register
* Carrier1 configuration register
*/
#define MCPWM_CARRIER1_CFG_REG (DR_REG_MCPWM_BASE + 0x98)
#define MCPWM_CARRIER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x98)
/** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable carrier1.
* 0: Bypassed
@@ -2057,7 +2059,7 @@ extern "C" {
/** MCPWM_FH1_CFG0_REG register
* PWM1 A and PWM1 B trip events actions configuration register
*/
#define MCPWM_FH1_CFG0_REG (DR_REG_MCPWM_BASE + 0x9c)
#define MCPWM_FH1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x9c)
/** MCPWM_TZ1_SW_CBC : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable software force cycle-by-cycle mode action.
* 0: Disable
@@ -2230,7 +2232,7 @@ extern "C" {
/** MCPWM_FH1_CFG1_REG register
* Software triggers for fault handler actions configuration register
*/
#define MCPWM_FH1_CFG1_REG (DR_REG_MCPWM_BASE + 0xa0)
#define MCPWM_FH1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xa0)
/** MCPWM_TZ1_CLR_OST : R/W; bitpos: [0]; default: 0;
* Configures the generation of software one-shot mode action clear. A toggle
* (software negate its value) triggers a clear for on going one-shot mode action.
@@ -2269,7 +2271,7 @@ extern "C" {
/** MCPWM_FH1_STATUS_REG register
* Fault events status register
*/
#define MCPWM_FH1_STATUS_REG (DR_REG_MCPWM_BASE + 0xa4)
#define MCPWM_FH1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xa4)
/** MCPWM_TZ1_CBC_ON : RO; bitpos: [0]; default: 0;
* Represents whether or not an cycle-by-cycle mode action is on going.
* 0:No action
@@ -2292,7 +2294,7 @@ extern "C" {
/** MCPWM_GEN2_STMP_CFG_REG register
* Generator2 time stamp registers A and B transfer status and update method register
*/
#define MCPWM_GEN2_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0xa8)
#define MCPWM_GEN2_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xa8)
/** MCPWM_CMPR2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
* Configures the update method for PWM generator 2 time stamp A's active register.
* 0: Immediately
@@ -2339,7 +2341,7 @@ extern "C" {
/** MCPWM_GEN2_TSTMP_A_REG register
* Generator2 time stamp A's shadow register
*/
#define MCPWM_GEN2_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0xac)
#define MCPWM_GEN2_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0xac)
/** MCPWM_CMPR2_A : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator 2 time stamp A's shadow register.
*/
@@ -2351,7 +2353,7 @@ extern "C" {
/** MCPWM_GEN2_TSTMP_B_REG register
* Generator2 time stamp B's shadow register
*/
#define MCPWM_GEN2_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0xb0)
#define MCPWM_GEN2_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0xb0)
/** MCPWM_CMPR2_B : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator 2 time stamp B's shadow register.
*/
@@ -2363,7 +2365,7 @@ extern "C" {
/** MCPWM_GEN2_CFG0_REG register
* Generator2 fault event T0 and T1 configuration register
*/
#define MCPWM_GEN2_CFG0_REG (DR_REG_MCPWM_BASE + 0xb4)
#define MCPWM_GEN2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xb4)
/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
* Configures update method for PWM generator 2's active register.
* 0: Immediately
@@ -2404,7 +2406,7 @@ extern "C" {
/** MCPWM_GEN2_FORCE_REG register
* Generator2 output signal force mode register.
*/
#define MCPWM_GEN2_FORCE_REG (DR_REG_MCPWM_BASE + 0xb8)
#define MCPWM_GEN2_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0xb8)
/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
* Configures update method for continuous software force of PWM generator2.
* 0: Immediately
@@ -2484,7 +2486,7 @@ extern "C" {
/** MCPWM_GEN2_A_REG register
* PWM2 output signal A actions configuration register
*/
#define MCPWM_GEN2_A_REG (DR_REG_MCPWM_BASE + 0xbc)
#define MCPWM_GEN2_A_REG(i) (REG_MCPWM_BASE(i) + 0xbc)
/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
* Configures action on PWM2 A triggered by event TEZ when timer increasing.
* 0: No change
@@ -2621,7 +2623,7 @@ extern "C" {
/** MCPWM_GEN2_B_REG register
* PWM2 output signal B actions configuration register
*/
#define MCPWM_GEN2_B_REG (DR_REG_MCPWM_BASE + 0xc0)
#define MCPWM_GEN2_B_REG(i) (REG_MCPWM_BASE(i) + 0xc0)
/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
* Configures action on PWM2 B triggered by event TEZ when timer increasing.
* 0: No change
@@ -2758,7 +2760,7 @@ extern "C" {
/** MCPWM_DT2_CFG_REG register
* Dead time configuration register
*/
#define MCPWM_DT2_CFG_REG (DR_REG_MCPWM_BASE + 0xc4)
#define MCPWM_DT2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xc4)
/** MCPWM_DB2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
* Configures update method for FED (Falling edge delay) active register.
* 0: Immediate
@@ -2861,7 +2863,7 @@ extern "C" {
/** MCPWM_DT2_FED_CFG_REG register
* Falling edge delay (FED) shadow register
*/
#define MCPWM_DT2_FED_CFG_REG (DR_REG_MCPWM_BASE + 0xc8)
#define MCPWM_DT2_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xc8)
/** MCPWM_DB2_FED : R/W; bitpos: [15:0]; default: 0;
* Configures shadow register for FED.
*/
@@ -2873,7 +2875,7 @@ extern "C" {
/** MCPWM_DT2_RED_CFG_REG register
* Rising edge delay (RED) shadow register
*/
#define MCPWM_DT2_RED_CFG_REG (DR_REG_MCPWM_BASE + 0xcc)
#define MCPWM_DT2_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xcc)
/** MCPWM_DB2_RED : R/W; bitpos: [15:0]; default: 0;
* Configures shadow register for RED.
*/
@@ -2885,7 +2887,7 @@ extern "C" {
/** MCPWM_CARRIER2_CFG_REG register
* Carrier2 configuration register
*/
#define MCPWM_CARRIER2_CFG_REG (DR_REG_MCPWM_BASE + 0xd0)
#define MCPWM_CARRIER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd0)
/** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable carrier2.
* 0: Bypassed
@@ -2941,7 +2943,7 @@ extern "C" {
/** MCPWM_FH2_CFG0_REG register
* PWM2 A and PWM2 B trip events actions configuration register
*/
#define MCPWM_FH2_CFG0_REG (DR_REG_MCPWM_BASE + 0xd4)
#define MCPWM_FH2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xd4)
/** MCPWM_TZ2_SW_CBC : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable software force cycle-by-cycle mode action.
* 0: Disable
@@ -3114,7 +3116,7 @@ extern "C" {
/** MCPWM_FH2_CFG1_REG register
* Software triggers for fault handler actions configuration register
*/
#define MCPWM_FH2_CFG1_REG (DR_REG_MCPWM_BASE + 0xd8)
#define MCPWM_FH2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xd8)
/** MCPWM_TZ2_CLR_OST : R/W; bitpos: [0]; default: 0;
* Configures the generation of software one-shot mode action clear. A toggle
* (software negate its value) triggers a clear for on going one-shot mode action.
@@ -3153,7 +3155,7 @@ extern "C" {
/** MCPWM_FH2_STATUS_REG register
* Fault events status register
*/
#define MCPWM_FH2_STATUS_REG (DR_REG_MCPWM_BASE + 0xdc)
#define MCPWM_FH2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xdc)
/** MCPWM_TZ2_CBC_ON : RO; bitpos: [0]; default: 0;
* Represents whether or not an cycle-by-cycle mode action is on going.
* 0:No action
@@ -3176,7 +3178,7 @@ extern "C" {
/** MCPWM_FAULT_DETECT_REG register
* Fault detection configuration and status register
*/
#define MCPWM_FAULT_DETECT_REG (DR_REG_MCPWM_BASE + 0xe0)
#define MCPWM_FAULT_DETECT_REG(i) (REG_MCPWM_BASE(i) + 0xe0)
/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable event_f0 generation.
* 0: Disable
@@ -3262,7 +3264,7 @@ extern "C" {
/** MCPWM_CAP_TIMER_CFG_REG register
* Capture timer configuration register
*/
#define MCPWM_CAP_TIMER_CFG_REG (DR_REG_MCPWM_BASE + 0xe4)
#define MCPWM_CAP_TIMER_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xe4)
/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable capture timer increment.
* 0: Disable
@@ -3310,7 +3312,7 @@ extern "C" {
/** MCPWM_CAP_TIMER_PHASE_REG register
* Capture timer sync phase register
*/
#define MCPWM_CAP_TIMER_PHASE_REG (DR_REG_MCPWM_BASE + 0xe8)
#define MCPWM_CAP_TIMER_PHASE_REG(i) (REG_MCPWM_BASE(i) + 0xe8)
/** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0;
* Configures phase value for capture timer sync operation.
*/
@@ -3322,7 +3324,7 @@ extern "C" {
/** MCPWM_CAP_CH0_CFG_REG register
* Capture channel 0 configuration register
*/
#define MCPWM_CAP_CH0_CFG_REG (DR_REG_MCPWM_BASE + 0xec)
#define MCPWM_CAP_CH0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xec)
/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable capture on channel 0.
* 0: Disable
@@ -3372,7 +3374,7 @@ extern "C" {
/** MCPWM_CAP_CH1_CFG_REG register
* Capture channel 1 configuration register
*/
#define MCPWM_CAP_CH1_CFG_REG (DR_REG_MCPWM_BASE + 0xf0)
#define MCPWM_CAP_CH1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf0)
/** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable capture on channel 1.
* 0: Disable
@@ -3422,7 +3424,7 @@ extern "C" {
/** MCPWM_CAP_CH2_CFG_REG register
* Capture channel 2 configuration register
*/
#define MCPWM_CAP_CH2_CFG_REG (DR_REG_MCPWM_BASE + 0xf4)
#define MCPWM_CAP_CH2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf4)
/** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable capture on channel 2.
* 0: Disable
@@ -3472,7 +3474,7 @@ extern "C" {
/** MCPWM_CAP_CH0_REG register
* CAP0 capture value register
*/
#define MCPWM_CAP_CH0_REG (DR_REG_MCPWM_BASE + 0xf8)
#define MCPWM_CAP_CH0_REG(i) (REG_MCPWM_BASE(i) + 0xf8)
/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
* Represents value of last capture on CAP0
*/
@@ -3484,7 +3486,7 @@ extern "C" {
/** MCPWM_CAP_CH1_REG register
* CAP1 capture value register
*/
#define MCPWM_CAP_CH1_REG (DR_REG_MCPWM_BASE + 0xfc)
#define MCPWM_CAP_CH1_REG(i) (REG_MCPWM_BASE(i) + 0xfc)
/** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0;
* Represents value of last capture on CAP1
*/
@@ -3496,7 +3498,7 @@ extern "C" {
/** MCPWM_CAP_CH2_REG register
* CAP2 capture value register
*/
#define MCPWM_CAP_CH2_REG (DR_REG_MCPWM_BASE + 0x100)
#define MCPWM_CAP_CH2_REG(i) (REG_MCPWM_BASE(i) + 0x100)
/** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0;
* Represents value of last capture on CAP2
*/
@@ -3508,7 +3510,7 @@ extern "C" {
/** MCPWM_CAP_STATUS_REG register
* Last capture trigger edge information register
*/
#define MCPWM_CAP_STATUS_REG (DR_REG_MCPWM_BASE + 0x104)
#define MCPWM_CAP_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x104)
/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0;
* Represents edge of last capture trigger on channel0.
* 0: Posedge
@@ -3540,7 +3542,7 @@ extern "C" {
/** MCPWM_UPDATE_CFG_REG register
* Generator Update configuration register
*/
#define MCPWM_UPDATE_CFG_REG (DR_REG_MCPWM_BASE + 0x108)
#define MCPWM_UPDATE_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x108)
/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1;
* Configures whether or not to enable global update for all active registers in MCPWM
* module.
@@ -3621,7 +3623,7 @@ extern "C" {
/** MCPWM_INT_ENA_REG register
* Interrupt enable register
*/
#define MCPWM_INT_ENA_REG (DR_REG_MCPWM_BASE + 0x10c)
#define MCPWM_INT_ENA_REG(i) (REG_MCPWM_BASE(i) + 0x10c)
/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0;
* Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops.
*/
@@ -3842,7 +3844,7 @@ extern "C" {
/** MCPWM_INT_RAW_REG register
* Interrupt raw status register
*/
#define MCPWM_INT_RAW_REG (DR_REG_MCPWM_BASE + 0x110)
#define MCPWM_INT_RAW_REG(i) (REG_MCPWM_BASE(i) + 0x110)
/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* Raw status bit: The raw interrupt status of the interrupt triggered when the timer
* 0 stops.
@@ -4087,7 +4089,7 @@ extern "C" {
/** MCPWM_INT_ST_REG register
* Interrupt masked status register
*/
#define MCPWM_INT_ST_REG (DR_REG_MCPWM_BASE + 0x114)
#define MCPWM_INT_ST_REG(i) (REG_MCPWM_BASE(i) + 0x114)
/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0;
* Masked status bit: The masked interrupt status of the interrupt triggered when the
* timer 0 stops.
@@ -4332,7 +4334,7 @@ extern "C" {
/** MCPWM_INT_CLR_REG register
* Interrupt clear register
*/
#define MCPWM_INT_CLR_REG (DR_REG_MCPWM_BASE + 0x118)
#define MCPWM_INT_CLR_REG(i) (REG_MCPWM_BASE(i) + 0x118)
/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0;
* Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops.
*/
@@ -4553,7 +4555,7 @@ extern "C" {
/** MCPWM_EVT_EN_REG register
* Event enable register
*/
#define MCPWM_EVT_EN_REG (DR_REG_MCPWM_BASE + 0x11c)
#define MCPWM_EVT_EN_REG(i) (REG_MCPWM_BASE(i) + 0x11c)
/** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable timer0 stop event generate.
* 0: Disable
@@ -4828,7 +4830,7 @@ extern "C" {
/** MCPWM_TASK_EN_REG register
* Task enable register
*/
#define MCPWM_TASK_EN_REG (DR_REG_MCPWM_BASE + 0x120)
#define MCPWM_TASK_EN_REG(i) (REG_MCPWM_BASE(i) + 0x120)
/** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable PWM generator0 timer stamp A's shadow register
* update task receive.
@@ -5091,7 +5093,7 @@ extern "C" {
/** MCPWM_EVT_EN2_REG register
* Event enable register2
*/
#define MCPWM_EVT_EN2_REG (DR_REG_MCPWM_BASE + 0x124)
#define MCPWM_EVT_EN2_REG(i) (REG_MCPWM_BASE(i) + 0x124)
/** MCPWM_EVT_OP0_TEE1_EN : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG
* event generate.
@@ -5210,7 +5212,7 @@ extern "C" {
/** MCPWM_OP0_TSTMP_E1_REG register
* Generator0 timer stamp E1 value register
*/
#define MCPWM_OP0_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x128)
#define MCPWM_OP0_TSTMP_E1_REG(i) (REG_MCPWM_BASE(i) + 0x128)
/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
* Configures generator0 timer stamp E1 value register
*/
@@ -5222,7 +5224,7 @@ extern "C" {
/** MCPWM_OP0_TSTMP_E2_REG register
* Generator0 timer stamp E2 value register
*/
#define MCPWM_OP0_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x12c)
#define MCPWM_OP0_TSTMP_E2_REG(i) (REG_MCPWM_BASE(i) + 0x12c)
/** MCPWM_OP0_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
* Configures generator0 timer stamp E2 value register
*/
@@ -5234,7 +5236,7 @@ extern "C" {
/** MCPWM_OP1_TSTMP_E1_REG register
* Generator1 timer stamp E1 value register
*/
#define MCPWM_OP1_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x130)
#define MCPWM_OP1_TSTMP_E1_REG(i) (REG_MCPWM_BASE(i) + 0x130)
/** MCPWM_OP1_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
* Configures generator1 timer stamp E1 value register
*/
@@ -5246,7 +5248,7 @@ extern "C" {
/** MCPWM_OP1_TSTMP_E2_REG register
* Generator1 timer stamp E2 value register
*/
#define MCPWM_OP1_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x134)
#define MCPWM_OP1_TSTMP_E2_REG(i) (REG_MCPWM_BASE(i) + 0x134)
/** MCPWM_OP1_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
* Configures generator1 timer stamp E2 value register
*/
@@ -5258,7 +5260,7 @@ extern "C" {
/** MCPWM_OP2_TSTMP_E1_REG register
* Generator2 timer stamp E1 value register
*/
#define MCPWM_OP2_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x138)
#define MCPWM_OP2_TSTMP_E1_REG(i) (REG_MCPWM_BASE(i) + 0x138)
/** MCPWM_OP2_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
* Configures generator2 timer stamp E1 value register
*/
@@ -5270,7 +5272,7 @@ extern "C" {
/** MCPWM_OP2_TSTMP_E2_REG register
* Generator2 timer stamp E2 value register
*/
#define MCPWM_OP2_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x13c)
#define MCPWM_OP2_TSTMP_E2_REG(i) (REG_MCPWM_BASE(i) + 0x13c)
/** MCPWM_OP2_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
* Configures generator2 timer stamp E2 value register
*/
@@ -5282,7 +5284,7 @@ extern "C" {
/** MCPWM_CLK_REG register
* Global configuration register
*/
#define MCPWM_CLK_REG (DR_REG_MCPWM_BASE + 0x140)
#define MCPWM_CLK_REG(i) (REG_MCPWM_BASE(i) + 0x140)
/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0;
* Configures whether or not to open register clock gate.
* 0: Open the clock gate only when application writes registers
@@ -5296,7 +5298,7 @@ extern "C" {
/** MCPWM_VERSION_REG register
* Version register.
*/
#define MCPWM_VERSION_REG (DR_REG_MCPWM_BASE + 0x144)
#define MCPWM_VERSION_REG(i) (REG_MCPWM_BASE(i) + 0x144)
/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 37761424;
* Configures the version.
*/
@@ -5308,7 +5310,7 @@ extern "C" {
/** MCPWM_TIMER0_CFG2_REG register
* PWM timer0 timestamp a configuration register.
*/
#define MCPWM_TIMER0_CFG2_REG (DR_REG_MCPWM_BASE + 0x14c)
#define MCPWM_TIMER0_CFG2_REG(i) (REG_MCPWM_BASE(i) + 0x14c)
/** MCPWM_TIMER0_A : R/W; bitpos: [15:0]; default: 255;
* Configures the timestamp a shadow of PWM timer0
*/
@@ -5342,7 +5344,7 @@ extern "C" {
/** MCPWM_TIMER0_CFG3_REG register
* PWM timer0 timestamp b configuration register.
*/
#define MCPWM_TIMER0_CFG3_REG (DR_REG_MCPWM_BASE + 0x150)
#define MCPWM_TIMER0_CFG3_REG(i) (REG_MCPWM_BASE(i) + 0x150)
/** MCPWM_TIMER0_B : R/W; bitpos: [15:0]; default: 255;
* Configures the timestamp b shadow of PWM timer0
*/
@@ -5376,7 +5378,7 @@ extern "C" {
/** MCPWM_TIMER1_CFG2_REG register
* PWM timer1 timestamp a configuration register.
*/
#define MCPWM_TIMER1_CFG2_REG (DR_REG_MCPWM_BASE + 0x154)
#define MCPWM_TIMER1_CFG2_REG(i) (REG_MCPWM_BASE(i) + 0x154)
/** MCPWM_TIMER1_A : R/W; bitpos: [15:0]; default: 255;
* Configures the timestamp a shadow of PWM timer1
*/
@@ -5410,7 +5412,7 @@ extern "C" {
/** MCPWM_TIMER1_CFG3_REG register
* PWM timer1 timestamp b configuration register.
*/
#define MCPWM_TIMER1_CFG3_REG (DR_REG_MCPWM_BASE + 0x158)
#define MCPWM_TIMER1_CFG3_REG(i) (REG_MCPWM_BASE(i) + 0x158)
/** MCPWM_TIMER1_B : R/W; bitpos: [15:0]; default: 255;
* Configures the timestamp b shadow of PWM timer1
*/
@@ -5444,7 +5446,7 @@ extern "C" {
/** MCPWM_TIMER2_CFG2_REG register
* PWM timer2 timestamp a configuration register.
*/
#define MCPWM_TIMER2_CFG2_REG (DR_REG_MCPWM_BASE + 0x15c)
#define MCPWM_TIMER2_CFG2_REG(i) (REG_MCPWM_BASE(i) + 0x15c)
/** MCPWM_TIMER2_A : R/W; bitpos: [15:0]; default: 255;
* Configures the timestamp a shadow of PWM timer2
*/
@@ -5478,7 +5480,7 @@ extern "C" {
/** MCPWM_TIMER2_CFG3_REG register
* PWM timer2 timestamp b configuration register.
*/
#define MCPWM_TIMER2_CFG3_REG (DR_REG_MCPWM_BASE + 0x160)
#define MCPWM_TIMER2_CFG3_REG(i) (REG_MCPWM_BASE(i) + 0x160)
/** MCPWM_TIMER2_B : R/W; bitpos: [15:0]; default: 255;
* Configures the timestamp b shadow of PWM timer2
*/
components/soc/esp32s31/register/soc/timer_group_reg.h
+205 -2
View File
@@ -1,15 +1,20 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#include "soc/soc.h"
#include "soc/reg_base.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Multi-instance reg base macro */
#define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i)*0x1000)
/** TIMG_T0CONFIG_REG register
* Timer 0 configuration register
*/
@@ -180,6 +185,176 @@ extern "C" {
#define TIMG_T0_LOAD_V 0xFFFFFFFFU
#define TIMG_T0_LOAD_S 0
/** TIMG_T1CONFIG_REG register
* Timer 1 configuration register
*/
#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x24)
/** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
* Configures whether or not to enable the timer 1 alarm function. This bit will be
* automatically cleared once an alarm occurs.
* 0: Disable
* 1: Enable
*/
#define TIMG_T1_ALARM_EN (BIT(10))
#define TIMG_T1_ALARM_EN_M (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S)
#define TIMG_T1_ALARM_EN_V 0x00000001U
#define TIMG_T1_ALARM_EN_S 10
/** TIMG_T1_DIVCNT_RST : WT; bitpos: [12]; default: 0;
* Configures whether or not to reset the timer 1 's clock divider counter.
* 0: No effect
* 1: Reset
*/
#define TIMG_T1_DIVCNT_RST (BIT(12))
#define TIMG_T1_DIVCNT_RST_M (TIMG_T1_DIVCNT_RST_V << TIMG_T1_DIVCNT_RST_S)
#define TIMG_T1_DIVCNT_RST_V 0x00000001U
#define TIMG_T1_DIVCNT_RST_S 12
/** TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1;
* Represents the timer 1 clock (T1_clk) prescaler value.
*/
#define TIMG_T1_DIVIDER 0x0000FFFFU
#define TIMG_T1_DIVIDER_M (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S)
#define TIMG_T1_DIVIDER_V 0x0000FFFFU
#define TIMG_T1_DIVIDER_S 13
/** TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1;
* Configures whether or not to enable the timer 1 auto-reload function at the time of
* alarm.
* 0: No effect
* 1: Enable
*/
#define TIMG_T1_AUTORELOAD (BIT(29))
#define TIMG_T1_AUTORELOAD_M (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S)
#define TIMG_T1_AUTORELOAD_V 0x00000001U
#define TIMG_T1_AUTORELOAD_S 29
/** TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1;
* Configures the counting direction of the timer 1 time-base counter.
* 0: Decrement
* 1: Increment
*/
#define TIMG_T1_INCREASE (BIT(30))
#define TIMG_T1_INCREASE_M (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S)
#define TIMG_T1_INCREASE_V 0x00000001U
#define TIMG_T1_INCREASE_S 30
/** TIMG_T1_EN : R/W/SS/SC; bitpos: [31]; default: 0;
* Configures whether or not to enable the timer 1 time-base counter.
* 0: Disable
* 1: Enable
*/
#define TIMG_T1_EN (BIT(31))
#define TIMG_T1_EN_M (TIMG_T1_EN_V << TIMG_T1_EN_S)
#define TIMG_T1_EN_V 0x00000001U
#define TIMG_T1_EN_S 31
/** TIMG_T1LO_REG register
* Timer 1 current value, low 32 bits
*/
#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x28)
/** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0;
* Represents the low 32 bits of the time-base counter of timer 1. Valid only after
* writing to TIMG_T1UPDATE_REG.
* Measurement unit: T1_clk
*/
#define TIMG_T1_LO 0xFFFFFFFFU
#define TIMG_T1_LO_M (TIMG_T1_LO_V << TIMG_T1_LO_S)
#define TIMG_T1_LO_V 0xFFFFFFFFU
#define TIMG_T1_LO_S 0
/** TIMG_T1HI_REG register
* Timer 1 current value, high 22 bits
*/
#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x2c)
/** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0;
* Represents the high 22 bits of the time-base counter of timer 1. Valid only after
* writing to TIMG_T1UPDATE_REG.
* Measurement unit: T1_clk
*/
#define TIMG_T1_HI 0x003FFFFFU
#define TIMG_T1_HI_M (TIMG_T1_HI_V << TIMG_T1_HI_S)
#define TIMG_T1_HI_V 0x003FFFFFU
#define TIMG_T1_HI_S 0
/** TIMG_T1UPDATE_REG register
* Write to copy current timer value to TIMGn_T0LO_REG or TIMGn_T0HI_REG
*/
#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x30)
/** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0;
* Configures to latch the counter value.
* 0: Latch
* 1: Latch
*/
#define TIMG_T1_UPDATE (BIT(31))
#define TIMG_T1_UPDATE_M (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S)
#define TIMG_T1_UPDATE_V 0x00000001U
#define TIMG_T1_UPDATE_S 31
/** TIMG_T1ALARMLO_REG register
* Timer 1 alarm value, low 32 bits
*/
#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x34)
/** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
* Configures the low 32 bits of timer 1 alarm trigger time-base counter value. Valid
* only when TIMG_T1_ALARM_EN is 1.
* Measurement unit: T1_clk
*/
#define TIMG_T1_ALARM_LO 0xFFFFFFFFU
#define TIMG_T1_ALARM_LO_M (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S)
#define TIMG_T1_ALARM_LO_V 0xFFFFFFFFU
#define TIMG_T1_ALARM_LO_S 0
/** TIMG_T1ALARMHI_REG register
* Timer 1 alarm value, high bits
*/
#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x38)
/** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
* Configures the high 22 bits of timer 1 alarm trigger time-base counter value. Valid
* only when TIMG_T1_ALARM_EN is 1.
* Measurement unit: T1_clk
*/
#define TIMG_T1_ALARM_HI 0x003FFFFFU
#define TIMG_T1_ALARM_HI_M (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S)
#define TIMG_T1_ALARM_HI_V 0x003FFFFFU
#define TIMG_T1_ALARM_HI_S 0
/** TIMG_T1LOADLO_REG register
* Timer 1 reload value, low 32 bits
*/
#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x3c)
/** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* Configures low 32 bits of the value that a reload will load onto timer 1 time-base
* counter.
* Measurement unit: T1_clk
*/
#define TIMG_T1_LOAD_LO 0xFFFFFFFFU
#define TIMG_T1_LOAD_LO_M (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S)
#define TIMG_T1_LOAD_LO_V 0xFFFFFFFFU
#define TIMG_T1_LOAD_LO_S 0
/** TIMG_T1LOADHI_REG register
* Timer 1 reload value, high 22 bits
*/
#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x40)
/** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
* Configures high 22 bits of the value that a reload will load onto timer 1 time-base
* counter.
* Measurement unit: T1_clk
*/
#define TIMG_T1_LOAD_HI 0x003FFFFFU
#define TIMG_T1_LOAD_HI_M (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S)
#define TIMG_T1_LOAD_HI_V 0x003FFFFFU
#define TIMG_T1_LOAD_HI_S 0
/** TIMG_T1LOAD_REG register
* Write to reload timer from TIMG_T1LOADLO_REG or TIMG_T1LOADHI_REG
*/
#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x44)
/** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0;
* Write any value to trigger a timer 1 time-base counter reload.
*
*/
#define TIMG_T1_LOAD 0xFFFFFFFFU
#define TIMG_T1_LOAD_M (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S)
#define TIMG_T1_LOAD_V 0xFFFFFFFFU
#define TIMG_T1_LOAD_S 0
/** TIMG_WDTCONFIG0_REG register
* Watchdog timer configuration register
*/
@@ -479,6 +654,13 @@ extern "C" {
#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
#define TIMG_T0_INT_ENA_V 0x00000001U
#define TIMG_T0_INT_ENA_S 0
/** TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0;
* Write 1 to enable the TIMG_T1_INT interrupt.
*/
#define TIMG_T1_INT_ENA (BIT(1))
#define TIMG_T1_INT_ENA_M (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S)
#define TIMG_T1_INT_ENA_V 0x00000001U
#define TIMG_T1_INT_ENA_S 1
/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0;
* Write 1 to enable the TIMG_WDT_INT interrupt.
*/
@@ -498,6 +680,13 @@ extern "C" {
#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
#define TIMG_T0_INT_RAW_V 0x00000001U
#define TIMG_T0_INT_RAW_S 0
/** TIMG_T1_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status bit of the TIMG_T1_INT interrupt.
*/
#define TIMG_T1_INT_RAW (BIT(1))
#define TIMG_T1_INT_RAW_M (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S)
#define TIMG_T1_INT_RAW_V 0x00000001U
#define TIMG_T1_INT_RAW_S 1
/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status bit of the TIMG_WDT_INT interrupt.
*/
@@ -517,6 +706,13 @@ extern "C" {
#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
#define TIMG_T0_INT_ST_V 0x00000001U
#define TIMG_T0_INT_ST_S 0
/** TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit of the TIMG_T1_INT interrupt.
*/
#define TIMG_T1_INT_ST (BIT(1))
#define TIMG_T1_INT_ST_M (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S)
#define TIMG_T1_INT_ST_V 0x00000001U
#define TIMG_T1_INT_ST_S 1
/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit of the TIMG_WDT_INT interrupt.
*/
@@ -536,6 +732,13 @@ extern "C" {
#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
#define TIMG_T0_INT_CLR_V 0x00000001U
#define TIMG_T0_INT_CLR_S 0
/** TIMG_T1_INT_CLR : WT; bitpos: [1]; default: 0;
* Write 1 to clear the TIMG_T1_INT interrupt.
*/
#define TIMG_T1_INT_CLR (BIT(1))
#define TIMG_T1_INT_CLR_M (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S)
#define TIMG_T1_INT_CLR_V 0x00000001U
#define TIMG_T1_INT_CLR_S 1
/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0;
* Write 1 to clear the TIMG_WDT_INT interrupt.
*/