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refactor(esp_system): clear dependency on hal components

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This commit is contained in:
Chen Chen
2025-12-15 22:56:09 +08:00
committed by suda-morris
parent b33c9cd7ce
commit 3cf86e260c
32 changed files with 1065 additions and 985 deletions
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components/hal/esp32c6/include/hal/clk_gate_ll.h
+121 -6
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@@ -9,10 +9,17 @@
#include <stdint.h>
#include <stdbool.h>
#include "hal/assert.h"
#include "soc/periph_defs.h"
#include "soc/pcr_reg.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "soc/reset_reasons.h"
#include "soc/periph_defs.h"
#include "soc/pcr_reg.h"
#include "soc/pcr_struct.h"
#include "soc/gdma_struct.h"
#include "soc/lpperi_struct.h"
#include "soc/lp_uart_struct.h"
#include "soc/uart_struct.h"
#include "soc/usb_serial_jtag_struct.h"
#include "esp_attr.h"
#include "soc/lp_clkrst_struct.h"
@@ -74,20 +81,20 @@ static inline uint32_t periph_ll_get_rst_en_mask(shared_periph_module_t periph,
case PERIPH_AES_MODULE:
if (enable == true) {
// Clear reset on digital signature, otherwise AES unit is held in reset
CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
PCR.ds_conf.ds_rst_en = 0;
}
return PCR_AES_RST_EN;
case PERIPH_SHA_MODULE:
if (enable == true) {
// Clear reset on digital signature and HMAC, otherwise SHA is held in reset
CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
PCR.ds_conf.ds_rst_en = 0;
PCR.hmac_conf.hmac_rst_en = 0;
}
return PCR_SHA_RST_EN;
case PERIPH_RSA_MODULE:
if (enable == true) {
// Clear reset on digital signature, otherwise RSA is held in reset
CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
PCR.ds_conf.ds_rst_en = 0;
}
return PCR_RSA_RST_EN;
case PERIPH_HMAC_MODULE:
@@ -207,6 +214,114 @@ FORCE_INLINE_ATTR void _clk_gate_ll_rtc_fast_to_lp_periph_en(bool enable)
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define clk_gate_ll_rtc_fast_to_lp_periph_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_rtc_fast_to_lp_periph_en(__VA_ARGS__)
/**
* @brief Configuration structure for peripheral clock gate settings
*/
typedef struct {
bool disable_uart0_clk; ///< Disable UART0 clock
bool disable_uart1_clk; ///< Disable UART1 clock
bool disable_mspi_flash_clk; ///< Disable MSPI flash clock
bool disable_assist_clk; ///< Disable ASSIST Debug module clock
bool disable_crypto_periph_clk; ///< Disable crypto peripherals clock
bool disable_usb_serial_jtag; ///< Disable USB-Serial-JTAG clock
} periph_ll_clk_gate_config_t;
/**
* @brief Set the default clock gate configuration
* @param config The configuration structure
*/
static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason, const periph_ll_clk_gate_config_t *config)
{
if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1) \
&& (rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT) \
&& (rst_reason != RESET_REASON_CPU0_JTAG)) {
if (config->disable_uart0_clk) {
PCR.uart0_conf.uart0_clk_en = 0;
PCR.uart0_sclk_conf.uart0_sclk_en = 0;
}
else if (config->disable_uart1_clk) {
PCR.uart1_sclk_conf.uart1_sclk_en = 0;
PCR.uart1_conf.uart1_clk_en = 0;
}
PCR.i2c_conf.i2c_clk_en = 0;
PCR.i2c_sclk_conf.i2c_sclk_en = 0;
PCR.rmt_conf.rmt_clk_en = 0;
PCR.rmt_sclk_conf.rmt_sclk_en = 0;
PCR.ledc_sclk_conf.ledc_sclk_en = 0;
PCR.ledc_conf.ledc_clk_en = 0;
PCR.timergroup0_timer_clk_conf.tg0_timer_clk_en = 0;
PCR.timergroup1_timer_clk_conf.tg1_timer_clk_en = 0;
PCR.timergroup0_conf.tg0_clk_en = 0;
PCR.timergroup1_conf.tg1_clk_en = 0;
PCR.twai0_func_clk_conf.twai0_func_clk_en = 0;
PCR.twai0_conf.twai0_clk_en = 0;
PCR.twai1_func_clk_conf.twai1_func_clk_en = 0;
PCR.twai1_conf.twai1_clk_en = 0;
PCR.i2s_conf.i2s_clk_en = 0;
PCR.i2s_tx_clkm_conf.i2s_tx_clkm_en = 0;
PCR.i2s_rx_clkm_conf.i2s_rx_clkm_en = 0;
PCR.pcnt_conf.pcnt_clk_en = 0;
PCR.etm_conf.etm_clk_en = 0;
PCR.pwm_conf.pwm_clk_en = 0;
PCR.pwm_clk_conf.pwm_clkm_en = 0;
PCR.parl_clk_rx_conf.parl_clk_rx_en = 0;
PCR.parl_clk_tx_conf.parl_clk_tx_en = 0;
PCR.parl_io_conf.parl_clk_en = 0;
PCR.gdma_conf.gdma_clk_en = 0;
if (config->disable_mspi_flash_clk) {
PCR.mspi_conf.mspi_clk_en = 0;
}
PCR.spi2_conf.spi2_clk_en = 0;
PCR.tsens_clk_conf.tsens_clk_en = 0;
PCR.uhci_conf.uhci_clk_en = 0;
PCR.saradc_conf.saradc_clk_en = 0;
PCR.sdio_slave_conf.sdio_slave_clk_en = 0;
if (config->disable_assist_clk) {
/* Disable ASSIST Debug module clock if PC recoreding function is not used,
* if stack guard function needs it, it will be re-enabled at esp_hw_stack_guard_init */
PCR.assist_conf.assist_clk_en = 0;
}
if (config->disable_crypto_periph_clk) {
// NOTE: [ESP-TEE] The TEE is responsible for the AES and SHA peripherals
PCR.aes_conf.aes_clk_en = 0;
PCR.sha_conf.sha_clk_en = 0;
PCR.hmac_conf.hmac_clk_en = 0;
PCR.ds_conf.ds_clk_en = 0;
PCR.ecc_conf.ecc_clk_en = 0;
PCR.rsa_conf.rsa_clk_en = 0;
}
PCR.ctrl_tick_conf.tick_enable = 0;
PCR.trace_conf.trace_clk_en = 0;
PCR.mem_monitor_conf.mem_monitor_clk_en = 0;
PCR.pvt_monitor_conf.pvt_monitor_clk_en = 0;
PCR.pvt_monitor_func_clk_conf.pvt_monitor_func_clk_en = 0;
PCR.ctrl_clk_out_en.val = 0;
if (config->disable_usb_serial_jtag) {
// Disable USB-Serial-JTAG clock and it's pad if not used
USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
PCR.usb_device_conf.usb_device_clk_en = 0;
}
}
if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CHIP_BROWN_OUT) \
|| (rst_reason == RESET_REASON_SYS_RTC_WDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT)) {
LP_CLKRST.lp_clk_po_en.val = 0;
LPPERI.clk_en.val = 0;
LPPERI.clk_en.efuse_ck_en = 1; // keep efuse clock enabled
LP_UART.clk_conf.val = 0;
}
}
#ifdef __cplusplus
}
#endif