mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-02 03:00:34 +03:00
Chip/support esp32c61 v5.5
This commit is contained in:
Jiang Jiang Jian
@@ -1,7 +1,7 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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/**
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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@@ -11,366 +11,524 @@
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extern "C" {
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#endif
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#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0)
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/* MODEM_LPCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: .*/
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/** MODEM_LPCON_TEST_CONF_REG register
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* need_des
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*/
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#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0)
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/** MODEM_LPCON_CLK_EN : R/W; bitpos: [0]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_EN (BIT(0))
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#define MODEM_LPCON_CLK_EN_M (BIT(0))
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#define MODEM_LPCON_CLK_EN_V 0x1
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#define MODEM_LPCON_CLK_EN_M (MODEM_LPCON_CLK_EN_V << MODEM_LPCON_CLK_EN_S)
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#define MODEM_LPCON_CLK_EN_V 0x00000001U
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#define MODEM_LPCON_CLK_EN_S 0
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#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4)
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/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFF
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#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M ((MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V)<<(MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S))
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#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0xFFF
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#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4
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/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (BIT(3))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x1
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3
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/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (BIT(2))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x1
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2
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/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (BIT(1))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x1
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1
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/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: .*/
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/** MODEM_LPCON_LP_TIMER_CONF_REG register
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* need_des
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*/
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#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4)
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/** MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW (BIT(0))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (BIT(0))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x1
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S)
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x00000001U
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S 0
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/** MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S)
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x00000001U
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1
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/** MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W; bitpos: [2]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S)
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x00000001U
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2
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/** MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W; bitpos: [3]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3))
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S)
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x00000001U
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#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3
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/** MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W; bitpos: [15:4]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFFU
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#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M (MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V << MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S)
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#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0x00000FFFU
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#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4
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#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8)
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/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFF
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M ((MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S))
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0xFFF
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4
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/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (BIT(3))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x1
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3
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/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (BIT(2))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x1
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2
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/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (BIT(1))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x1
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1
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/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: .*/
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/** MODEM_LPCON_COEX_LP_CLK_CONF_REG register
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* need_des
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*/
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#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8)
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/** MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (BIT(0))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x1
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S)
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x00000001U
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0
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/** MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S)
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x00000001U
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#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1
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/** MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S)
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x00000001U
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2
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/** MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3))
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S)
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x00000001U
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#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3
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/** MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFFU
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M (MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V << MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S)
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0x00000FFFU
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#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4
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#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xC)
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/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFF
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#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M ((MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0xFFF
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#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4
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/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (BIT(3))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x1
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3
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/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (BIT(2))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x1
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2
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/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */
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/*description: .*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (BIT(1))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x1
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1
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/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: .*/
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/** MODEM_LPCON_WIFI_LP_CLK_CONF_REG register
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* need_des
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*/
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#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xc)
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/** MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW (BIT(0))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (BIT(0))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x1
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S)
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x00000001U
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S 0
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/** MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0;
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* need_des
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*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S)
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x00000001U
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1
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/** MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0;
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* need_des
|
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*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S)
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x00000001U
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2
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/** MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0;
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* need_des
|
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*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3))
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S)
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x00000001U
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#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3
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/** MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0;
|
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* need_des
|
||||
*/
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#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFFU
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#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M (MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V << MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S)
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#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0x00000FFFU
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4
|
||||
|
||||
#define MODEM_LPCON_MODEM_SRC_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10)
|
||||
/* MODEM_LPCON_MODEM_PWR_CLK_SRC_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO (BIT(2))
|
||||
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_M (BIT(2))
|
||||
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V 0x1
|
||||
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S 2
|
||||
/* MODEM_LPCON_CLK_MODEM_AON_FORCE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_MODEM_AON_FORCE 0x00000003
|
||||
#define MODEM_LPCON_CLK_MODEM_AON_FORCE_M ((MODEM_LPCON_CLK_MODEM_AON_FORCE_V)<<(MODEM_LPCON_CLK_MODEM_AON_FORCE_S))
|
||||
#define MODEM_LPCON_CLK_MODEM_AON_FORCE_V 0x3
|
||||
/** MODEM_LPCON_MODEM_SRC_CLK_CONF_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MODEM_SRC_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10)
|
||||
/** MODEM_LPCON_CLK_MODEM_AON_FORCE : R/W; bitpos: [1:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_MODEM_AON_FORCE 0x00000003U
|
||||
#define MODEM_LPCON_CLK_MODEM_AON_FORCE_M (MODEM_LPCON_CLK_MODEM_AON_FORCE_V << MODEM_LPCON_CLK_MODEM_AON_FORCE_S)
|
||||
#define MODEM_LPCON_CLK_MODEM_AON_FORCE_V 0x00000003U
|
||||
#define MODEM_LPCON_CLK_MODEM_AON_FORCE_S 0
|
||||
/** MODEM_LPCON_MODEM_PWR_CLK_SRC_FO : R/W; bitpos: [2]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO (BIT(2))
|
||||
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_M (MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V << MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S)
|
||||
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V 0x00000001U
|
||||
#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S 2
|
||||
|
||||
#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14)
|
||||
/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003
|
||||
#define MODEM_LPCON_CLK_MODEM_32K_SEL_M ((MODEM_LPCON_CLK_MODEM_32K_SEL_V)<<(MODEM_LPCON_CLK_MODEM_32K_SEL_S))
|
||||
#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x3
|
||||
/** MODEM_LPCON_MODEM_32K_CLK_CONF_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14)
|
||||
/** MODEM_LPCON_CLK_MODEM_32K_SEL : R/W; bitpos: [1:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003U
|
||||
#define MODEM_LPCON_CLK_MODEM_32K_SEL_M (MODEM_LPCON_CLK_MODEM_32K_SEL_V << MODEM_LPCON_CLK_MODEM_32K_SEL_S)
|
||||
#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x00000003U
|
||||
#define MODEM_LPCON_CLK_MODEM_32K_SEL_S 0
|
||||
|
||||
#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18)
|
||||
/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3))
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_EN_M (BIT(3))
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x1
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3
|
||||
/* MODEM_LPCON_CLK_I2C_MST_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2))
|
||||
#define MODEM_LPCON_CLK_I2C_MST_EN_M (BIT(2))
|
||||
#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x1
|
||||
#define MODEM_LPCON_CLK_I2C_MST_EN_S 2
|
||||
/* MODEM_LPCON_CLK_COEX_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_COEX_EN (BIT(1))
|
||||
#define MODEM_LPCON_CLK_COEX_EN_M (BIT(1))
|
||||
#define MODEM_LPCON_CLK_COEX_EN_V 0x1
|
||||
#define MODEM_LPCON_CLK_COEX_EN_S 1
|
||||
/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
/** MODEM_LPCON_CLK_CONF_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18)
|
||||
/** MODEM_LPCON_CLK_WIFIPWR_EN : R/W; bitpos: [0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_EN (BIT(0))
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_EN_M (BIT(0))
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x1
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_EN_M (MODEM_LPCON_CLK_WIFIPWR_EN_V << MODEM_LPCON_CLK_WIFIPWR_EN_S)
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_EN_S 0
|
||||
/** MODEM_LPCON_CLK_COEX_EN : R/W; bitpos: [1]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_COEX_EN (BIT(1))
|
||||
#define MODEM_LPCON_CLK_COEX_EN_M (MODEM_LPCON_CLK_COEX_EN_V << MODEM_LPCON_CLK_COEX_EN_S)
|
||||
#define MODEM_LPCON_CLK_COEX_EN_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_COEX_EN_S 1
|
||||
/** MODEM_LPCON_CLK_I2C_MST_EN : R/W; bitpos: [2]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2))
|
||||
#define MODEM_LPCON_CLK_I2C_MST_EN_M (MODEM_LPCON_CLK_I2C_MST_EN_V << MODEM_LPCON_CLK_I2C_MST_EN_S)
|
||||
#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_I2C_MST_EN_S 2
|
||||
/** MODEM_LPCON_CLK_LP_TIMER_EN : R/W; bitpos: [3]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3))
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_EN_M (MODEM_LPCON_CLK_LP_TIMER_EN_V << MODEM_LPCON_CLK_LP_TIMER_EN_S)
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3
|
||||
|
||||
#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1C)
|
||||
/* MODEM_LPCON_CLK_FE_MEM_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_FE_MEM_FO (BIT(4))
|
||||
#define MODEM_LPCON_CLK_FE_MEM_FO_M (BIT(4))
|
||||
#define MODEM_LPCON_CLK_FE_MEM_FO_V 0x1
|
||||
#define MODEM_LPCON_CLK_FE_MEM_FO_S 4
|
||||
/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3))
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_FO_M (BIT(3))
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x1
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3
|
||||
/* MODEM_LPCON_CLK_I2C_MST_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2))
|
||||
#define MODEM_LPCON_CLK_I2C_MST_FO_M (BIT(2))
|
||||
#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x1
|
||||
#define MODEM_LPCON_CLK_I2C_MST_FO_S 2
|
||||
/* MODEM_LPCON_CLK_COEX_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_COEX_FO (BIT(1))
|
||||
#define MODEM_LPCON_CLK_COEX_FO_M (BIT(1))
|
||||
#define MODEM_LPCON_CLK_COEX_FO_V 0x1
|
||||
#define MODEM_LPCON_CLK_COEX_FO_S 1
|
||||
/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
/** MODEM_LPCON_CLK_CONF_FORCE_ON_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1c)
|
||||
/** MODEM_LPCON_CLK_WIFIPWR_FO : R/W; bitpos: [0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_FO (BIT(0))
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_FO_M (BIT(0))
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x1
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_FO_M (MODEM_LPCON_CLK_WIFIPWR_FO_V << MODEM_LPCON_CLK_WIFIPWR_FO_S)
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_FO_S 0
|
||||
/** MODEM_LPCON_CLK_COEX_FO : R/W; bitpos: [1]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_COEX_FO (BIT(1))
|
||||
#define MODEM_LPCON_CLK_COEX_FO_M (MODEM_LPCON_CLK_COEX_FO_V << MODEM_LPCON_CLK_COEX_FO_S)
|
||||
#define MODEM_LPCON_CLK_COEX_FO_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_COEX_FO_S 1
|
||||
/** MODEM_LPCON_CLK_I2C_MST_FO : R/W; bitpos: [2]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2))
|
||||
#define MODEM_LPCON_CLK_I2C_MST_FO_M (MODEM_LPCON_CLK_I2C_MST_FO_V << MODEM_LPCON_CLK_I2C_MST_FO_S)
|
||||
#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_I2C_MST_FO_S 2
|
||||
/** MODEM_LPCON_CLK_LP_TIMER_FO : R/W; bitpos: [3]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3))
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_FO_M (MODEM_LPCON_CLK_LP_TIMER_FO_V << MODEM_LPCON_CLK_LP_TIMER_FO_S)
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3
|
||||
/** MODEM_LPCON_CLK_FE_MEM_FO : R/W; bitpos: [4]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_FE_MEM_FO (BIT(4))
|
||||
#define MODEM_LPCON_CLK_FE_MEM_FO_M (MODEM_LPCON_CLK_FE_MEM_FO_V << MODEM_LPCON_CLK_FE_MEM_FO_S)
|
||||
#define MODEM_LPCON_CLK_FE_MEM_FO_V 0x00000001U
|
||||
#define MODEM_LPCON_CLK_FE_MEM_FO_S 4
|
||||
|
||||
#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20)
|
||||
/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000F
|
||||
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M ((MODEM_LPCON_CLK_LP_APB_ST_MAP_V)<<(MODEM_LPCON_CLK_LP_APB_ST_MAP_S))
|
||||
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0xF
|
||||
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28
|
||||
/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000F
|
||||
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M ((MODEM_LPCON_CLK_I2C_MST_ST_MAP_V)<<(MODEM_LPCON_CLK_I2C_MST_ST_MAP_S))
|
||||
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0xF
|
||||
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24
|
||||
/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000F
|
||||
#define MODEM_LPCON_CLK_COEX_ST_MAP_M ((MODEM_LPCON_CLK_COEX_ST_MAP_V)<<(MODEM_LPCON_CLK_COEX_ST_MAP_S))
|
||||
#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0xF
|
||||
#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20
|
||||
/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000F
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M ((MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V)<<(MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S))
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0xF
|
||||
/** MODEM_LPCON_CLK_CONF_POWER_ST_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20)
|
||||
/** MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W; bitpos: [19:16]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000FU
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M (MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V << MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S)
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0x0000000FU
|
||||
#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S 16
|
||||
/** MODEM_LPCON_CLK_COEX_ST_MAP : R/W; bitpos: [23:20]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000FU
|
||||
#define MODEM_LPCON_CLK_COEX_ST_MAP_M (MODEM_LPCON_CLK_COEX_ST_MAP_V << MODEM_LPCON_CLK_COEX_ST_MAP_S)
|
||||
#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0x0000000FU
|
||||
#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20
|
||||
/** MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W; bitpos: [27:24]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000FU
|
||||
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M (MODEM_LPCON_CLK_I2C_MST_ST_MAP_V << MODEM_LPCON_CLK_I2C_MST_ST_MAP_S)
|
||||
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0x0000000FU
|
||||
#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24
|
||||
/** MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000FU
|
||||
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M (MODEM_LPCON_CLK_LP_APB_ST_MAP_V << MODEM_LPCON_CLK_LP_APB_ST_MAP_S)
|
||||
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0x0000000FU
|
||||
#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28
|
||||
|
||||
#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24)
|
||||
/* MODEM_LPCON_RST_LP_TIMER : WO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_RST_LP_TIMER (BIT(3))
|
||||
#define MODEM_LPCON_RST_LP_TIMER_M (BIT(3))
|
||||
#define MODEM_LPCON_RST_LP_TIMER_V 0x1
|
||||
#define MODEM_LPCON_RST_LP_TIMER_S 3
|
||||
/* MODEM_LPCON_RST_I2C_MST : WO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_RST_I2C_MST (BIT(2))
|
||||
#define MODEM_LPCON_RST_I2C_MST_M (BIT(2))
|
||||
#define MODEM_LPCON_RST_I2C_MST_V 0x1
|
||||
#define MODEM_LPCON_RST_I2C_MST_S 2
|
||||
/* MODEM_LPCON_RST_COEX : WO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_RST_COEX (BIT(1))
|
||||
#define MODEM_LPCON_RST_COEX_M (BIT(1))
|
||||
#define MODEM_LPCON_RST_COEX_V 0x1
|
||||
#define MODEM_LPCON_RST_COEX_S 1
|
||||
/* MODEM_LPCON_RST_WIFIPWR : WO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
/** MODEM_LPCON_RST_CONF_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24)
|
||||
/** MODEM_LPCON_RST_WIFIPWR : WO; bitpos: [0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_RST_WIFIPWR (BIT(0))
|
||||
#define MODEM_LPCON_RST_WIFIPWR_M (BIT(0))
|
||||
#define MODEM_LPCON_RST_WIFIPWR_V 0x1
|
||||
#define MODEM_LPCON_RST_WIFIPWR_M (MODEM_LPCON_RST_WIFIPWR_V << MODEM_LPCON_RST_WIFIPWR_S)
|
||||
#define MODEM_LPCON_RST_WIFIPWR_V 0x00000001U
|
||||
#define MODEM_LPCON_RST_WIFIPWR_S 0
|
||||
/** MODEM_LPCON_RST_COEX : WO; bitpos: [1]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_RST_COEX (BIT(1))
|
||||
#define MODEM_LPCON_RST_COEX_M (MODEM_LPCON_RST_COEX_V << MODEM_LPCON_RST_COEX_S)
|
||||
#define MODEM_LPCON_RST_COEX_V 0x00000001U
|
||||
#define MODEM_LPCON_RST_COEX_S 1
|
||||
/** MODEM_LPCON_RST_I2C_MST : WO; bitpos: [2]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_RST_I2C_MST (BIT(2))
|
||||
#define MODEM_LPCON_RST_I2C_MST_M (MODEM_LPCON_RST_I2C_MST_V << MODEM_LPCON_RST_I2C_MST_S)
|
||||
#define MODEM_LPCON_RST_I2C_MST_V 0x00000001U
|
||||
#define MODEM_LPCON_RST_I2C_MST_S 2
|
||||
/** MODEM_LPCON_RST_LP_TIMER : WO; bitpos: [3]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_RST_LP_TIMER (BIT(3))
|
||||
#define MODEM_LPCON_RST_LP_TIMER_M (MODEM_LPCON_RST_LP_TIMER_V << MODEM_LPCON_RST_LP_TIMER_S)
|
||||
#define MODEM_LPCON_RST_LP_TIMER_V 0x00000001U
|
||||
#define MODEM_LPCON_RST_LP_TIMER_S 3
|
||||
/** MODEM_LPCON_RST_DCMEM : WO; bitpos: [4]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_RST_DCMEM (BIT(4))
|
||||
#define MODEM_LPCON_RST_DCMEM_M (MODEM_LPCON_RST_DCMEM_V << MODEM_LPCON_RST_DCMEM_S)
|
||||
#define MODEM_LPCON_RST_DCMEM_V 0x00000001U
|
||||
#define MODEM_LPCON_RST_DCMEM_S 4
|
||||
|
||||
#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28)
|
||||
/* MODEM_LPCON_MODEM_PWR_TICK_TARGET : R/W ;bitpos:[5:0] ;default: 6'd39 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET 0x0000003F
|
||||
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_M ((MODEM_LPCON_MODEM_PWR_TICK_TARGET_V)<<(MODEM_LPCON_MODEM_PWR_TICK_TARGET_S))
|
||||
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_V 0x3F
|
||||
/** MODEM_LPCON_TICK_CONF_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28)
|
||||
/** MODEM_LPCON_MODEM_PWR_TICK_TARGET : R/W; bitpos: [5:0]; default: 39;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET 0x0000003FU
|
||||
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_M (MODEM_LPCON_MODEM_PWR_TICK_TARGET_V << MODEM_LPCON_MODEM_PWR_TICK_TARGET_S)
|
||||
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_V 0x0000003FU
|
||||
#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_S 0
|
||||
|
||||
#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x2C)
|
||||
/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE : R/W ;bitpos:[23] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE (BIT(23))
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_M (BIT(23))
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V 0x1
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S 23
|
||||
/* MODEM_LPCON_CHAN_FREQ_MEM_MODE : R/W ;bitpos:[22:20] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE 0x00000007
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_M ((MODEM_LPCON_CHAN_FREQ_MEM_MODE_V)<<(MODEM_LPCON_CHAN_FREQ_MEM_MODE_S))
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_V 0x7
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_S 20
|
||||
/* MODEM_LPCON_I2C_MST_MEM_FORCE : R/W ;bitpos:[19] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_I2C_MST_MEM_FORCE (BIT(19))
|
||||
#define MODEM_LPCON_I2C_MST_MEM_FORCE_M (BIT(19))
|
||||
#define MODEM_LPCON_I2C_MST_MEM_FORCE_V 0x1
|
||||
#define MODEM_LPCON_I2C_MST_MEM_FORCE_S 19
|
||||
/* MODEM_LPCON_I2C_MST_MEM_MODE : R/W ;bitpos:[18:16] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_I2C_MST_MEM_MODE 0x00000007
|
||||
#define MODEM_LPCON_I2C_MST_MEM_MODE_M ((MODEM_LPCON_I2C_MST_MEM_MODE_V)<<(MODEM_LPCON_I2C_MST_MEM_MODE_S))
|
||||
#define MODEM_LPCON_I2C_MST_MEM_MODE_V 0x7
|
||||
#define MODEM_LPCON_I2C_MST_MEM_MODE_S 16
|
||||
/* MODEM_LPCON_BC_MEM_FORCE : R/W ;bitpos:[15] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_BC_MEM_FORCE (BIT(15))
|
||||
#define MODEM_LPCON_BC_MEM_FORCE_M (BIT(15))
|
||||
#define MODEM_LPCON_BC_MEM_FORCE_V 0x1
|
||||
#define MODEM_LPCON_BC_MEM_FORCE_S 15
|
||||
/* MODEM_LPCON_BC_MEM_MODE : R/W ;bitpos:[14:12] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_BC_MEM_MODE 0x00000007
|
||||
#define MODEM_LPCON_BC_MEM_MODE_M ((MODEM_LPCON_BC_MEM_MODE_V)<<(MODEM_LPCON_BC_MEM_MODE_S))
|
||||
#define MODEM_LPCON_BC_MEM_MODE_V 0x7
|
||||
#define MODEM_LPCON_BC_MEM_MODE_S 12
|
||||
/* MODEM_LPCON_PBUS_MEM_FORCE : R/W ;bitpos:[11] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_PBUS_MEM_FORCE (BIT(11))
|
||||
#define MODEM_LPCON_PBUS_MEM_FORCE_M (BIT(11))
|
||||
#define MODEM_LPCON_PBUS_MEM_FORCE_V 0x1
|
||||
#define MODEM_LPCON_PBUS_MEM_FORCE_S 11
|
||||
/* MODEM_LPCON_PBUS_MEM_MODE : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_PBUS_MEM_MODE 0x00000007
|
||||
#define MODEM_LPCON_PBUS_MEM_MODE_M ((MODEM_LPCON_PBUS_MEM_MODE_V)<<(MODEM_LPCON_PBUS_MEM_MODE_S))
|
||||
#define MODEM_LPCON_PBUS_MEM_MODE_V 0x7
|
||||
#define MODEM_LPCON_PBUS_MEM_MODE_S 8
|
||||
/* MODEM_LPCON_AGC_MEM_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_AGC_MEM_FORCE (BIT(7))
|
||||
#define MODEM_LPCON_AGC_MEM_FORCE_M (BIT(7))
|
||||
#define MODEM_LPCON_AGC_MEM_FORCE_V 0x1
|
||||
#define MODEM_LPCON_AGC_MEM_FORCE_S 7
|
||||
/* MODEM_LPCON_AGC_MEM_MODE : R/W ;bitpos:[6:4] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_AGC_MEM_MODE 0x00000007
|
||||
#define MODEM_LPCON_AGC_MEM_MODE_M ((MODEM_LPCON_AGC_MEM_MODE_V)<<(MODEM_LPCON_AGC_MEM_MODE_S))
|
||||
#define MODEM_LPCON_AGC_MEM_MODE_V 0x7
|
||||
#define MODEM_LPCON_AGC_MEM_MODE_S 4
|
||||
/* MODEM_LPCON_DC_MEM_FORCE : R/W ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_DC_MEM_FORCE (BIT(3))
|
||||
#define MODEM_LPCON_DC_MEM_FORCE_M (BIT(3))
|
||||
#define MODEM_LPCON_DC_MEM_FORCE_V 0x1
|
||||
#define MODEM_LPCON_DC_MEM_FORCE_S 3
|
||||
/* MODEM_LPCON_DC_MEM_MODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_DC_MEM_MODE 0x00000007
|
||||
#define MODEM_LPCON_DC_MEM_MODE_M ((MODEM_LPCON_DC_MEM_MODE_V)<<(MODEM_LPCON_DC_MEM_MODE_S))
|
||||
#define MODEM_LPCON_DC_MEM_MODE_V 0x7
|
||||
/** MODEM_LPCON_MEM_CONF_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x2c)
|
||||
/** MODEM_LPCON_DC_MEM_MODE : R/W; bitpos: [2:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_DC_MEM_MODE 0x00000007U
|
||||
#define MODEM_LPCON_DC_MEM_MODE_M (MODEM_LPCON_DC_MEM_MODE_V << MODEM_LPCON_DC_MEM_MODE_S)
|
||||
#define MODEM_LPCON_DC_MEM_MODE_V 0x00000007U
|
||||
#define MODEM_LPCON_DC_MEM_MODE_S 0
|
||||
/** MODEM_LPCON_DC_MEM_FORCE : R/W; bitpos: [3]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_DC_MEM_FORCE (BIT(3))
|
||||
#define MODEM_LPCON_DC_MEM_FORCE_M (MODEM_LPCON_DC_MEM_FORCE_V << MODEM_LPCON_DC_MEM_FORCE_S)
|
||||
#define MODEM_LPCON_DC_MEM_FORCE_V 0x00000001U
|
||||
#define MODEM_LPCON_DC_MEM_FORCE_S 3
|
||||
/** MODEM_LPCON_AGC_MEM_MODE : R/W; bitpos: [6:4]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_AGC_MEM_MODE 0x00000007U
|
||||
#define MODEM_LPCON_AGC_MEM_MODE_M (MODEM_LPCON_AGC_MEM_MODE_V << MODEM_LPCON_AGC_MEM_MODE_S)
|
||||
#define MODEM_LPCON_AGC_MEM_MODE_V 0x00000007U
|
||||
#define MODEM_LPCON_AGC_MEM_MODE_S 4
|
||||
/** MODEM_LPCON_AGC_MEM_FORCE : R/W; bitpos: [7]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_AGC_MEM_FORCE (BIT(7))
|
||||
#define MODEM_LPCON_AGC_MEM_FORCE_M (MODEM_LPCON_AGC_MEM_FORCE_V << MODEM_LPCON_AGC_MEM_FORCE_S)
|
||||
#define MODEM_LPCON_AGC_MEM_FORCE_V 0x00000001U
|
||||
#define MODEM_LPCON_AGC_MEM_FORCE_S 7
|
||||
/** MODEM_LPCON_PBUS_MEM_MODE : R/W; bitpos: [10:8]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_PBUS_MEM_MODE 0x00000007U
|
||||
#define MODEM_LPCON_PBUS_MEM_MODE_M (MODEM_LPCON_PBUS_MEM_MODE_V << MODEM_LPCON_PBUS_MEM_MODE_S)
|
||||
#define MODEM_LPCON_PBUS_MEM_MODE_V 0x00000007U
|
||||
#define MODEM_LPCON_PBUS_MEM_MODE_S 8
|
||||
/** MODEM_LPCON_PBUS_MEM_FORCE : R/W; bitpos: [11]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_PBUS_MEM_FORCE (BIT(11))
|
||||
#define MODEM_LPCON_PBUS_MEM_FORCE_M (MODEM_LPCON_PBUS_MEM_FORCE_V << MODEM_LPCON_PBUS_MEM_FORCE_S)
|
||||
#define MODEM_LPCON_PBUS_MEM_FORCE_V 0x00000001U
|
||||
#define MODEM_LPCON_PBUS_MEM_FORCE_S 11
|
||||
/** MODEM_LPCON_BC_MEM_MODE : R/W; bitpos: [14:12]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_BC_MEM_MODE 0x00000007U
|
||||
#define MODEM_LPCON_BC_MEM_MODE_M (MODEM_LPCON_BC_MEM_MODE_V << MODEM_LPCON_BC_MEM_MODE_S)
|
||||
#define MODEM_LPCON_BC_MEM_MODE_V 0x00000007U
|
||||
#define MODEM_LPCON_BC_MEM_MODE_S 12
|
||||
/** MODEM_LPCON_BC_MEM_FORCE : R/W; bitpos: [15]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_BC_MEM_FORCE (BIT(15))
|
||||
#define MODEM_LPCON_BC_MEM_FORCE_M (MODEM_LPCON_BC_MEM_FORCE_V << MODEM_LPCON_BC_MEM_FORCE_S)
|
||||
#define MODEM_LPCON_BC_MEM_FORCE_V 0x00000001U
|
||||
#define MODEM_LPCON_BC_MEM_FORCE_S 15
|
||||
/** MODEM_LPCON_I2C_MST_MEM_MODE : R/W; bitpos: [18:16]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_I2C_MST_MEM_MODE 0x00000007U
|
||||
#define MODEM_LPCON_I2C_MST_MEM_MODE_M (MODEM_LPCON_I2C_MST_MEM_MODE_V << MODEM_LPCON_I2C_MST_MEM_MODE_S)
|
||||
#define MODEM_LPCON_I2C_MST_MEM_MODE_V 0x00000007U
|
||||
#define MODEM_LPCON_I2C_MST_MEM_MODE_S 16
|
||||
/** MODEM_LPCON_I2C_MST_MEM_FORCE : R/W; bitpos: [19]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_I2C_MST_MEM_FORCE (BIT(19))
|
||||
#define MODEM_LPCON_I2C_MST_MEM_FORCE_M (MODEM_LPCON_I2C_MST_MEM_FORCE_V << MODEM_LPCON_I2C_MST_MEM_FORCE_S)
|
||||
#define MODEM_LPCON_I2C_MST_MEM_FORCE_V 0x00000001U
|
||||
#define MODEM_LPCON_I2C_MST_MEM_FORCE_S 19
|
||||
/** MODEM_LPCON_CHAN_FREQ_MEM_MODE : R/W; bitpos: [22:20]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE 0x00000007U
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_M (MODEM_LPCON_CHAN_FREQ_MEM_MODE_V << MODEM_LPCON_CHAN_FREQ_MEM_MODE_S)
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_V 0x00000007U
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_S 20
|
||||
/** MODEM_LPCON_CHAN_FREQ_MEM_FORCE : R/W; bitpos: [23]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE (BIT(23))
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_M (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S)
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V 0x00000001U
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S 23
|
||||
|
||||
#define MODEM_LPCON_MEM_RF1_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x30)
|
||||
/* MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL 0xFFFFFFFF
|
||||
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S))
|
||||
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V 0xFFFFFFFF
|
||||
/** MODEM_LPCON_MEM_RF1_AUX_CTRL_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MEM_RF1_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x30)
|
||||
/** MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL 0xFFFFFFFFU
|
||||
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_M (MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V << MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S)
|
||||
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V 0xFFFFFFFFU
|
||||
#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S 0
|
||||
|
||||
#define MODEM_LPCON_MEM_RF2_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x34)
|
||||
/* MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL 0xFFFFFFFF
|
||||
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S))
|
||||
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V 0xFFFFFFFF
|
||||
/** MODEM_LPCON_MEM_RF2_AUX_CTRL_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MEM_RF2_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x34)
|
||||
/** MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL 0xFFFFFFFFU
|
||||
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_M (MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V << MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S)
|
||||
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V 0xFFFFFFFFU
|
||||
#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S 0
|
||||
|
||||
#define MODEM_LPCON_APB_MEM_SEL_REG (DR_REG_MODEM_LPCON_BASE + 0x38)
|
||||
/* MODEM_LPCON_AGC_MEM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_AGC_MEM_EN (BIT(2))
|
||||
#define MODEM_LPCON_AGC_MEM_EN_M (BIT(2))
|
||||
#define MODEM_LPCON_AGC_MEM_EN_V 0x1
|
||||
#define MODEM_LPCON_AGC_MEM_EN_S 2
|
||||
/* MODEM_LPCON_PBUS_MEM_EN : R/W ;bitpos:[1] ;default: 'b0 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_PBUS_MEM_EN (BIT(1))
|
||||
#define MODEM_LPCON_PBUS_MEM_EN_M (BIT(1))
|
||||
#define MODEM_LPCON_PBUS_MEM_EN_V 0x1
|
||||
#define MODEM_LPCON_PBUS_MEM_EN_S 1
|
||||
/* MODEM_LPCON_CHAN_FREQ_MEM_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
/** MODEM_LPCON_APB_MEM_SEL_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_APB_MEM_SEL_REG (DR_REG_MODEM_LPCON_BASE + 0x38)
|
||||
/** MODEM_LPCON_CHAN_FREQ_MEM_EN : R/W; bitpos: [0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_EN (BIT(0))
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_EN_M (BIT(0))
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_EN_V 0x1
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_EN_M (MODEM_LPCON_CHAN_FREQ_MEM_EN_V << MODEM_LPCON_CHAN_FREQ_MEM_EN_S)
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_EN_V 0x00000001U
|
||||
#define MODEM_LPCON_CHAN_FREQ_MEM_EN_S 0
|
||||
/** MODEM_LPCON_PBUS_MEM_EN : R/W; bitpos: [1]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_PBUS_MEM_EN (BIT(1))
|
||||
#define MODEM_LPCON_PBUS_MEM_EN_M (MODEM_LPCON_PBUS_MEM_EN_V << MODEM_LPCON_PBUS_MEM_EN_S)
|
||||
#define MODEM_LPCON_PBUS_MEM_EN_V 0x00000001U
|
||||
#define MODEM_LPCON_PBUS_MEM_EN_S 1
|
||||
/** MODEM_LPCON_AGC_MEM_EN : R/W; bitpos: [2]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_AGC_MEM_EN (BIT(2))
|
||||
#define MODEM_LPCON_AGC_MEM_EN_M (MODEM_LPCON_AGC_MEM_EN_V << MODEM_LPCON_AGC_MEM_EN_S)
|
||||
#define MODEM_LPCON_AGC_MEM_EN_V 0x00000001U
|
||||
#define MODEM_LPCON_AGC_MEM_EN_S 2
|
||||
|
||||
#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x3C)
|
||||
/* MODEM_LPCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2311220 ; */
|
||||
/*description: .*/
|
||||
#define MODEM_LPCON_DATE 0x0FFFFFFF
|
||||
#define MODEM_LPCON_DATE_M ((MODEM_LPCON_DATE_V)<<(MODEM_LPCON_DATE_S))
|
||||
#define MODEM_LPCON_DATE_V 0xFFFFFFF
|
||||
/** MODEM_LPCON_DCMEM_VALID_0_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_DCMEM_VALID_0_REG (DR_REG_MODEM_LPCON_BASE + 0x3c)
|
||||
/** MODEM_LPCON__DCMEM_VALID_0 : RO; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON__DCMEM_VALID_0 0xFFFFFFFFU
|
||||
#define MODEM_LPCON__DCMEM_VALID_0_M (MODEM_LPCON__DCMEM_VALID_0_V << MODEM_LPCON__DCMEM_VALID_0_S)
|
||||
#define MODEM_LPCON__DCMEM_VALID_0_V 0xFFFFFFFFU
|
||||
#define MODEM_LPCON__DCMEM_VALID_0_S 0
|
||||
|
||||
/** MODEM_LPCON_DCMEM_VALID_1_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_DCMEM_VALID_1_REG (DR_REG_MODEM_LPCON_BASE + 0x40)
|
||||
/** MODEM_LPCON__DCMEM_VALID_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON__DCMEM_VALID_1 0xFFFFFFFFU
|
||||
#define MODEM_LPCON__DCMEM_VALID_1_M (MODEM_LPCON__DCMEM_VALID_1_V << MODEM_LPCON__DCMEM_VALID_1_S)
|
||||
#define MODEM_LPCON__DCMEM_VALID_1_V 0xFFFFFFFFU
|
||||
#define MODEM_LPCON__DCMEM_VALID_1_S 0
|
||||
|
||||
/** MODEM_LPCON_DCMEM_VALID_2_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_DCMEM_VALID_2_REG (DR_REG_MODEM_LPCON_BASE + 0x44)
|
||||
/** MODEM_LPCON__DCMEM_VALID_2 : RO; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON__DCMEM_VALID_2 0xFFFFFFFFU
|
||||
#define MODEM_LPCON__DCMEM_VALID_2_M (MODEM_LPCON__DCMEM_VALID_2_V << MODEM_LPCON__DCMEM_VALID_2_S)
|
||||
#define MODEM_LPCON__DCMEM_VALID_2_V 0xFFFFFFFFU
|
||||
#define MODEM_LPCON__DCMEM_VALID_2_S 0
|
||||
|
||||
/** MODEM_LPCON_DCMEM_VALID_3_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_DCMEM_VALID_3_REG (DR_REG_MODEM_LPCON_BASE + 0x48)
|
||||
/** MODEM_LPCON__DCMEM_VALID_3 : RO; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON__DCMEM_VALID_3 0xFFFFFFFFU
|
||||
#define MODEM_LPCON__DCMEM_VALID_3_M (MODEM_LPCON__DCMEM_VALID_3_V << MODEM_LPCON__DCMEM_VALID_3_S)
|
||||
#define MODEM_LPCON__DCMEM_VALID_3_V 0xFFFFFFFFU
|
||||
#define MODEM_LPCON__DCMEM_VALID_3_S 0
|
||||
|
||||
/** MODEM_LPCON_DATE_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x4c)
|
||||
/** MODEM_LPCON_DATE : R/W; bitpos: [27:0]; default: 37814640;
|
||||
* need_des
|
||||
*/
|
||||
#define MODEM_LPCON_DATE 0x0FFFFFFFU
|
||||
#define MODEM_LPCON_DATE_M (MODEM_LPCON_DATE_V << MODEM_LPCON_DATE_S)
|
||||
#define MODEM_LPCON_DATE_V 0x0FFFFFFFU
|
||||
#define MODEM_LPCON_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
@@ -10,240 +10,228 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en : 1;
|
||||
uint32_t reserved1 : 1;
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} test_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_lp_timer_sel_osc_slow : 1;
|
||||
uint32_t clk_lp_timer_sel_osc_fast : 1;
|
||||
uint32_t clk_lp_timer_sel_xtal : 1;
|
||||
uint32_t clk_lp_timer_sel_xtal32k : 1;
|
||||
uint32_t clk_lp_timer_div_num : 12;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_timer_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_coex_lp_sel_osc_slow : 1;
|
||||
uint32_t clk_coex_lp_sel_osc_fast : 1;
|
||||
uint32_t clk_coex_lp_sel_xtal : 1;
|
||||
uint32_t clk_coex_lp_sel_xtal32k : 1;
|
||||
uint32_t clk_coex_lp_div_num : 12;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} coex_lp_clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_wifipwr_lp_sel_osc_slow: 1;
|
||||
uint32_t clk_wifipwr_lp_sel_osc_fast: 1;
|
||||
uint32_t clk_wifipwr_lp_sel_xtal : 1;
|
||||
uint32_t clk_wifipwr_lp_sel_xtal32k: 1;
|
||||
uint32_t clk_wifipwr_lp_div_num : 12;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} wifi_lp_clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_modem_aon_force : 2;
|
||||
uint32_t modem_pwr_clk_src_fo : 1;
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_src_clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_modem_32k_sel : 2;
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_32k_clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_wifipwr_en : 1;
|
||||
uint32_t clk_coex_en : 1;
|
||||
uint32_t clk_i2c_mst_en : 1;
|
||||
uint32_t clk_lp_timer_en : 1;
|
||||
uint32_t reserved4 : 1;
|
||||
uint32_t reserved5 : 1;
|
||||
uint32_t reserved6 : 1;
|
||||
uint32_t reserved7 : 1;
|
||||
uint32_t reserved8 : 1;
|
||||
uint32_t reserved9 : 1;
|
||||
uint32_t reserved10 : 1;
|
||||
uint32_t reserved11 : 1;
|
||||
uint32_t reserved12 : 1;
|
||||
uint32_t reserved13 : 1;
|
||||
uint32_t reserved14 : 1;
|
||||
uint32_t reserved15 : 1;
|
||||
uint32_t reserved16 : 1;
|
||||
uint32_t reserved17 : 1;
|
||||
uint32_t reserved18 : 1;
|
||||
uint32_t reserved19 : 1;
|
||||
uint32_t reserved20 : 1;
|
||||
uint32_t reserved21 : 1;
|
||||
uint32_t reserved22 : 1;
|
||||
uint32_t reserved23 : 1;
|
||||
uint32_t reserved24 : 1;
|
||||
uint32_t reserved25 : 1;
|
||||
uint32_t reserved26 : 1;
|
||||
uint32_t reserved27 : 1;
|
||||
uint32_t reserved28 : 1;
|
||||
uint32_t reserved29 : 1;
|
||||
uint32_t reserved30 : 1;
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_wifipwr_fo : 1;
|
||||
uint32_t clk_coex_fo : 1;
|
||||
uint32_t clk_i2c_mst_fo : 1;
|
||||
uint32_t clk_lp_timer_fo : 1;
|
||||
uint32_t clk_fe_mem_fo : 1;
|
||||
uint32_t reserved5 : 1;
|
||||
uint32_t reserved6 : 1;
|
||||
uint32_t reserved7 : 1;
|
||||
uint32_t reserved8 : 1;
|
||||
uint32_t reserved9 : 1;
|
||||
uint32_t reserved10 : 1;
|
||||
uint32_t reserved11 : 1;
|
||||
uint32_t reserved12 : 1;
|
||||
uint32_t reserved13 : 1;
|
||||
uint32_t reserved14 : 1;
|
||||
uint32_t reserved15 : 1;
|
||||
uint32_t reserved16 : 1;
|
||||
uint32_t reserved17 : 1;
|
||||
uint32_t reserved18 : 1;
|
||||
uint32_t reserved19 : 1;
|
||||
uint32_t reserved20 : 1;
|
||||
uint32_t reserved21 : 1;
|
||||
uint32_t reserved22 : 1;
|
||||
uint32_t reserved23 : 1;
|
||||
uint32_t reserved24 : 1;
|
||||
uint32_t reserved25 : 1;
|
||||
uint32_t reserved26 : 1;
|
||||
uint32_t reserved27 : 1;
|
||||
uint32_t reserved28 : 1;
|
||||
uint32_t reserved29 : 1;
|
||||
uint32_t reserved30 : 1;
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf_force_on;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 16;
|
||||
uint32_t clk_wifipwr_st_map : 4;
|
||||
uint32_t clk_coex_st_map : 4;
|
||||
uint32_t clk_i2c_mst_st_map : 4;
|
||||
uint32_t clk_lp_apb_st_map : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf_power_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rst_wifipwr : 1;
|
||||
uint32_t rst_coex : 1;
|
||||
uint32_t rst_i2c_mst : 1;
|
||||
uint32_t rst_lp_timer : 1;
|
||||
uint32_t reserved4 : 1;
|
||||
uint32_t reserved5 : 1;
|
||||
uint32_t reserved6 : 1;
|
||||
uint32_t reserved7 : 1;
|
||||
uint32_t reserved8 : 1;
|
||||
uint32_t reserved9 : 1;
|
||||
uint32_t reserved10 : 1;
|
||||
uint32_t reserved11 : 1;
|
||||
uint32_t reserved12 : 1;
|
||||
uint32_t reserved13 : 1;
|
||||
uint32_t reserved14 : 1;
|
||||
uint32_t reserved15 : 1;
|
||||
uint32_t reserved16 : 1;
|
||||
uint32_t reserved17 : 1;
|
||||
uint32_t reserved18 : 1;
|
||||
uint32_t reserved19 : 1;
|
||||
uint32_t reserved20 : 1;
|
||||
uint32_t reserved21 : 1;
|
||||
uint32_t reserved22 : 1;
|
||||
uint32_t reserved23 : 1;
|
||||
uint32_t reserved24 : 1;
|
||||
uint32_t reserved25 : 1;
|
||||
uint32_t reserved26 : 1;
|
||||
uint32_t reserved27 : 1;
|
||||
uint32_t reserved28 : 1;
|
||||
uint32_t reserved29 : 1;
|
||||
uint32_t reserved30 : 1;
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rst_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t modem_pwr_tick_target : 6;
|
||||
uint32_t reserved6 : 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} tick_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dc_mem_mode : 3;
|
||||
uint32_t dc_mem_force : 1;
|
||||
uint32_t agc_mem_mode : 3;
|
||||
uint32_t agc_mem_force : 1;
|
||||
uint32_t pbus_mem_mode : 3;
|
||||
uint32_t pbus_mem_force : 1;
|
||||
uint32_t bc_mem_mode : 3;
|
||||
uint32_t bc_mem_force : 1;
|
||||
uint32_t i2c_mst_mem_mode : 3;
|
||||
uint32_t i2c_mst_mem_force : 1;
|
||||
uint32_t chan_freq_mem_mode : 3;
|
||||
uint32_t chan_freq_mem_force : 1;
|
||||
uint32_t reserved24 : 1;
|
||||
uint32_t reserved25 : 1;
|
||||
uint32_t reserved26 : 1;
|
||||
uint32_t reserved27 : 1;
|
||||
uint32_t reserved28 : 1;
|
||||
uint32_t reserved29 : 1;
|
||||
uint32_t reserved30 : 1;
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_conf;
|
||||
uint32_t mem_rf1_aux_ctrl;
|
||||
uint32_t mem_rf2_aux_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t chan_freq_mem_en : 1;
|
||||
uint32_t pbus_mem_en : 1;
|
||||
uint32_t agc_mem_en : 1;
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_mem_sel;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date : 28;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
/** Group: configure_register */
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t reserved_1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_test_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_lp_timer_sel_osc_slow: 1;
|
||||
uint32_t clk_lp_timer_sel_osc_fast: 1;
|
||||
uint32_t clk_lp_timer_sel_xtal: 1;
|
||||
uint32_t clk_lp_timer_sel_xtal32k: 1;
|
||||
uint32_t clk_lp_timer_div_num: 12;
|
||||
uint32_t reserved_16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_lp_timer_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_coex_lp_sel_osc_slow: 1;
|
||||
uint32_t clk_coex_lp_sel_osc_fast: 1;
|
||||
uint32_t clk_coex_lp_sel_xtal: 1;
|
||||
uint32_t clk_coex_lp_sel_xtal32k: 1;
|
||||
uint32_t clk_coex_lp_div_num: 12;
|
||||
uint32_t reserved_16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_coex_lp_clk_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_wifipwr_lp_sel_osc_slow: 1;
|
||||
uint32_t clk_wifipwr_lp_sel_osc_fast: 1;
|
||||
uint32_t clk_wifipwr_lp_sel_xtal: 1;
|
||||
uint32_t clk_wifipwr_lp_sel_xtal32k: 1;
|
||||
uint32_t clk_wifipwr_lp_div_num: 12;
|
||||
uint32_t reserved_16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_wifi_lp_clk_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_modem_aon_force: 2;
|
||||
uint32_t modem_pwr_clk_src_fo: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_modem_src_clk_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_modem_32k_sel: 2;
|
||||
uint32_t reserved_2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_modem_32k_clk_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_wifipwr_en: 1;
|
||||
uint32_t clk_coex_en: 1;
|
||||
uint32_t clk_i2c_mst_en: 1;
|
||||
uint32_t clk_lp_timer_en: 1;
|
||||
uint32_t reserved_4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_clk_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_wifipwr_fo: 1;
|
||||
uint32_t clk_coex_fo: 1;
|
||||
uint32_t clk_i2c_mst_fo: 1;
|
||||
uint32_t clk_lp_timer_fo: 1;
|
||||
uint32_t clk_fe_mem_fo: 1;
|
||||
uint32_t reserved_5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_clk_conf_force_on_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 16;
|
||||
uint32_t clk_wifipwr_st_map: 4;
|
||||
uint32_t clk_coex_st_map: 4;
|
||||
uint32_t clk_i2c_mst_st_map: 4;
|
||||
uint32_t clk_lp_apb_st_map: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_clk_conf_power_st_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t rst_wifipwr: 1;
|
||||
uint32_t rst_coex: 1;
|
||||
uint32_t rst_i2c_mst: 1;
|
||||
uint32_t rst_lp_timer: 1;
|
||||
uint32_t rst_dcmem: 1;
|
||||
uint32_t reserved_5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_rst_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t modem_pwr_tick_target: 6;
|
||||
uint32_t reserved_6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_tick_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t dc_mem_mode: 3;
|
||||
uint32_t dc_mem_force: 1;
|
||||
uint32_t agc_mem_mode: 3;
|
||||
uint32_t agc_mem_force: 1;
|
||||
uint32_t pbus_mem_mode: 3;
|
||||
uint32_t pbus_mem_force: 1;
|
||||
uint32_t bc_mem_mode: 3;
|
||||
uint32_t bc_mem_force: 1;
|
||||
uint32_t i2c_mst_mem_mode: 3;
|
||||
uint32_t i2c_mst_mem_force: 1;
|
||||
uint32_t chan_freq_mem_mode: 3;
|
||||
uint32_t chan_freq_mem_force: 1;
|
||||
uint32_t reserved_24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_mem_conf_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t modem_pwr_rf1_aux_ctrl: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_mem_rf1_aux_ctrl_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t modem_pwr_rf2_aux_ctrl: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_mem_rf2_aux_ctrl_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t chan_freq_mem_en: 1;
|
||||
uint32_t pbus_mem_en: 1;
|
||||
uint32_t agc_mem_en: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_apb_mem_sel_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t _dcmem_valid_0: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_dcmem_valid_0_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t _dcmem_valid_1: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_dcmem_valid_1_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t _dcmem_valid_2: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_dcmem_valid_2_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t _dcmem_valid_3: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_dcmem_valid_3_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t date: 28;
|
||||
uint32_t reserved_28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_lpcon_date_t;
|
||||
|
||||
typedef struct {
|
||||
volatile modem_lpcon_test_conf_t test_conf;
|
||||
volatile modem_lpcon_lp_timer_conf_t lp_timer_conf;
|
||||
volatile modem_lpcon_coex_lp_clk_conf_t coex_lp_clk_conf;
|
||||
volatile modem_lpcon_wifi_lp_clk_conf_t wifi_lp_clk_conf;
|
||||
volatile modem_lpcon_modem_src_clk_conf_t modem_src_clk_conf;
|
||||
volatile modem_lpcon_modem_32k_clk_conf_t modem_32k_clk_conf;
|
||||
volatile modem_lpcon_clk_conf_t clk_conf;
|
||||
volatile modem_lpcon_clk_conf_force_on_t clk_conf_force_on;
|
||||
volatile modem_lpcon_clk_conf_power_st_t clk_conf_power_st;
|
||||
volatile modem_lpcon_rst_conf_t rst_conf;
|
||||
volatile modem_lpcon_tick_conf_t tick_conf;
|
||||
volatile modem_lpcon_mem_conf_t mem_conf;
|
||||
volatile modem_lpcon_mem_rf1_aux_ctrl_t mem_rf1_aux_ctrl;
|
||||
volatile modem_lpcon_mem_rf2_aux_ctrl_t mem_rf2_aux_ctrl;
|
||||
volatile modem_lpcon_apb_mem_sel_t apb_mem_sel;
|
||||
volatile modem_lpcon_dcmem_valid_0_t dcmem_valid_0;
|
||||
volatile modem_lpcon_dcmem_valid_1_t dcmem_valid_1;
|
||||
volatile modem_lpcon_dcmem_valid_2_t dcmem_valid_2;
|
||||
volatile modem_lpcon_dcmem_valid_3_t dcmem_valid_3;
|
||||
volatile modem_lpcon_date_t date;
|
||||
} modem_lpcon_dev_t;
|
||||
|
||||
extern modem_lpcon_dev_t MODEM_LPCON;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(modem_lpcon_dev_t) == 0x40, "Invalid size of modem_lpcon_dev_t structure");
|
||||
_Static_assert(sizeof(modem_lpcon_dev_t) == 0x50, "Invalid size of modem_lpcon_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
@@ -10,164 +10,194 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en : 1;
|
||||
uint32_t modem_ant_force_sel_bt : 1;
|
||||
uint32_t modem_ant_force_sel_wifi : 1;
|
||||
uint32_t fpga_debug_clkswitch : 1;
|
||||
uint32_t fpga_debug_clk80 : 1;
|
||||
uint32_t fpga_debug_clk40 : 1;
|
||||
uint32_t fpga_debug_clk20 : 1;
|
||||
uint32_t fpga_debug_clk10 : 1;
|
||||
uint32_t modem_mem_mode_force : 1;
|
||||
uint32_t modem_dis_wifi6_force : 1;
|
||||
uint32_t reserved10 : 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} test_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t pwdet_sar_clock_ena : 1;
|
||||
uint32_t pwdet_clk_div_num : 8;
|
||||
uint32_t clk_tx_dac_inv_ena : 1;
|
||||
uint32_t clk_rx_adc_inv_ena : 1;
|
||||
uint32_t clk_pwdet_adc_inv_ena : 1;
|
||||
uint32_t clk_i2c_mst_sel_160m : 1;
|
||||
uint32_t reserved13 : 8;
|
||||
uint32_t clk_data_dump_mux : 1;
|
||||
uint32_t clk_etm_en : 1;
|
||||
uint32_t clk_zb_apb_en : 1;
|
||||
uint32_t clk_zbmac_en : 1;
|
||||
uint32_t clk_modem_sec_ecb_en : 1;
|
||||
uint32_t clk_modem_sec_ccm_en : 1;
|
||||
uint32_t clk_modem_sec_bah_en : 1;
|
||||
uint32_t clk_modem_sec_apb_en : 1;
|
||||
uint32_t clk_modem_sec_en : 1;
|
||||
uint32_t clk_ble_timer_en : 1;
|
||||
uint32_t clk_data_dump_en : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_wifibb_fo : 1;
|
||||
uint32_t clk_wifimac_fo : 1;
|
||||
uint32_t clk_wifi_apb_fo : 1;
|
||||
uint32_t clk_fe_fo : 1;
|
||||
uint32_t clk_fe_apb_fo : 1;
|
||||
uint32_t clk_btbb_fo : 1;
|
||||
uint32_t clk_btmac_fo : 1;
|
||||
uint32_t clk_bt_apb_fo : 1;
|
||||
uint32_t clk_zbmac_fo : 1;
|
||||
uint32_t clk_zbmac_apb_fo : 1;
|
||||
uint32_t reserved10 : 13;
|
||||
uint32_t reserved23 : 1;
|
||||
uint32_t reserved24 : 1;
|
||||
uint32_t reserved25 : 1;
|
||||
uint32_t reserved26 : 1;
|
||||
uint32_t reserved27 : 1;
|
||||
uint32_t clk_etm_fo : 1;
|
||||
uint32_t clk_modem_sec_fo : 1;
|
||||
uint32_t clk_ble_timer_fo : 1;
|
||||
uint32_t clk_data_dump_fo : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf_force_on;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 8;
|
||||
uint32_t clk_zb_st_map : 4;
|
||||
uint32_t clk_fe_st_map : 4;
|
||||
uint32_t clk_bt_st_map : 4;
|
||||
uint32_t clk_wifi_st_map : 4;
|
||||
uint32_t clk_modem_peri_st_map : 4;
|
||||
uint32_t clk_modem_apb_st_map : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf_power_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 1;
|
||||
uint32_t reserved1 : 1;
|
||||
uint32_t reserved2 : 1;
|
||||
uint32_t reserved3 : 1;
|
||||
uint32_t reserved4 : 1;
|
||||
uint32_t reserved5 : 1;
|
||||
uint32_t reserved6 : 1;
|
||||
uint32_t reserved7 : 1;
|
||||
uint32_t rst_wifibb : 1;
|
||||
uint32_t rst_wifimac : 1;
|
||||
uint32_t rst_fe_pwdet_adc : 1;
|
||||
uint32_t rst_fe_dac : 1;
|
||||
uint32_t rst_fe_adc : 1;
|
||||
uint32_t rst_fe_ahb : 1;
|
||||
uint32_t rst_fe : 1;
|
||||
uint32_t rst_btmac_apb : 1;
|
||||
uint32_t rst_btmac : 1;
|
||||
uint32_t rst_btbb_apb : 1;
|
||||
uint32_t rst_btbb : 1;
|
||||
uint32_t reserved19 : 3;
|
||||
uint32_t rst_etm : 1;
|
||||
uint32_t rst_zbmac_apb : 1;
|
||||
uint32_t rst_zbmac : 1;
|
||||
uint32_t rst_modem_ecb : 1;
|
||||
uint32_t rst_modem_ccm : 1;
|
||||
uint32_t rst_modem_bah : 1;
|
||||
uint32_t reserved28 : 1;
|
||||
uint32_t rst_modem_sec : 1;
|
||||
uint32_t rst_ble_timer : 1;
|
||||
uint32_t rst_data_dump : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_rst_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_wifibb_22m_en : 1;
|
||||
uint32_t clk_wifibb_40m_en : 1;
|
||||
uint32_t clk_wifibb_44m_en : 1;
|
||||
uint32_t clk_wifibb_80m_en : 1;
|
||||
uint32_t clk_wifibb_40x_en : 1;
|
||||
uint32_t clk_wifibb_80x_en : 1;
|
||||
uint32_t clk_wifibb_40x1_en : 1;
|
||||
uint32_t clk_wifibb_80x1_en : 1;
|
||||
uint32_t clk_wifibb_160x1_en : 1;
|
||||
uint32_t clk_wifimac_en : 1;
|
||||
uint32_t clk_wifi_apb_en : 1;
|
||||
uint32_t clk_fe_20m_en : 1;
|
||||
uint32_t clk_fe_40m_en : 1;
|
||||
uint32_t clk_fe_80m_en : 1;
|
||||
uint32_t clk_fe_160m_en : 1;
|
||||
uint32_t clk_fe_apb_en : 1;
|
||||
uint32_t clk_bt_apb_en : 1;
|
||||
uint32_t clk_btbb_en : 1;
|
||||
uint32_t clk_btmac_en : 1;
|
||||
uint32_t clk_fe_pwdet_adc_en : 1;
|
||||
uint32_t clk_fe_adc_en : 1;
|
||||
uint32_t clk_fe_dac_en : 1;
|
||||
uint32_t reserved22 : 1;
|
||||
uint32_t reserved23 : 1;
|
||||
uint32_t reserved24 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf1;
|
||||
uint32_t wifi_bb_cfg;
|
||||
uint32_t mem_rf1_conf;
|
||||
uint32_t mem_rf2_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date : 28;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
/** Group: configure_register */
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t modem_ant_force_sel_bt: 1;
|
||||
uint32_t modem_ant_force_sel_wifi: 1;
|
||||
uint32_t fpga_debug_clkswitch: 1;
|
||||
uint32_t fpga_debug_clk80: 1;
|
||||
uint32_t fpga_debug_clk40: 1;
|
||||
uint32_t fpga_debug_clk20: 1;
|
||||
uint32_t fpga_debug_clk10: 1;
|
||||
uint32_t modem_mem_mode_force: 1;
|
||||
uint32_t modem_dis_wifi6_force: 1;
|
||||
uint32_t reserved_10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_test_conf_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t pwdet_sar_clock_ena: 1;
|
||||
uint32_t pwdet_clk_div_num: 8;
|
||||
uint32_t clk_tx_dac_inv_ena: 1;
|
||||
uint32_t clk_rx_adc_inv_ena: 1;
|
||||
uint32_t clk_pwdet_adc_inv_ena: 1;
|
||||
uint32_t clk_i2c_mst_sel_160m: 1;
|
||||
uint32_t reserved_13: 8;
|
||||
uint32_t clk_data_dump_mux: 1;
|
||||
uint32_t clk_etm_en: 1;
|
||||
uint32_t clk_zb_apb_en: 1;
|
||||
uint32_t clk_zbmac_en: 1;
|
||||
uint32_t clk_modem_sec_ecb_en: 1;
|
||||
uint32_t clk_modem_sec_ccm_en: 1;
|
||||
uint32_t clk_modem_sec_bah_en: 1;
|
||||
uint32_t clk_modem_sec_apb_en: 1;
|
||||
uint32_t clk_modem_sec_en: 1;
|
||||
uint32_t clk_ble_timer_en: 1;
|
||||
uint32_t clk_data_dump_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_clk_conf_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_wifibb_fo: 1;
|
||||
uint32_t clk_wifimac_fo: 1;
|
||||
uint32_t clk_wifi_apb_fo: 1;
|
||||
uint32_t clk_fe_fo: 1;
|
||||
uint32_t clk_fe_apb_fo: 1;
|
||||
uint32_t clk_btbb_fo: 1;
|
||||
uint32_t clk_btmac_fo: 1;
|
||||
uint32_t clk_bt_apb_fo: 1;
|
||||
uint32_t clk_zbmac_fo: 1;
|
||||
uint32_t clk_zbmac_apb_fo: 1;
|
||||
uint32_t reserved_10: 18;
|
||||
uint32_t clk_etm_fo: 1;
|
||||
uint32_t clk_modem_sec_fo: 1;
|
||||
uint32_t clk_ble_timer_fo: 1;
|
||||
uint32_t clk_data_dump_fo: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_clk_conf_force_on_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 8;
|
||||
uint32_t clk_zb_st_map: 4;
|
||||
uint32_t clk_fe_st_map: 4;
|
||||
uint32_t clk_bt_st_map: 4;
|
||||
uint32_t clk_wifi_st_map: 4;
|
||||
uint32_t clk_modem_peri_st_map: 4;
|
||||
uint32_t clk_modem_apb_st_map: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_clk_conf_power_st_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 8;
|
||||
uint32_t rst_wifibb: 1;
|
||||
uint32_t rst_wifimac: 1;
|
||||
uint32_t rst_fe_pwdet_adc: 1;
|
||||
uint32_t rst_fe_dac: 1;
|
||||
uint32_t rst_fe_adc: 1;
|
||||
uint32_t rst_fe_ahb: 1;
|
||||
uint32_t rst_fe: 1;
|
||||
uint32_t rst_btmac_apb: 1;
|
||||
uint32_t rst_btmac: 1;
|
||||
uint32_t rst_btbb_apb: 1;
|
||||
uint32_t rst_btbb: 1;
|
||||
uint32_t reserved_19: 3;
|
||||
uint32_t rst_etm: 1;
|
||||
uint32_t rst_zbmac_apb: 1;
|
||||
uint32_t rst_zbmac: 1;
|
||||
uint32_t rst_modem_ecb: 1;
|
||||
uint32_t rst_modem_ccm: 1;
|
||||
uint32_t rst_modem_bah: 1;
|
||||
uint32_t reserved_28: 1;
|
||||
uint32_t rst_modem_sec: 1;
|
||||
uint32_t rst_ble_timer: 1;
|
||||
uint32_t rst_data_dump: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_modem_rst_conf_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t clk_wifibb_22m_en: 1;
|
||||
uint32_t clk_wifibb_40m_en: 1;
|
||||
uint32_t clk_wifibb_44m_en: 1;
|
||||
uint32_t clk_wifibb_80m_en: 1;
|
||||
uint32_t clk_wifibb_40x_en: 1;
|
||||
uint32_t clk_wifibb_80x_en: 1;
|
||||
uint32_t clk_wifibb_40x1_en: 1;
|
||||
uint32_t clk_wifibb_80x1_en: 1;
|
||||
uint32_t clk_wifibb_160x1_en: 1;
|
||||
uint32_t clk_wifimac_en: 1;
|
||||
uint32_t clk_wifi_apb_en: 1;
|
||||
uint32_t clk_fe_20m_en: 1;
|
||||
uint32_t clk_fe_40m_en: 1;
|
||||
uint32_t clk_fe_80m_en: 1;
|
||||
uint32_t clk_fe_160m_en: 1;
|
||||
uint32_t clk_fe_apb_en: 1;
|
||||
uint32_t clk_bt_apb_en: 1;
|
||||
uint32_t clk_btbb_en: 1;
|
||||
uint32_t clk_btmac_en: 1;
|
||||
uint32_t clk_fe_pwdet_adc_en: 1;
|
||||
uint32_t clk_fe_adc_en: 1;
|
||||
uint32_t clk_fe_dac_en: 1;
|
||||
uint32_t reserved_22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_clk_conf1_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t wifi_bb_cfg: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_wifi_bb_cfg_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t fe_cfg: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_fe_cfg_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t modem_rf1_mem_aux_ctrl: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_mem_rf1_conf_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t modem_rf2_mem_aux_ctrl: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_mem_rf2_conf_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t date: 28;
|
||||
uint32_t reserved_28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} modem_syscon_date_reg_t;
|
||||
|
||||
typedef struct {
|
||||
volatile modem_syscon_test_conf_reg_t test_conf;
|
||||
volatile modem_syscon_clk_conf_reg_t clk_conf;
|
||||
volatile modem_syscon_clk_conf_force_on_reg_t clk_conf_force_on;
|
||||
volatile modem_syscon_clk_conf_power_st_reg_t clk_conf_power_st;
|
||||
volatile modem_syscon_modem_rst_conf_reg_t modem_rst_conf;
|
||||
volatile modem_syscon_clk_conf1_reg_t clk_conf1;
|
||||
volatile modem_syscon_wifi_bb_cfg_reg_t wifi_bb_cfg;
|
||||
volatile modem_syscon_fe_cfg_reg_t fe_cfg;
|
||||
volatile modem_syscon_mem_rf1_conf_reg_t mem_rf1_conf;
|
||||
volatile modem_syscon_mem_rf2_conf_reg_t mem_rf2_conf;
|
||||
volatile modem_syscon_date_reg_t date;
|
||||
} modem_syscon_dev_t;
|
||||
|
||||
extern modem_syscon_dev_t MODEM_SYSCON;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(modem_syscon_dev_t) == 0x28, "Invalid size of modem_syscon_dev_t structure");
|
||||
_Static_assert(sizeof(modem_syscon_dev_t) == 0x2c, "Invalid size of modem_syscon_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -379,6 +379,10 @@ config SOC_GDMA_SUPPORT_SLEEP_RETENTION
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_AHB_GDMA_SUPPORT_PSRAM
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_ETM_GROUPS
|
||||
int
|
||||
default 1
|
||||
@@ -397,7 +401,7 @@ config SOC_GPIO_PORT
|
||||
|
||||
config SOC_GPIO_PIN_COUNT
|
||||
int
|
||||
default 25
|
||||
default 30
|
||||
|
||||
config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
|
||||
bool
|
||||
@@ -421,11 +425,11 @@ config SOC_LP_IO_CLOCK_IS_INDEPENDENT
|
||||
|
||||
config SOC_GPIO_IN_RANGE_MAX
|
||||
int
|
||||
default 24
|
||||
default 29
|
||||
|
||||
config SOC_GPIO_OUT_RANGE_MAX
|
||||
int
|
||||
default 24
|
||||
default 29
|
||||
|
||||
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
|
||||
bool
|
||||
@@ -441,7 +445,7 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
|
||||
|
||||
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
|
||||
hex
|
||||
default 0x1FFFF80
|
||||
default 0x3FFFFF80
|
||||
|
||||
config SOC_GPIO_SUPPORT_FORCE_HOLD
|
||||
bool
|
||||
@@ -791,6 +795,10 @@ config SOC_SPIRAM_XIP_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PSRAM_DMA_CAPABLE
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
|
||||
bool
|
||||
default y
|
||||
@@ -819,6 +827,10 @@ config SOC_SPI_MEM_SUPPORT_WRAP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
@@ -975,10 +987,26 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RECOVERY_BOOTLOADER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_BOOTLOADER_ANTI_ROLLBACK_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_APM_CTRL_FILTER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_APM_CPU_APM_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_APM_SUPPORT_CTRL_CFG_LOCK
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_CRYPTO_DPA_PROTECTION_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
@@ -1259,10 +1287,6 @@ config SOC_BLE_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_BLE_MESH_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_ESP_NIMBLE_CONTROLLER
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Number of paths for each supported APM controller */
|
||||
#define APM_CTRL_HP_APM_PATH_NUM (4)
|
||||
#define APM_CTRL_LP_APM_PATH_NUM (1)
|
||||
#define APM_CTRL_CPU_APM_PATH_NUM (2)
|
||||
/* Number of regions for each supported APM controller */
|
||||
#define APM_CTRL_HP_APM_REGION_NUM (16)
|
||||
#define APM_CTRL_LP_APM_REGION_NUM (4)
|
||||
#define APM_CTRL_CPU_APM_REGION_NUM (8)
|
||||
|
||||
/* Register offset for TEE mode control */
|
||||
#define APM_TEE_MODE_CTRL_OFFSET (0x04)
|
||||
/* Register offset between region bound address registers */
|
||||
#define APM_REGION_ADDR_OFFSET (0x0C)
|
||||
/* Register offset between region pms attribute registers */
|
||||
#define APM_REGION_ATTR_OFFSET (0x0C)
|
||||
/* Register offset between exception info registers */
|
||||
#define APM_EXCP_INFO_OFFSET (0x10)
|
||||
|
||||
/* Bit to clear exception status */
|
||||
#define APM_EXCP_STATUS_CLR_BIT (BIT(0))
|
||||
/* Bit to lock TEE mode */
|
||||
#define APM_TEE_MODE_LOCK_BIT (BIT(2))
|
||||
/* Bit to lock region pms attributes */
|
||||
#define APM_REGION_LOCK_BIT (BIT(11))
|
||||
|
||||
/* APM controller masters mask */
|
||||
#define APM_MASTER_MASK_ALL (0x018E0175U)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -40,6 +40,11 @@ typedef enum {
|
||||
GPIO_NUM_22 = 22, /*!< GPIO22, input and output */
|
||||
GPIO_NUM_23 = 23, /*!< GPIO23, input and output */
|
||||
GPIO_NUM_24 = 24, /*!< GPIO24, input and output */
|
||||
GPIO_NUM_25 = 25, /*!< GPIO25, input and output */
|
||||
GPIO_NUM_26 = 26, /*!< GPIO26, input and output */
|
||||
GPIO_NUM_27 = 27, /*!< GPIO27, input and output */
|
||||
GPIO_NUM_28 = 28, /*!< GPIO28, input and output */
|
||||
GPIO_NUM_29 = 29, /*!< GPIO29, input and output */
|
||||
GPIO_NUM_MAX,
|
||||
} gpio_num_t;
|
||||
|
||||
|
||||
@@ -10,8 +10,8 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define GPIO_MATRIX_CONST_ONE_INPUT (0x20)
|
||||
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x30)
|
||||
#define GPIO_MATRIX_CONST_ONE_INPUT (0x40)
|
||||
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x60)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -1,12 +1,11 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
// version date 2310090
|
||||
#define EXT_ADC_START_IDX 0
|
||||
#define LEDC_LS_SIG_OUT0_IDX 0
|
||||
#define LEDC_LS_SIG_OUT1_IDX 1
|
||||
@@ -141,6 +140,7 @@
|
||||
#define GPIO_TASK_MATRIX_OUT2_IDX 120
|
||||
#define GPIO_EVENT_MATRIX_IN3_IDX 121
|
||||
#define GPIO_TASK_MATRIX_OUT3_IDX 121
|
||||
#define SDIO_TOHOST_INT_OUT_IDX 124
|
||||
#define CLK_OUT_OUT1_IDX 126
|
||||
#define CLK_OUT_OUT2_IDX 127
|
||||
#define CLK_OUT_OUT3_IDX 128
|
||||
@@ -176,5 +176,5 @@
|
||||
#define MODEM_DIAG29_IDX 158
|
||||
#define MODEM_DIAG30_IDX 159
|
||||
#define MODEM_DIAG31_IDX 160
|
||||
|
||||
// version date 2310090
|
||||
#define SIG_GPIO_OUT_IDX 256
|
||||
|
||||
@@ -14,5 +14,3 @@
|
||||
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG)
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG INTERRUPT_CURRENT_CORE_INT_THRESH_REG
|
||||
|
||||
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -35,15 +35,15 @@ typedef enum {
|
||||
ETS_LP_WDT_INTR_SOURCE,
|
||||
ETS_LP_PERI_TIMEOUT_INTR_SOURCE,
|
||||
ETS_LP_APM_M0_INTR_SOURCE,
|
||||
ETS_FROM_CPU_INTR0_SOURCE,
|
||||
ETS_FROM_CPU_INTR1_SOURCE,
|
||||
ETS_FROM_CPU_INTR2_SOURCE,
|
||||
ETS_FROM_CPU_INTR3_SOURCE,
|
||||
ETS_CPU_INTR_FROM_CPU_0_SOURCE,
|
||||
ETS_CPU_INTR_FROM_CPU_1_SOURCE,
|
||||
ETS_CPU_INTR_FROM_CPU_2_SOURCE,
|
||||
ETS_CPU_INTR_FROM_CPU_3_SOURCE,
|
||||
ETS_ASSIST_DEBUG_INTR_SOURCE,
|
||||
ETS_TRACE_INTR_SOURCE,
|
||||
ETS_CACHE_INTR_SOURCE,
|
||||
ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
|
||||
ETS_GPIO_INTR_SOURCE,
|
||||
ETS_GPIO_INTERRUPT_PRO_SOURCE,
|
||||
ETS_GPIO_INTERRUPT_EXT_SOURCE,
|
||||
ETS_PAU_INTR_SOURCE,
|
||||
ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
|
||||
@@ -52,6 +52,8 @@ typedef enum {
|
||||
ETS_HP_APM_M1_INTR_SOURCE,
|
||||
ETS_HP_APM_M2_INTR_SOURCE,
|
||||
ETS_HP_APM_M3_INTR_SOURCE,
|
||||
ETS_CPU_APM_M0_INTR_SOURCE,
|
||||
ETS_CPU_APM_M1_INTR_SOURCE,
|
||||
ETS_MSPI_INTR_SOURCE,
|
||||
ETS_I2S0_INTR_SOURCE,
|
||||
ETS_UART0_INTR_SOURCE,
|
||||
@@ -62,16 +64,18 @@ typedef enum {
|
||||
ETS_I2C_EXT0_INTR_SOURCE,
|
||||
ETS_TG0_T0_INTR_SOURCE,
|
||||
ETS_TG0_T1_INTR_SOURCE,
|
||||
ETS_TG0_WDT_LEVEL_INTR_SOURCE,
|
||||
ETS_TG0_WDT_INTR_SOURCE,
|
||||
ETS_TG1_T0_INTR_SOURCE,
|
||||
ETS_TG1_T1_INTR_SOURCE,
|
||||
ETS_TG1_WDT_LEVEL_INTR_SOURCE,
|
||||
ETS_TG1_WDT_INTR_SOURCE,
|
||||
ETS_SYSTIMER_TARGET0_INTR_SOURCE,
|
||||
ETS_SYSTIMER_TARGET1_INTR_SOURCE,
|
||||
ETS_SYSTIMER_TARGET2_INTR_SOURCE,
|
||||
ETS_APB_ADC_INTR_SOURCE = 53,
|
||||
ETS_APB_ADC_INTR_SOURCE,
|
||||
ETS_TEMPERATURE_SENSOR_INTR_SOURCE = ETS_APB_ADC_INTR_SOURCE,
|
||||
ETS_DMA_IN_CH0_INTR_SOURCE = 54,
|
||||
ETS_SLC0_INTR_SOURCE,
|
||||
ETS_SLC1_INTR_SOURCE,
|
||||
ETS_DMA_IN_CH0_INTR_SOURCE,
|
||||
ETS_DMA_IN_CH1_INTR_SOURCE,
|
||||
ETS_DMA_OUT_CH0_INTR_SOURCE,
|
||||
ETS_DMA_OUT_CH1_INTR_SOURCE,
|
||||
|
||||
@@ -1,10 +1,11 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#define PMU_ICG_APB_ENA_SEC 0
|
||||
#define PMU_ICG_APB_ENA_GDMA 1
|
||||
#define PMU_ICG_APB_ENA_SPI2 2
|
||||
@@ -35,6 +36,7 @@
|
||||
#define PMU_ICG_FUNC_ENA_I2S_TX 7
|
||||
#define PMU_ICG_FUNC_ENA_REGDMA 8
|
||||
#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10
|
||||
#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11
|
||||
#define PMU_ICG_FUNC_ENA_TSENS 12
|
||||
#define PMU_ICG_FUNC_ENA_TG1 13
|
||||
#define PMU_ICG_FUNC_ENA_TG0 14
|
||||
|
||||
@@ -22,9 +22,7 @@
|
||||
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C61
|
||||
#define REG_TIMG_BASE(i) (DR_REG_TIMG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
|
||||
#define REG_SPI_MEM_BASE(i) (DR_REG_MSPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
|
||||
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C61
|
||||
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C61
|
||||
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE
|
||||
|
||||
//Registers Operation {{
|
||||
#define ETS_UNCACHED_ADDR(addr) (addr)
|
||||
|
||||
@@ -152,6 +152,7 @@
|
||||
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 2
|
||||
#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
|
||||
#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
|
||||
#define SOC_AHB_GDMA_SUPPORT_PSRAM 1
|
||||
|
||||
/*-------------------------- ETM CAPS --------------------------------------*/
|
||||
#define SOC_ETM_GROUPS 1U // Number of ETM groups
|
||||
@@ -161,7 +162,7 @@
|
||||
/*-------------------------- GPIO CAPS ---------------------------------------*/
|
||||
// ESP32-C61 has 1 GPIO peripheral
|
||||
#define SOC_GPIO_PORT 1U
|
||||
#define SOC_GPIO_PIN_COUNT 25
|
||||
#define SOC_GPIO_PIN_COUNT 30
|
||||
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
|
||||
#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
|
||||
|
||||
@@ -178,16 +179,16 @@
|
||||
#define SOC_GPIO_VALID_GPIO_MASK ((1ULL<<SOC_GPIO_PIN_COUNT) - 1)
|
||||
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
|
||||
|
||||
#define SOC_GPIO_IN_RANGE_MAX 24
|
||||
#define SOC_GPIO_OUT_RANGE_MAX 24
|
||||
#define SOC_GPIO_IN_RANGE_MAX 29
|
||||
#define SOC_GPIO_OUT_RANGE_MAX 29
|
||||
|
||||
// GPIO0~6 on ESP32C61 can support chip deep sleep wakeup
|
||||
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
|
||||
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
|
||||
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (7)
|
||||
|
||||
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_24)
|
||||
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x1FFFF80ULL
|
||||
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_29)
|
||||
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x3FFFFF80ULL
|
||||
|
||||
// Support to force hold all IOs
|
||||
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
|
||||
@@ -335,6 +336,7 @@
|
||||
|
||||
/*-------------------------- SPIRAM CAPS ----------------------------------------*/
|
||||
#define SOC_SPIRAM_XIP_SUPPORTED 1
|
||||
#define SOC_PSRAM_DMA_CAPABLE 1
|
||||
|
||||
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
|
||||
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
|
||||
@@ -344,6 +346,7 @@
|
||||
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_WRAP (1)
|
||||
#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1)
|
||||
|
||||
#define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
|
||||
#define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
|
||||
@@ -400,8 +403,16 @@
|
||||
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
|
||||
#define SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND 1
|
||||
|
||||
/*------------------------Bootloader CAPS---------------------------------*/
|
||||
/* Support Recovery Bootloader */
|
||||
#define SOC_RECOVERY_BOOTLOADER_SUPPORTED (1)
|
||||
/* Support Anti-rollback */
|
||||
#define SOC_BOOTLOADER_ANTI_ROLLBACK_SUPPORTED (1)
|
||||
|
||||
/*-------------------------- APM CAPS ----------------------------------------*/
|
||||
#define SOC_APM_CTRL_FILTER_SUPPORTED 1 /*!< Support for APM control filter */
|
||||
#define SOC_APM_CPU_APM_SUPPORTED 1 /*!< Support for CPU APM control filter */
|
||||
#define SOC_APM_SUPPORT_CTRL_CFG_LOCK 1 /*!< Support for APM controller configuration lock */
|
||||
|
||||
/*------------------------ Anti DPA (Security) CAPS --------------------------*/
|
||||
#define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1
|
||||
@@ -510,9 +521,9 @@
|
||||
#define SOC_WIFI_MAC_VERSION_NUM (3) /*!< Wi-Fi MAC version num is 3 */
|
||||
#define SOC_WIFI_NAN_SUPPORT (1) /*!< Support WIFI Aware (NAN) */
|
||||
|
||||
/*---------------------------------- Bluetooth CAPS ----------------------------------*/
|
||||
// /*---------------------------------- Bluetooth CAPS ----------------------------------*/
|
||||
#define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */
|
||||
#define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */
|
||||
// #define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */
|
||||
#define SOC_ESP_NIMBLE_CONTROLLER (1) /*!< Support BLE EMBEDDED controller V1 */
|
||||
#define SOC_BLE_50_SUPPORTED (1) /*!< Support Bluetooth 5.0 */
|
||||
#define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1) /*!< Support BLE device privacy mode */
|
||||
|
||||
@@ -8,10 +8,10 @@
|
||||
#include "soc/interrupts.h"
|
||||
|
||||
// Maps misc system interrupt to hardware interrupt names
|
||||
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_FROM_CPU_INTR0_SOURCE
|
||||
#define SYS_CPU_INTR_FROM_CPU_1_SOURCE ETS_FROM_CPU_INTR1_SOURCE
|
||||
#define SYS_CPU_INTR_FROM_CPU_2_SOURCE ETS_FROM_CPU_INTR2_SOURCE
|
||||
#define SYS_CPU_INTR_FROM_CPU_3_SOURCE ETS_FROM_CPU_INTR3_SOURCE
|
||||
#define SYS_CPU_INTR_FROM_CPU_0_SOURCE ETS_CPU_INTR_FROM_CPU_0_SOURCE
|
||||
#define SYS_CPU_INTR_FROM_CPU_1_SOURCE ETS_CPU_INTR_FROM_CPU_1_SOURCE
|
||||
#define SYS_CPU_INTR_FROM_CPU_2_SOURCE ETS_CPU_INTR_FROM_CPU_2_SOURCE
|
||||
#define SYS_CPU_INTR_FROM_CPU_3_SOURCE ETS_CPU_INTR_FROM_CPU_3_SOURCE
|
||||
|
||||
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
|
||||
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_LEVEL_INTR_SOURCE
|
||||
#define SYS_TG0_WDT_INTR_SOURCE ETS_TG0_WDT_INTR_SOURCE
|
||||
#define SYS_TG1_WDT_INTR_SOURCE ETS_TG1_WDT_INTR_SOURCE
|
||||
|
||||
Reference in New Issue
Block a user