diff --git a/components/efuse/esp32p4/esp_efuse_table_v3.0.c b/components/efuse/esp32p4/esp_efuse_table_v3.0.c new file mode 100644 index 00000000000..7fd5fab35e3 --- /dev/null +++ b/components/efuse/esp32p4/esp_efuse_table_v3.0.c @@ -0,0 +1,1679 @@ +/* + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include "esp_efuse.h" +#include +#include "esp_efuse_table_v3.0.h" + +// md5_digest_table 546834ca62bf5546bc26447554d7a099 +// This file was generated from the file esp_efuse_table_v3.0.csv. DO NOT CHANGE THIS FILE MANUALLY. +// If you want to change some fields, you need to change esp_efuse_table_v3.0.csv file +// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. +// To show efuse_table run the command 'show_efuse_table'. + +static const esp_efuse_desc_t WR_DIS[] = { + {EFUSE_BLK0, 0, 32}, // [] Disable programming of individual eFuses, +}; + +static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { + {EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS, +}; + +static const esp_efuse_desc_t WR_DIS_KM_RND_SWITCH_CYCLE[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_RND_SWITCH_CYCLE, +}; + +static const esp_efuse_desc_t WR_DIS_KM_DEPLOY_ONLY_ONCE[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_DEPLOY_ONLY_ONCE, +}; + +static const esp_efuse_desc_t WR_DIS_FORCE_USE_KEY_MANAGER_KEY[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of FORCE_USE_KEY_MANAGER_KEY, +}; + +static const esp_efuse_desc_t WR_DIS_FORCE_DISABLE_SW_INIT_KEY[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of FORCE_DISABLE_SW_INIT_KEY, +}; + +static const esp_efuse_desc_t WR_DIS_KM_XTS_KEY_LENGTH_256[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_XTS_KEY_LENGTH_256, +}; + +static const esp_efuse_desc_t WR_DIS_KM_DEPLOY_ONLY_ONCE_H[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_DEPLOY_ONLY_ONCE_H, +}; + +static const esp_efuse_desc_t WR_DIS_FORCE_USE_KEY_MANAGER_KEY_H[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of FORCE_USE_KEY_MANAGER_KEY_H, +}; + +static const esp_efuse_desc_t WR_DIS_LOCK_KM_KEY[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of LOCK_KM_KEY, +}; + +static const esp_efuse_desc_t WR_DIS_KM_DISABLE_DEPLOY_MODE_H[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_DISABLE_DEPLOY_MODE_H, +}; + +static const esp_efuse_desc_t WR_DIS_KM_DISABLE_DEPLOY_MODE[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_DISABLE_DEPLOY_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_FORCE_DOWNLOAD, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_TWAI, +}; + +static const esp_efuse_desc_t WR_DIS_JTAG_SEL_ENABLE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of JTAG_SEL_ENABLE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_PAD_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_PAD_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT, +}; + +static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of WDT_DELAY_SEL, +}; + +static const esp_efuse_desc_t WR_DIS_HYS_EN_PAD[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of HYS_EN_PAD, +}; + +static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_0[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of PXA0_TIEH_SEL_0, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_WDT[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_WDT, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_SWD[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_SWD, +}; + +static const esp_efuse_desc_t WR_DIS_PVT_GLITCH_EN[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of PVT_GLITCH_EN, +}; + +static const esp_efuse_desc_t WR_DIS_PVT_GLITCH_MODE[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of PVT_GLITCH_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = { + {EFUSE_BLK0, 4, 1}, // [] wr_dis of SPI_BOOT_CRYPT_CNT, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { + {EFUSE_BLK0, 5, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE0, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { + {EFUSE_BLK0, 6, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE1, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { + {EFUSE_BLK0, 7, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE2, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_0[] = { + {EFUSE_BLK0, 8, 1}, // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_0_H[] = { + {EFUSE_BLK0, 8, 1}, // [] wr_dis of KEY_PURPOSE_0_H, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_1[] = { + {EFUSE_BLK0, 9, 1}, // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_1_H[] = { + {EFUSE_BLK0, 9, 1}, // [] wr_dis of KEY_PURPOSE_1_H, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_2[] = { + {EFUSE_BLK0, 10, 1}, // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_2_H[] = { + {EFUSE_BLK0, 10, 1}, // [] wr_dis of KEY_PURPOSE_2_H, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_3[] = { + {EFUSE_BLK0, 11, 1}, // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_3_H[] = { + {EFUSE_BLK0, 11, 1}, // [] wr_dis of KEY_PURPOSE_3_H, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_4[] = { + {EFUSE_BLK0, 12, 1}, // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_4_H[] = { + {EFUSE_BLK0, 12, 1}, // [] wr_dis of KEY_PURPOSE_4_H, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = { + {EFUSE_BLK0, 13, 1}, // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5, +}; + +static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5_H[] = { + {EFUSE_BLK0, 13, 1}, // [] wr_dis of KEY_PURPOSE_5_H, +}; + +static const esp_efuse_desc_t WR_DIS_ECC_FORCE_CONST_TIME[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of ECC_FORCE_CONST_TIME, +}; + +static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of SEC_DPA_LEVEL, +}; + +static const esp_efuse_desc_t WR_DIS_XTS_DPA_CLK_ENABLE[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of XTS_DPA_CLK_ENABLE, +}; + +static const esp_efuse_desc_t WR_DIS_XTS_DPA_PSEUDO_LEVEL[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of XTS_DPA_PSEUDO_LEVEL, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { + {EFUSE_BLK0, 15, 1}, // [] wr_dis of SECURE_BOOT_EN, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + {EFUSE_BLK0, 16, 1}, // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE, +}; + +static const esp_efuse_desc_t WR_DIS_HP_PWR_SRC_SEL[] = { + {EFUSE_BLK0, 17, 1}, // [] wr_dis of HP_PWR_SRC_SEL, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_ECC_EN[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_ECC_EN, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TPUW, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DIRECT_BOOT[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DIRECT_BOOT, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of ENABLE_SECURITY_DOWNLOAD, +}; + +static const esp_efuse_desc_t WR_DIS_UART_PRINT_CONTROL[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of UART_PRINT_CONTROL, +}; + +static const esp_efuse_desc_t WR_DIS_FORCE_SEND_RESUME[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FORCE_SEND_RESUME, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE, +}; + +static const esp_efuse_desc_t WR_DIS_HUK_GEN_STATE[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of HUK_GEN_STATE, +}; + +static const esp_efuse_desc_t WR_DIS_BLK1[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLOCK1, +}; + +static const esp_efuse_desc_t WR_DIS_MAC[] = { + {EFUSE_BLK0, 20, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR_LO[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR_LO, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR, +}; + +static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MAJOR, +}; + +static const esp_efuse_desc_t WR_DIS_PSRAM_CAP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_CAP, +}; + +static const esp_efuse_desc_t WR_DIS_TEMP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of TEMP, +}; + +static const esp_efuse_desc_t WR_DIS_PSRAM_VENDOR[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_VENDOR, +}; + +static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2, +}; + +static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR_HI[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR_HI, +}; + +static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = { + {EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA, +}; + +static const esp_efuse_desc_t WR_DIS_CUSTOM_MAC[] = { + {EFUSE_BLK0, 22, 1}, // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY0[] = { + {EFUSE_BLK0, 23, 1}, // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY1[] = { + {EFUSE_BLK0, 24, 1}, // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY2[] = { + {EFUSE_BLK0, 25, 1}, // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY3[] = { + {EFUSE_BLK0, 26, 1}, // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY4[] = { + {EFUSE_BLK0, 27, 1}, // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_KEY5[] = { + {EFUSE_BLK0, 28, 1}, // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5, +}; + +static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = { + {EFUSE_BLK0, 29, 1}, // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2, +}; + +static const esp_efuse_desc_t WR_DIS_USB_DEVICE_EXCHG_PINS[] = { + {EFUSE_BLK0, 29, 1}, // [] wr_dis of USB_DEVICE_EXCHG_PINS, +}; + +static const esp_efuse_desc_t WR_DIS_USB_OTG11_EXCHG_PINS[] = { + {EFUSE_BLK0, 29, 1}, // [] wr_dis of USB_OTG11_EXCHG_PINS, +}; + +static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = { + {EFUSE_BLK0, 31, 1}, // [] wr_dis of SOFT_DIS_JTAG, +}; + +static const esp_efuse_desc_t RD_DIS[] = { + {EFUSE_BLK0, 32, 7}, // [] Disable reading from BlOCK4-10, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY0[] = { + {EFUSE_BLK0, 32, 1}, // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY1[] = { + {EFUSE_BLK0, 33, 1}, // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY2[] = { + {EFUSE_BLK0, 34, 1}, // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY3[] = { + {EFUSE_BLK0, 35, 1}, // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY4[] = { + {EFUSE_BLK0, 36, 1}, // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_KEY5[] = { + {EFUSE_BLK0, 37, 1}, // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5, +}; + +static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = { + {EFUSE_BLK0, 38, 1}, // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2, +}; + +static const esp_efuse_desc_t RD_DIS_USB_DEVICE_EXCHG_PINS[] = { + {EFUSE_BLK0, 38, 1}, // [] rd_dis of USB_DEVICE_EXCHG_PINS, +}; + +static const esp_efuse_desc_t RD_DIS_USB_OTG11_EXCHG_PINS[] = { + {EFUSE_BLK0, 38, 1}, // [] rd_dis of USB_OTG11_EXCHG_PINS, +}; + +static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1[] = { + {EFUSE_BLK0, 39, 2}, // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled, +}; + +static const esp_efuse_desc_t DIS_USB_JTAG[] = { + {EFUSE_BLK0, 41, 1}, // [] Set this bit to disable function of usb switch to jtag in module of usb device, +}; + +static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2[] = { + {EFUSE_BLK0, 42, 1}, // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled, +}; + +static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { + {EFUSE_BLK0, 44, 1}, // [] Set this bit to disable the function that forces chip into download mode, +}; + +static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = { + {EFUSE_BLK0, 45, 1}, // [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download, +}; + +static const esp_efuse_desc_t DIS_TWAI[] = { + {EFUSE_BLK0, 46, 1}, // [] Set this bit to disable TWAI function, +}; + +static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = { + {EFUSE_BLK0, 47, 1}, // [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0, +}; + +static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { + {EFUSE_BLK0, 48, 3}, // [] Set odd bits to disable JTAG in the soft way. JTAG can be enabled in HMAC module, +}; + +static const esp_efuse_desc_t DIS_PAD_JTAG[] = { + {EFUSE_BLK0, 51, 1}, // [] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently, +}; + +static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + {EFUSE_BLK0, 52, 1}, // [] Set this bit to disable flash manual encrypt function (except in SPI boot mode), +}; + +static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6[] = { + {EFUSE_BLK0, 53, 4}, // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled, +}; + +static const esp_efuse_desc_t USB_PHY_SEL[] = { + {EFUSE_BLK0, 57, 1}, // [] 0: intphy(gpio24/25) <---> usb_device 1: intphy(26/27) <---> usb_otg11.1: intphy(gpio26/27) <---> usb_device 1: intphy(24/25) <---> usb_otg11, +}; + +static const esp_efuse_desc_t HUK_GEN_STATE[] = { + {EFUSE_BLK0, 58, 5}, // [] Set the bits to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid, +}; + +static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7[] = { + {EFUSE_BLK0, 63, 1}, // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled, +}; + +static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10[] = { + {EFUSE_BLK0, 64, 3}, // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled, +}; + +static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11[] = { + {EFUSE_BLK0, 67, 1}, // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled, +}; + +static const esp_efuse_desc_t KM_RND_SWITCH_CYCLE[] = { + {EFUSE_BLK0, 68, 1}, // [] Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles, +}; + +static const esp_efuse_desc_t KM_DEPLOY_ONLY_ONCE[] = { + {EFUSE_BLK0, 69, 4}, // [] EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: {EFUSE_KM_DEPLOY_ONLY_ONCE_H; EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram, + {EFUSE_BLK0, 118, 1}, // [] EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: {EFUSE_KM_DEPLOY_ONLY_ONCE_H; EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram, +}; + +static const esp_efuse_desc_t FORCE_USE_KEY_MANAGER_KEY[] = { + {EFUSE_BLK0, 73, 4}, // [] EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H; EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram, + {EFUSE_BLK0, 119, 1}, // [] EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H; EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram, +}; + +static const esp_efuse_desc_t FORCE_DISABLE_SW_INIT_KEY[] = { + {EFUSE_BLK0, 77, 1}, // [] Set this bit to disable software written init key; and force use efuse_init_key, +}; + +static const esp_efuse_desc_t KM_XTS_KEY_LENGTH_256[] = { + {EFUSE_BLK0, 78, 1}, // [] Set this bit to config flash encryption xts-512 key; else use xts-256 key when using the key manager, +}; + +static const esp_efuse_desc_t ECC_FORCE_CONST_TIME[] = { + {EFUSE_BLK0, 79, 1}, // [] Set this bit to permanently turn on ECC const-time mode, +}; + +static const esp_efuse_desc_t WDT_DELAY_SEL[] = { + {EFUSE_BLK0, 81, 1}, // [] Select lp wdt timeout threshold at startup = initial timeout value * (2 ^ (EFUSE_WDT_DELAY_SEL + 1)), +}; + +static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { + {EFUSE_BLK0, 82, 3}, // [] Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = { + {EFUSE_BLK0, 85, 1}, // [] Revoke 1st secure boot key, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = { + {EFUSE_BLK0, 86, 1}, // [] Revoke 2nd secure boot key, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = { + {EFUSE_BLK0, 87, 1}, // [] Revoke 3rd secure boot key, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_0[] = { + {EFUSE_BLK0, 88, 4}, // [KEY0_PURPOSE] Purpose of Key0, + {EFUSE_BLK0, 155, 1}, // [] Purpose of Key0. The 5-th bit, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_1[] = { + {EFUSE_BLK0, 92, 4}, // [KEY1_PURPOSE] Purpose of Key1, + {EFUSE_BLK0, 156, 1}, // [] Purpose of Key1. The 5-th bit, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_2[] = { + {EFUSE_BLK0, 96, 4}, // [KEY2_PURPOSE] Purpose of Key2, + {EFUSE_BLK0, 157, 1}, // [] Purpose of Key2. The 5-th bit, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_3[] = { + {EFUSE_BLK0, 100, 4}, // [KEY3_PURPOSE] Purpose of Key3, + {EFUSE_BLK0, 158, 1}, // [] Purpose of Key3. The 5-th bit, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_4[] = { + {EFUSE_BLK0, 104, 4}, // [KEY4_PURPOSE] Purpose of Key4, + {EFUSE_BLK0, 159, 1}, // [] Purpose of Key4. The 5-th bit, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_5[] = { + {EFUSE_BLK0, 108, 4}, // [KEY5_PURPOSE] Purpose of Key5, + {EFUSE_BLK0, 164, 1}, // [] Purpose of Key5. The 5-th bit, +}; + +static const esp_efuse_desc_t SEC_DPA_LEVEL[] = { + {EFUSE_BLK0, 112, 2}, // [] Configures the clock random divide mode to determine the dpa secure level, +}; + +static const esp_efuse_desc_t XTS_DPA_CLK_ENABLE[] = { + {EFUSE_BLK0, 115, 1}, // [] Sets this bit to enable xts clock anti-dpa attack function, +}; + +static const esp_efuse_desc_t SECURE_BOOT_EN[] = { + {EFUSE_BLK0, 116, 1}, // [] Set this bit to enable secure boot, +}; + +static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + {EFUSE_BLK0, 117, 1}, // [] Set this bit to enable revoking aggressive secure boot, +}; + +static const esp_efuse_desc_t FLASH_ECC_EN[] = { + {EFUSE_BLK0, 122, 1}, // [] Set this bit to enable ECC for flash boot, +}; + +static const esp_efuse_desc_t DIS_USB_OTG_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 123, 1}, // [] Set this bit to disable download via USB-OTG, +}; + +static const esp_efuse_desc_t FLASH_TPUW[] = { + {EFUSE_BLK0, 124, 4}, // [] Configures flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the configurable value. Otherwise; the waiting time is 30, +}; + +static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 128, 1}, // [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 4; 5; 6; 7), +}; + +static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { + {EFUSE_BLK0, 129, 1}, // [] Set this bit to disable direct boot mode, +}; + +static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + {EFUSE_BLK0, 130, 1}, // [] Set this bit to disable USB-Serial-JTAG print during rom boot, +}; + +static const esp_efuse_desc_t LOCK_KM_KEY[] = { + {EFUSE_BLK0, 131, 1}, // [] set this bit to lock the key manager key after deploy, +}; + +static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 132, 1}, // [] Set this bit to disable the USB-Serial-JTAG download function, +}; + +static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { + {EFUSE_BLK0, 133, 1}, // [] Set this bit to enable security download mode, +}; + +static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { + {EFUSE_BLK0, 134, 2}, // [] Set the type of UART printing; 00: force enable printing; 01: enable printing when GPIO8 is reset at low level; 10: enable printing when GPIO8 is reset at high level; 11: force disable printing, +}; + +static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { + {EFUSE_BLK0, 136, 1}, // [] Set this bit to force ROM code to send a resume command during SPI boot, +}; + +static const esp_efuse_desc_t SECURE_VERSION[] = { + {EFUSE_BLK0, 137, 16}, // [] Secure version used by ESP-IDF anti-rollback feature, +}; + +static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = { + {EFUSE_BLK0, 153, 1}, // [] Represents whether secure boot do fast verification on wake is disabled. 0: enabled 1: disabled, +}; + +static const esp_efuse_desc_t HYS_EN_PAD[] = { + {EFUSE_BLK0, 154, 1}, // [] Set bits to enable hysteresis function of PAD0~27, +}; + +static const esp_efuse_desc_t PXA0_TIEH_SEL_0[] = { + {EFUSE_BLK0, 160, 2}, // [] Output LDO VO0 tieh source select. 0: 1'b1 1: sdmmc1 2: reg 3:sdmmc0, +}; + +static const esp_efuse_desc_t PVT_GLITCH_EN[] = { + {EFUSE_BLK0, 162, 1}, // [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable, +}; + +static const esp_efuse_desc_t KM_DISABLE_DEPLOY_MODE[] = { + {EFUSE_BLK0, 168, 4}, // [] EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H; EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set each bit to control whether corresponding key's deploy mode of new value deployment is disabled. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram, + {EFUSE_BLK0, 167, 1}, // [] EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H; EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set each bit to control whether corresponding key's deploy mode of new value deployment is disabled. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram, +}; + +static const esp_efuse_desc_t XTS_DPA_PSEUDO_LEVEL[] = { + {EFUSE_BLK0, 176, 2}, // [] Sets this bit to control the xts pseudo-round anti-dpa attack function. 0: controlled by register. 1-3: the higher the value is; the more pseudo-rounds are inserted to the xts-aes calculation, +}; + +static const esp_efuse_desc_t HP_PWR_SRC_SEL[] = { + {EFUSE_BLK0, 178, 1}, // [] HP system power source select. 0:LDO 1: DCDC, +}; + +static const esp_efuse_desc_t SECURE_BOOT_SHA384_EN[] = { + {EFUSE_BLK0, 179, 1}, // [] Represents whether secure boot using SHA-384 is enabled. 0: disable 1: enable, +}; + +static const esp_efuse_desc_t DIS_WDT[] = { + {EFUSE_BLK0, 180, 1}, // [] Set this bit to disable watch dog, +}; + +static const esp_efuse_desc_t DIS_SWD[] = { + {EFUSE_BLK0, 181, 1}, // [] Set bit to disable super-watchdog, +}; + +static const esp_efuse_desc_t PVT_GLITCH_MODE[] = { + {EFUSE_BLK0, 182, 2}, // [] Use to configure glitch mode, +}; + +static const esp_efuse_desc_t MAC[] = { + {EFUSE_BLK1, 40, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 32, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 24, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 16, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 8, 8}, // [MAC_FACTORY] MAC address, + {EFUSE_BLK1, 0, 8}, // [MAC_FACTORY] MAC address, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { + {EFUSE_BLK1, 64, 4}, // [] Minor chip version, +}; + +static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 68, 2}, // [] Major chip version (lower 2 bits), + {EFUSE_BLK1, 87, 1}, // [] Major chip version (MSB), +}; + +static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = { + {EFUSE_BLK1, 70, 1}, // [] Disables check of wafer version major, +}; + +static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = { + {EFUSE_BLK1, 71, 1}, // [] Disables check of blk version major, +}; + +static const esp_efuse_desc_t BLK_VERSION_MINOR[] = { + {EFUSE_BLK1, 72, 3}, // [] BLK_VERSION_MINOR of BLOCK2, +}; + +static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { + {EFUSE_BLK1, 75, 2}, // [] BLK_VERSION_MAJOR of BLOCK2, +}; + +static const esp_efuse_desc_t PSRAM_CAP[] = { + {EFUSE_BLK1, 77, 3}, // [] PSRAM capacity, +}; + +static const esp_efuse_desc_t TEMP[] = { + {EFUSE_BLK1, 80, 2}, // [] Operating temperature of the ESP chip, +}; + +static const esp_efuse_desc_t PSRAM_VENDOR[] = { + {EFUSE_BLK1, 82, 2}, // [] PSRAM vendor, +}; + +static const esp_efuse_desc_t PKG_VERSION[] = { + {EFUSE_BLK1, 84, 3}, // [] Package version, +}; + +static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, +}; + +static const esp_efuse_desc_t USER_DATA[] = { + {EFUSE_BLK3, 0, 256}, // [BLOCK_USR_DATA] User data, +}; + +static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = { + {EFUSE_BLK3, 200, 48}, // [MAC_CUSTOM CUSTOM_MAC] Custom MAC, +}; + +static const esp_efuse_desc_t KEY0[] = { + {EFUSE_BLK4, 0, 256}, // [BLOCK_KEY0] Key0 or user data, +}; + +static const esp_efuse_desc_t KEY1[] = { + {EFUSE_BLK5, 0, 256}, // [BLOCK_KEY1] Key1 or user data, +}; + +static const esp_efuse_desc_t KEY2[] = { + {EFUSE_BLK6, 0, 256}, // [BLOCK_KEY2] Key2 or user data, +}; + +static const esp_efuse_desc_t KEY3[] = { + {EFUSE_BLK7, 0, 256}, // [BLOCK_KEY3] Key3 or user data, +}; + +static const esp_efuse_desc_t KEY4[] = { + {EFUSE_BLK8, 0, 256}, // [BLOCK_KEY4] Key4 or user data, +}; + +static const esp_efuse_desc_t KEY5[] = { + {EFUSE_BLK9, 0, 256}, // [BLOCK_KEY5] Key5 or user data, +}; + +static const esp_efuse_desc_t USB_DEVICE_EXCHG_PINS[] = { + {EFUSE_BLK10, 228, 1}, // [] Enable usb device exchange pins of D+ and D-, +}; + +static const esp_efuse_desc_t USB_OTG11_EXCHG_PINS[] = { + {EFUSE_BLK10, 229, 1}, // [] Enable usb otg11 exchange pins of D+ and D-, +}; + + + + + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = { + &WR_DIS[0], // [] Disable programming of individual eFuses + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { + &WR_DIS_RD_DIS[0], // [] wr_dis of RD_DIS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[] = { + &WR_DIS_KM_RND_SWITCH_CYCLE[0], // [] wr_dis of KM_RND_SWITCH_CYCLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[] = { + &WR_DIS_KM_DEPLOY_ONLY_ONCE[0], // [] wr_dis of KM_DEPLOY_ONLY_ONCE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[] = { + &WR_DIS_FORCE_USE_KEY_MANAGER_KEY[0], // [] wr_dis of FORCE_USE_KEY_MANAGER_KEY + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[] = { + &WR_DIS_FORCE_DISABLE_SW_INIT_KEY[0], // [] wr_dis of FORCE_DISABLE_SW_INIT_KEY + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_XTS_KEY_LENGTH_256[] = { + &WR_DIS_KM_XTS_KEY_LENGTH_256[0], // [] wr_dis of KM_XTS_KEY_LENGTH_256 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE_H[] = { + &WR_DIS_KM_DEPLOY_ONLY_ONCE_H[0], // [] wr_dis of KM_DEPLOY_ONLY_ONCE_H + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY_H[] = { + &WR_DIS_FORCE_USE_KEY_MANAGER_KEY_H[0], // [] wr_dis of FORCE_USE_KEY_MANAGER_KEY_H + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[] = { + &WR_DIS_LOCK_KM_KEY[0], // [] wr_dis of LOCK_KM_KEY + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE_H[] = { + &WR_DIS_KM_DISABLE_DEPLOY_MODE_H[0], // [] wr_dis of KM_DISABLE_DEPLOY_MODE_H + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[] = { + &WR_DIS_KM_DISABLE_DEPLOY_MODE[0], // [] wr_dis of KM_DISABLE_DEPLOY_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[] = { + &WR_DIS_DIS_USB_JTAG[0], // [] wr_dis of DIS_USB_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = { + &WR_DIS_DIS_FORCE_DOWNLOAD[0], // [] wr_dis of DIS_FORCE_DOWNLOAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = { + &WR_DIS_SPI_DOWNLOAD_MSPI_DIS[0], // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = { + &WR_DIS_DIS_TWAI[0], // [] wr_dis of DIS_TWAI + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[] = { + &WR_DIS_JTAG_SEL_ENABLE[0], // [] wr_dis of JTAG_SEL_ENABLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[] = { + &WR_DIS_DIS_PAD_JTAG[0], // [] wr_dis of DIS_PAD_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + &WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = { + &WR_DIS_WDT_DELAY_SEL[0], // [] wr_dis of WDT_DELAY_SEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[] = { + &WR_DIS_HYS_EN_PAD[0], // [] wr_dis of HYS_EN_PAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[] = { + &WR_DIS_PXA0_TIEH_SEL_0[0], // [] wr_dis of PXA0_TIEH_SEL_0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WDT[] = { + &WR_DIS_DIS_WDT[0], // [] wr_dis of DIS_WDT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[] = { + &WR_DIS_DIS_SWD[0], // [] wr_dis of DIS_SWD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_EN[] = { + &WR_DIS_PVT_GLITCH_EN[0], // [] wr_dis of PVT_GLITCH_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_MODE[] = { + &WR_DIS_PVT_GLITCH_MODE[0], // [] wr_dis of PVT_GLITCH_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = { + &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // [] wr_dis of SPI_BOOT_CRYPT_CNT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[] = { + &WR_DIS_KEY_PURPOSE_0[0], // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0_H[] = { + &WR_DIS_KEY_PURPOSE_0_H[0], // [] wr_dis of KEY_PURPOSE_0_H + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[] = { + &WR_DIS_KEY_PURPOSE_1[0], // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1_H[] = { + &WR_DIS_KEY_PURPOSE_1_H[0], // [] wr_dis of KEY_PURPOSE_1_H + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[] = { + &WR_DIS_KEY_PURPOSE_2[0], // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2_H[] = { + &WR_DIS_KEY_PURPOSE_2_H[0], // [] wr_dis of KEY_PURPOSE_2_H + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[] = { + &WR_DIS_KEY_PURPOSE_3[0], // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3_H[] = { + &WR_DIS_KEY_PURPOSE_3_H[0], // [] wr_dis of KEY_PURPOSE_3_H + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[] = { + &WR_DIS_KEY_PURPOSE_4[0], // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4_H[] = { + &WR_DIS_KEY_PURPOSE_4_H[0], // [] wr_dis of KEY_PURPOSE_4_H + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = { + &WR_DIS_KEY_PURPOSE_5[0], // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5_H[] = { + &WR_DIS_KEY_PURPOSE_5_H[0], // [] wr_dis of KEY_PURPOSE_5_H + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[] = { + &WR_DIS_ECC_FORCE_CONST_TIME[0], // [] wr_dis of ECC_FORCE_CONST_TIME + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = { + &WR_DIS_SEC_DPA_LEVEL[0], // [] wr_dis of SEC_DPA_LEVEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[] = { + &WR_DIS_XTS_DPA_CLK_ENABLE[0], // [] wr_dis of XTS_DPA_CLK_ENABLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[] = { + &WR_DIS_XTS_DPA_PSEUDO_LEVEL[0], // [] wr_dis of XTS_DPA_PSEUDO_LEVEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = { + &WR_DIS_SECURE_BOOT_EN[0], // [] wr_dis of SECURE_BOOT_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[] = { + &WR_DIS_HP_PWR_SRC_SEL[0], // [] wr_dis of HP_PWR_SRC_SEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[] = { + &WR_DIS_FLASH_ECC_EN[0], // [] wr_dis of FLASH_ECC_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[0], // [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[] = { + &WR_DIS_FLASH_TPUW[0], // [] wr_dis of FLASH_TPUW + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_DOWNLOAD_MODE[0], // [] wr_dis of DIS_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[] = { + &WR_DIS_DIS_DIRECT_BOOT[0], // [] wr_dis of DIS_DIRECT_BOOT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + &WR_DIS_ENABLE_SECURITY_DOWNLOAD[0], // [] wr_dis of ENABLE_SECURITY_DOWNLOAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[] = { + &WR_DIS_UART_PRINT_CONTROL[0], // [] wr_dis of UART_PRINT_CONTROL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[] = { + &WR_DIS_FORCE_SEND_RESUME[0], // [] wr_dis of FORCE_SEND_RESUME + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[] = { + &WR_DIS_SECURE_VERSION[0], // [] wr_dis of SECURE_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { + &WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HUK_GEN_STATE[] = { + &WR_DIS_HUK_GEN_STATE[0], // [] wr_dis of HUK_GEN_STATE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { + &WR_DIS_BLK1[0], // [] wr_dis of BLOCK1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = { + &WR_DIS_MAC[0], // [WR_DIS.MAC_FACTORY] wr_dis of MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = { + &WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_LO[] = { + &WR_DIS_WAFER_VERSION_MAJOR_LO[0], // [] wr_dis of WAFER_VERSION_MAJOR_LO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = { + &WR_DIS_DISABLE_BLK_VERSION_MAJOR[0], // [] wr_dis of DISABLE_BLK_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = { + &WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = { + &WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[] = { + &WR_DIS_PSRAM_CAP[0], // [] wr_dis of PSRAM_CAP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[] = { + &WR_DIS_TEMP[0], // [] wr_dis of TEMP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[] = { + &WR_DIS_PSRAM_VENDOR[0], // [] wr_dis of PSRAM_VENDOR + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = { + &WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { + &WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_HI[] = { + &WR_DIS_WAFER_VERSION_MAJOR_HI[0], // [] wr_dis of WAFER_VERSION_MAJOR_HI + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { + &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = { + &WR_DIS_BLOCK_USR_DATA[0], // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[] = { + &WR_DIS_CUSTOM_MAC[0], // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[] = { + &WR_DIS_BLOCK_KEY0[0], // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[] = { + &WR_DIS_BLOCK_KEY1[0], // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[] = { + &WR_DIS_BLOCK_KEY2[0], // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[] = { + &WR_DIS_BLOCK_KEY3[0], // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[] = { + &WR_DIS_BLOCK_KEY4[0], // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[] = { + &WR_DIS_BLOCK_KEY5[0], // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = { + &WR_DIS_BLOCK_SYS_DATA2[0], // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[] = { + &WR_DIS_USB_DEVICE_EXCHG_PINS[0], // [] wr_dis of USB_DEVICE_EXCHG_PINS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[] = { + &WR_DIS_USB_OTG11_EXCHG_PINS[0], // [] wr_dis of USB_OTG11_EXCHG_PINS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = { + &WR_DIS_SOFT_DIS_JTAG[0], // [] wr_dis of SOFT_DIS_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = { + &RD_DIS[0], // [] Disable reading from BlOCK4-10 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[] = { + &RD_DIS_BLOCK_KEY0[0], // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[] = { + &RD_DIS_BLOCK_KEY1[0], // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[] = { + &RD_DIS_BLOCK_KEY2[0], // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[] = { + &RD_DIS_BLOCK_KEY3[0], // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[] = { + &RD_DIS_BLOCK_KEY4[0], // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[] = { + &RD_DIS_BLOCK_KEY5[0], // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = { + &RD_DIS_BLOCK_SYS_DATA2[0], // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_USB_DEVICE_EXCHG_PINS[] = { + &RD_DIS_USB_DEVICE_EXCHG_PINS[0], // [] rd_dis of USB_DEVICE_EXCHG_PINS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_USB_OTG11_EXCHG_PINS[] = { + &RD_DIS_USB_OTG11_EXCHG_PINS[0], // [] rd_dis of USB_OTG11_EXCHG_PINS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1[] = { + &RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1[0], // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { + &DIS_USB_JTAG[0], // [] Set this bit to disable function of usb switch to jtag in module of usb device + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2[] = { + &RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2[0], // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { + &DIS_FORCE_DOWNLOAD[0], // [] Set this bit to disable the function that forces chip into download mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = { + &SPI_DOWNLOAD_MSPI_DIS[0], // [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = { + &DIS_TWAI[0], // [] Set this bit to disable TWAI function + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = { + &JTAG_SEL_ENABLE[0], // [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { + &SOFT_DIS_JTAG[0], // [] Set odd bits to disable JTAG in the soft way. JTAG can be enabled in HMAC module + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { + &DIS_PAD_JTAG[0], // [] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Set this bit to disable flash manual encrypt function (except in SPI boot mode) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6[] = { + &RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6[0], // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[] = { + &USB_PHY_SEL[0], // [] 0: intphy(gpio24/25) <---> usb_device 1: intphy(26/27) <---> usb_otg11.1: intphy(gpio26/27) <---> usb_device 1: intphy(24/25) <---> usb_otg11 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_HUK_GEN_STATE[] = { + &HUK_GEN_STATE[0], // [] Set the bits to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7[] = { + &RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7[0], // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10[] = { + &RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10[0], // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11[] = { + &RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11[0], // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[] = { + &KM_RND_SWITCH_CYCLE[0], // [] Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[] = { + &KM_DEPLOY_ONLY_ONCE[0], // [] EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: {EFUSE_KM_DEPLOY_ONLY_ONCE_H; EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram + &KM_DEPLOY_ONLY_ONCE[1], // [] EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: {EFUSE_KM_DEPLOY_ONLY_ONCE_H; EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[] = { + &FORCE_USE_KEY_MANAGER_KEY[0], // [] EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H; EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram + &FORCE_USE_KEY_MANAGER_KEY[1], // [] EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H; EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[] = { + &FORCE_DISABLE_SW_INIT_KEY[0], // [] Set this bit to disable software written init key; and force use efuse_init_key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KM_XTS_KEY_LENGTH_256[] = { + &KM_XTS_KEY_LENGTH_256[0], // [] Set this bit to config flash encryption xts-512 key; else use xts-256 key when using the key manager + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[] = { + &ECC_FORCE_CONST_TIME[0], // [] Set this bit to permanently turn on ECC const-time mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { + &WDT_DELAY_SEL[0], // [] Select lp wdt timeout threshold at startup = initial timeout value * (2 ^ (EFUSE_WDT_DELAY_SEL + 1)) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = { + &SPI_BOOT_CRYPT_CNT[0], // [] Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = { + &SECURE_BOOT_KEY_REVOKE0[0], // [] Revoke 1st secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = { + &SECURE_BOOT_KEY_REVOKE1[0], // [] Revoke 2nd secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = { + &SECURE_BOOT_KEY_REVOKE2[0], // [] Revoke 3rd secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = { + &KEY_PURPOSE_0[0], // [KEY0_PURPOSE] Purpose of Key0 + &KEY_PURPOSE_0[1], // [] Purpose of Key0. The 5-th bit + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = { + &KEY_PURPOSE_1[0], // [KEY1_PURPOSE] Purpose of Key1 + &KEY_PURPOSE_1[1], // [] Purpose of Key1. The 5-th bit + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = { + &KEY_PURPOSE_2[0], // [KEY2_PURPOSE] Purpose of Key2 + &KEY_PURPOSE_2[1], // [] Purpose of Key2. The 5-th bit + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = { + &KEY_PURPOSE_3[0], // [KEY3_PURPOSE] Purpose of Key3 + &KEY_PURPOSE_3[1], // [] Purpose of Key3. The 5-th bit + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = { + &KEY_PURPOSE_4[0], // [KEY4_PURPOSE] Purpose of Key4 + &KEY_PURPOSE_4[1], // [] Purpose of Key4. The 5-th bit + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = { + &KEY_PURPOSE_5[0], // [KEY5_PURPOSE] Purpose of Key5 + &KEY_PURPOSE_5[1], // [] Purpose of Key5. The 5-th bit + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = { + &SEC_DPA_LEVEL[0], // [] Configures the clock random divide mode to determine the dpa secure level + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[] = { + &XTS_DPA_CLK_ENABLE[0], // [] Sets this bit to enable xts clock anti-dpa attack function + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { + &SECURE_BOOT_EN[0], // [] Set this bit to enable secure boot + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Set this bit to enable revoking aggressive secure boot + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[] = { + &FLASH_ECC_EN[0], // [] Set this bit to enable ECC for flash boot + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[] = { + &DIS_USB_OTG_DOWNLOAD_MODE[0], // [] Set this bit to disable download via USB-OTG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { + &FLASH_TPUW[0], // [] Configures flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the configurable value. Otherwise; the waiting time is 30 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { + &DIS_DOWNLOAD_MODE[0], // [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 4; 5; 6; 7) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { + &DIS_DIRECT_BOOT[0], // [] Set this bit to disable direct boot mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] Set this bit to disable USB-Serial-JTAG print during rom boot + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[] = { + &LOCK_KM_KEY[0], // [] set this bit to lock the key manager key after deploy + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Set this bit to disable the USB-Serial-JTAG download function + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { + &ENABLE_SECURITY_DOWNLOAD[0], // [] Set this bit to enable security download mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { + &UART_PRINT_CONTROL[0], // [] Set the type of UART printing; 00: force enable printing; 01: enable printing when GPIO8 is reset at low level; 10: enable printing when GPIO8 is reset at high level; 11: force disable printing + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { + &FORCE_SEND_RESUME[0], // [] Set this bit to force ROM code to send a resume command during SPI boot + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { + &SECURE_VERSION[0], // [] Secure version used by ESP-IDF anti-rollback feature + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = { + &SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] Represents whether secure boot do fast verification on wake is disabled. 0: enabled 1: disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[] = { + &HYS_EN_PAD[0], // [] Set bits to enable hysteresis function of PAD0~27 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_0[] = { + &PXA0_TIEH_SEL_0[0], // [] Output LDO VO0 tieh source select. 0: 1'b1 1: sdmmc1 2: reg 3:sdmmc0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_EN[] = { + &PVT_GLITCH_EN[0], // [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[] = { + &KM_DISABLE_DEPLOY_MODE[0], // [] EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H; EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set each bit to control whether corresponding key's deploy mode of new value deployment is disabled. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram + &KM_DISABLE_DEPLOY_MODE[1], // [] EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H; EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set each bit to control whether corresponding key's deploy mode of new value deployment is disabled. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[] = { + &XTS_DPA_PSEUDO_LEVEL[0], // [] Sets this bit to control the xts pseudo-round anti-dpa attack function. 0: controlled by register. 1-3: the higher the value is; the more pseudo-rounds are inserted to the xts-aes calculation + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_HP_PWR_SRC_SEL[] = { + &HP_PWR_SRC_SEL[0], // [] HP system power source select. 0:LDO 1: DCDC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_SHA384_EN[] = { + &SECURE_BOOT_SHA384_EN[0], // [] Represents whether secure boot using SHA-384 is enabled. 0: disable 1: enable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_WDT[] = { + &DIS_WDT[0], // [] Set this bit to disable watch dog + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_SWD[] = { + &DIS_SWD[0], // [] Set bit to disable super-watchdog + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_MODE[] = { + &PVT_GLITCH_MODE[0], // [] Use to configure glitch mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_MAC[] = { + &MAC[0], // [MAC_FACTORY] MAC address + &MAC[1], // [MAC_FACTORY] MAC address + &MAC[2], // [MAC_FACTORY] MAC address + &MAC[3], // [MAC_FACTORY] MAC address + &MAC[4], // [MAC_FACTORY] MAC address + &MAC[5], // [MAC_FACTORY] MAC address + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = { + &WAFER_VERSION_MINOR[0], // [] Minor chip version + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = { + &WAFER_VERSION_MAJOR[0], // [] Major chip version (lower 2 bits) + &WAFER_VERSION_MAJOR[1], // [] Major chip version (MSB) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = { + &DISABLE_WAFER_VERSION_MAJOR[0], // [] Disables check of wafer version major + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = { + &DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = { + &BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR of BLOCK2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { + &BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = { + &PSRAM_CAP[0], // [] PSRAM capacity + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_TEMP[] = { + &TEMP[0], // [] Operating temperature of the ESP chip + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[] = { + &PSRAM_VENDOR[0], // [] PSRAM vendor + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { + &PKG_VERSION[0], // [] Package version + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { + &OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { + &USER_DATA[0], // [BLOCK_USR_DATA] User data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = { + &USER_DATA_MAC_CUSTOM[0], // [MAC_CUSTOM CUSTOM_MAC] Custom MAC + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { + &KEY0[0], // [BLOCK_KEY0] Key0 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = { + &KEY1[0], // [BLOCK_KEY1] Key1 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = { + &KEY2[0], // [BLOCK_KEY2] Key2 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = { + &KEY3[0], // [BLOCK_KEY3] Key3 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { + &KEY4[0], // [BLOCK_KEY4] Key4 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = { + &KEY5[0], // [BLOCK_KEY5] Key5 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[] = { + &USB_DEVICE_EXCHG_PINS[0], // [] Enable usb device exchange pins of D+ and D- + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[] = { + &USB_OTG11_EXCHG_PINS[0], // [] Enable usb otg11 exchange pins of D+ and D- + NULL +}; diff --git a/components/efuse/esp32p4/esp_efuse_table_v3.0.csv b/components/efuse/esp32p4/esp_efuse_table_v3.0.csv new file mode 100644 index 00000000000..b1a06a657c8 --- /dev/null +++ b/components/efuse/esp32p4/esp_efuse_table_v3.0.csv @@ -0,0 +1,209 @@ + +# field_name, | efuse_block, | bit_start, | bit_count, |comment # +# | (EFUSE_BLK0 | (0..255) | (1-256) | # +# | EFUSE_BLK1 | | | # +# | ...) | | | # +########################################################################## +# !!!!!!!!!!! # +# After editing this file, run the command manually "idf.py efuse-common-table" +# this will generate new source files, next rebuild all the sources. +# !!!!!!!!!!! # + +# This file was generated by regtools.py based on the efuses.yaml file with the version: 8f99219081b5ec5521595bf60ed8b331 + +WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses +WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS +WR_DIS.KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_RND_SWITCH_CYCLE +WR_DIS.KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DEPLOY_ONLY_ONCE +WR_DIS.FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_USE_KEY_MANAGER_KEY +WR_DIS.FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_DISABLE_SW_INIT_KEY +WR_DIS.KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 1, 1, [] wr_dis of KM_XTS_KEY_LENGTH_256 +WR_DIS.KM_DEPLOY_ONLY_ONCE_H, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DEPLOY_ONLY_ONCE_H +WR_DIS.FORCE_USE_KEY_MANAGER_KEY_H, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_USE_KEY_MANAGER_KEY_H +WR_DIS.LOCK_KM_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of LOCK_KM_KEY +WR_DIS.KM_DISABLE_DEPLOY_MODE_H, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DISABLE_DEPLOY_MODE_H +WR_DIS.KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DISABLE_DEPLOY_MODE +WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG +WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD +WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS +WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_TWAI +WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE +WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG +WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT +WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of WDT_DELAY_SEL +WR_DIS.HYS_EN_PAD, EFUSE_BLK0, 2, 1, [] wr_dis of HYS_EN_PAD +WR_DIS.PXA0_TIEH_SEL_0, EFUSE_BLK0, 2, 1, [] wr_dis of PXA0_TIEH_SEL_0 +WR_DIS.DIS_WDT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_WDT +WR_DIS.DIS_SWD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_SWD +WR_DIS.PVT_GLITCH_EN, EFUSE_BLK0, 3, 1, [] wr_dis of PVT_GLITCH_EN +WR_DIS.PVT_GLITCH_MODE, EFUSE_BLK0, 3, 1, [] wr_dis of PVT_GLITCH_MODE +WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT +WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0 +WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1 +WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2 +WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0 +WR_DIS.KEY_PURPOSE_0_H, EFUSE_BLK0, 8, 1, [] wr_dis of KEY_PURPOSE_0_H +WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1 +WR_DIS.KEY_PURPOSE_1_H, EFUSE_BLK0, 9, 1, [] wr_dis of KEY_PURPOSE_1_H +WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2 +WR_DIS.KEY_PURPOSE_2_H, EFUSE_BLK0, 10, 1, [] wr_dis of KEY_PURPOSE_2_H +WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 +WR_DIS.KEY_PURPOSE_3_H, EFUSE_BLK0, 11, 1, [] wr_dis of KEY_PURPOSE_3_H +WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 +WR_DIS.KEY_PURPOSE_4_H, EFUSE_BLK0, 12, 1, [] wr_dis of KEY_PURPOSE_4_H +WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 +WR_DIS.KEY_PURPOSE_5_H, EFUSE_BLK0, 13, 1, [] wr_dis of KEY_PURPOSE_5_H +WR_DIS.ECC_FORCE_CONST_TIME, EFUSE_BLK0, 14, 1, [] wr_dis of ECC_FORCE_CONST_TIME +WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL +WR_DIS.XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_CLK_ENABLE +WR_DIS.XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_PSEUDO_LEVEL +WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN +WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE +WR_DIS.HP_PWR_SRC_SEL, EFUSE_BLK0, 17, 1, [] wr_dis of HP_PWR_SRC_SEL +WR_DIS.FLASH_ECC_EN, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_ECC_EN +WR_DIS.DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE +WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW +WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE +WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT +WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT +WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE +WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD +WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL +WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME +WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION +WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE +WR_DIS.HUK_GEN_STATE, EFUSE_BLK0, 19, 1, [] wr_dis of HUK_GEN_STATE +WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 +WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC +WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR +WR_DIS.WAFER_VERSION_MAJOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR_LO +WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR +WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR +WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR +WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR +WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_CAP +WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP +WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR +WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION +WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 +WR_DIS.WAFER_VERSION_MAJOR_HI, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR_HI +WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID +WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA +WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC +WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 +WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1 +WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2 +WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 +WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 +WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 +WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 +WR_DIS.USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 29, 1, [] wr_dis of USB_DEVICE_EXCHG_PINS +WR_DIS.USB_OTG11_EXCHG_PINS, EFUSE_BLK0, 29, 1, [] wr_dis of USB_OTG11_EXCHG_PINS +WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG +RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10 +RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 +RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 +RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 +RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 +RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 +RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 +RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 +RD_DIS.USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 38, 1, [] rd_dis of USB_DEVICE_EXCHG_PINS +RD_DIS.USB_OTG11_EXCHG_PINS, EFUSE_BLK0, 38, 1, [] rd_dis of USB_OTG11_EXCHG_PINS +RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1, EFUSE_BLK0, 39, 2, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled +DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Set this bit to disable function of usb switch to jtag in module of usb device +RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2, EFUSE_BLK0, 42, 1, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled +DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Set this bit to disable the function that forces chip into download mode +SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download +DIS_TWAI, EFUSE_BLK0, 46, 1, [] Set this bit to disable TWAI function +JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 +SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Set odd bits to disable JTAG in the soft way. JTAG can be enabled in HMAC module +DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently +DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Set this bit to disable flash manual encrypt function (except in SPI boot mode) +RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6, EFUSE_BLK0, 53, 4, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled +USB_PHY_SEL, EFUSE_BLK0, 57, 1, [] 0: intphy(gpio24/25) <---> usb_device 1: intphy(26/27) <---> usb_otg11.1: intphy(gpio26/27) <---> usb_device 1: intphy(24/25) <---> usb_otg11 +HUK_GEN_STATE, EFUSE_BLK0, 58, 5, [] Set the bits to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid +RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7, EFUSE_BLK0, 63, 1, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled +RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10, EFUSE_BLK0, 64, 3, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled +RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11, EFUSE_BLK0, 67, 1, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled +KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 68, 1, [] Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles +KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 69, 4, [] EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: {EFUSE_KM_DEPLOY_ONLY_ONCE_H; EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram +, EFUSE_BLK0, 118, 1, [] EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: {EFUSE_KM_DEPLOY_ONLY_ONCE_H; EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram +FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 73, 4, [] EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H; EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram +, EFUSE_BLK0, 119, 1, [] EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H; EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram +FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 77, 1, [] Set this bit to disable software written init key; and force use efuse_init_key +KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 78, 1, [] Set this bit to config flash encryption xts-512 key; else use xts-256 key when using the key manager +ECC_FORCE_CONST_TIME, EFUSE_BLK0, 79, 1, [] Set this bit to permanently turn on ECC const-time mode +WDT_DELAY_SEL, EFUSE_BLK0, 81, 1, [] Select lp wdt timeout threshold at startup = initial timeout value * (2 ^ (EFUSE_WDT_DELAY_SEL + 1)) +SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} +SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key +SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key +SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key +KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Purpose of Key0 +, EFUSE_BLK0, 155, 1, [] Purpose of Key0. The 5-th bit +KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Purpose of Key1 +, EFUSE_BLK0, 156, 1, [] Purpose of Key1. The 5-th bit +KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Purpose of Key2 +, EFUSE_BLK0, 157, 1, [] Purpose of Key2. The 5-th bit +KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Purpose of Key3 +, EFUSE_BLK0, 158, 1, [] Purpose of Key3. The 5-th bit +KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Purpose of Key4 +, EFUSE_BLK0, 159, 1, [] Purpose of Key4. The 5-th bit +KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Purpose of Key5 +, EFUSE_BLK0, 164, 1, [] Purpose of Key5. The 5-th bit +SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, [] Configures the clock random divide mode to determine the dpa secure level +XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 115, 1, [] Sets this bit to enable xts clock anti-dpa attack function +SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Set this bit to enable secure boot +SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Set this bit to enable revoking aggressive secure boot +FLASH_ECC_EN, EFUSE_BLK0, 122, 1, [] Set this bit to enable ECC for flash boot +DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 123, 1, [] Set this bit to disable download via USB-OTG +FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Configures flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the configurable value. Otherwise; the waiting time is 30 +DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 4; 5; 6; 7) +DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [] Set this bit to disable direct boot mode +DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [] Set this bit to disable USB-Serial-JTAG print during rom boot +LOCK_KM_KEY, EFUSE_BLK0, 131, 1, [] set this bit to lock the key manager key after deploy +DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Set this bit to disable the USB-Serial-JTAG download function +ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Set this bit to enable security download mode +UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the type of UART printing; 00: force enable printing; 01: enable printing when GPIO8 is reset at low level; 10: enable printing when GPIO8 is reset at high level; 11: force disable printing +FORCE_SEND_RESUME, EFUSE_BLK0, 136, 1, [] Set this bit to force ROM code to send a resume command during SPI boot +SECURE_VERSION, EFUSE_BLK0, 137, 16, [] Secure version used by ESP-IDF anti-rollback feature +SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 153, 1, [] Represents whether secure boot do fast verification on wake is disabled. 0: enabled 1: disabled +HYS_EN_PAD, EFUSE_BLK0, 154, 1, [] Set bits to enable hysteresis function of PAD0~27 +PXA0_TIEH_SEL_0, EFUSE_BLK0, 160, 2, [] Output LDO VO0 tieh source select. 0: 1'b1 1: sdmmc1 2: reg 3:sdmmc0 +PVT_GLITCH_EN, EFUSE_BLK0, 162, 1, [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable +KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 168, 4, [] EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H; EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set each bit to control whether corresponding key's deploy mode of new value deployment is disabled. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram +, EFUSE_BLK0, 167, 1, [] EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H; EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set each bit to control whether corresponding key's deploy mode of new value deployment is disabled. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds; bit4:psram +XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 176, 2, [] Sets this bit to control the xts pseudo-round anti-dpa attack function. 0: controlled by register. 1-3: the higher the value is; the more pseudo-rounds are inserted to the xts-aes calculation +HP_PWR_SRC_SEL, EFUSE_BLK0, 178, 1, [] HP system power source select. 0:LDO 1: DCDC +SECURE_BOOT_SHA384_EN, EFUSE_BLK0, 179, 1, [] Represents whether secure boot using SHA-384 is enabled. 0: disable 1: enable +DIS_WDT, EFUSE_BLK0, 180, 1, [] Set this bit to disable watch dog +DIS_SWD, EFUSE_BLK0, 181, 1, [] Set bit to disable super-watchdog +PVT_GLITCH_MODE, EFUSE_BLK0, 182, 2, [] Use to configure glitch mode +MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address +, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address +WAFER_VERSION_MINOR, EFUSE_BLK1, 64, 4, [] Minor chip version +WAFER_VERSION_MAJOR, EFUSE_BLK1, 68, 2, [] Major chip version (lower 2 bits) +, EFUSE_BLK1, 87, 1, [] Major chip version (MSB) +DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 70, 1, [] Disables check of wafer version major +DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK1, 71, 1, [] Disables check of blk version major +BLK_VERSION_MINOR, EFUSE_BLK1, 72, 3, [] BLK_VERSION_MINOR of BLOCK2 +BLK_VERSION_MAJOR, EFUSE_BLK1, 75, 2, [] BLK_VERSION_MAJOR of BLOCK2 +PSRAM_CAP, EFUSE_BLK1, 77, 3, [] PSRAM capacity +TEMP, EFUSE_BLK1, 80, 2, [] Operating temperature of the ESP chip +PSRAM_VENDOR, EFUSE_BLK1, 82, 2, [] PSRAM vendor +PKG_VERSION, EFUSE_BLK1, 84, 3, [] Package version +OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID +USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data +USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC +KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data +KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data +KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data +KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data +KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data +KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data +USB_DEVICE_EXCHG_PINS, EFUSE_BLK10, 228, 1, [] Enable usb device exchange pins of D+ and D- +USB_OTG11_EXCHG_PINS, EFUSE_BLK10, 229, 1, [] Enable usb otg11 exchange pins of D+ and D- diff --git a/components/efuse/esp32p4/include/esp_efuse_chip.h b/components/efuse/esp32p4/include/esp_efuse_chip.h index 3b065c517ce..b9e6bcc2344 100644 --- a/components/efuse/esp32p4/include/esp_efuse_chip.h +++ b/components/efuse/esp32p4/include/esp_efuse_chip.h @@ -1,11 +1,13 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include "sdkconfig.h" + #ifdef __cplusplus extern "C" { #endif @@ -63,6 +65,11 @@ typedef enum { typedef enum { ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */ ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, /**< ECDSA private key (Expected in little endian order)*/ + +#if CONFIG_ESP32P4_REV_MIN_FULL >= 300 + ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P256 = ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY, /**< ECDSA private key (P256) (Expected in little endian order)*/ +#endif + ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 = 2, /**< XTS_AES_256_KEY_1 (flash/PSRAM encryption) */ ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 = 3, /**< XTS_AES_256_KEY_2 (flash/PSRAM encryption) */ ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */ @@ -74,7 +81,18 @@ typedef enum { ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */ ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */ ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY = 12, /**< KM_INIT_KEY */ + +#if CONFIG_ESP32P4_REV_MIN_FULL >= 300 + ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 = 13, /**< PSRAM encryption key (XTS_AES_256_KEY_1) */ + ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 = 14, /**< PSRAM encryption key (XTS_AES_256_KEY_2) */ + ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY = 15, /**< PSRAM encryption key (XTS_AES_128_KEY) */ + ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 = 16, /**< ECDSA private key (P192) */ + ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L = 17, /**< ECDSA private key (P384_L) */ + ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H = 18, /**< ECDSA private key (P384_H) */ + ESP_EFUSE_KEY_PURPOSE_MAX = 32, /**< MAX PURPOSE */ +#else ESP_EFUSE_KEY_PURPOSE_MAX = 16, /**< MAX PURPOSE */ +#endif } esp_efuse_purpose_t; #ifdef __cplusplus diff --git a/components/efuse/esp32p4/include/esp_efuse_table.h b/components/efuse/esp32p4/include/esp_efuse_table.h index 4366f8541db..fed2072d5b4 100644 --- a/components/efuse/esp32p4/include/esp_efuse_table.h +++ b/components/efuse/esp32p4/include/esp_efuse_table.h @@ -8,340 +8,13 @@ extern "C" { #endif -#include "esp_efuse.h" +#include "sdkconfig.h" -// md5_digest_table 665d4d3a1354653f8e46869d49df1a2f -// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. -// If you want to change some fields, you need to change esp_efuse_table.csv file -// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. -// To show efuse_table run the command 'show_efuse_table'. - - -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_KEY_LENGTH_256[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WDT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[]; -#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0 -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[]; -#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1 -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[]; -#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2 -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[]; -#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3 -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; -#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4 -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; -#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_ENABLE_SOFT_K[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_HUK_GEN_STATE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; -#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_LO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_HI[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_DREF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_DREF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_MUL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_MUL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_K[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_VOS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_C[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_K[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_VOS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_C[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_DCDC_DBIAS_VOL_GAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; -#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; -#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC -#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[]; -#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0 -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[]; -#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1 -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[]; -#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2 -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[]; -#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3 -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[]; -#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4 -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[]; -#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5 -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[]; -#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[]; -#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0 -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[]; -#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1 -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[]; -#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2 -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[]; -#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3 -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[]; -#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4 -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[]; -#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5 -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[]; -#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2 -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_TEMPERATURE_SENSOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; -extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_XTS_KEY_LENGTH_256[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; -#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0 -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; -#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1 -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; -#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2 -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; -#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3 -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; -#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4 -extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; -#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5 -extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_ENABLE_SOFT_K[]; -extern const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_HP_PWR_SRC_SEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET_EN[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_WDT[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DIS_SWD[]; -extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; -#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR_LO[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR_HI[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_DREF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_DREF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_MUL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_MUL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_K[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_VOS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_C[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_K[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_VOS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_C[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBG[]; -extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[]; -extern const esp_efuse_desc_t* ESP_EFUSE_LP_DCDC_DBIAS_VOL_GAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; -#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA -extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; -#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM -#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM -extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; -#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0 -extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; -#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1 -extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; -#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2 -extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; -#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3 -extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; -#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4 -extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; -#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5 -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN0[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN1[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN2[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN3[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF[]; -extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[]; +#if CONFIG_ESP32P4_REV_MIN_FULL >= 300 +#include "esp_efuse_table_v3.0.h" +#else +#include "esp_efuse_table_v0.0_v2.0.h" +#endif #ifdef __cplusplus } diff --git a/components/efuse/esp32p4/include/esp_efuse_table_v0.0_v2.0.h b/components/efuse/esp32p4/include/esp_efuse_table_v0.0_v2.0.h new file mode 100644 index 00000000000..5cdada4fc14 --- /dev/null +++ b/components/efuse/esp32p4/include/esp_efuse_table_v0.0_v2.0.h @@ -0,0 +1,348 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "esp_efuse.h" + +// md5_digest_table 665d4d3a1354653f8e46869d49df1a2f +// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. +// If you want to change some fields, you need to change esp_efuse_table.csv file +// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. +// To show efuse_table run the command 'show_efuse_table'. + + +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_KEY_LENGTH_256[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WDT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[]; +#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[]; +#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[]; +#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[]; +#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; +#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; +#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_ENABLE_SOFT_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_HUK_GEN_STATE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_LO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_HI[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_DREF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_DREF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_MUL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_MUL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_VOS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_C[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_VOS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_C[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_DCDC_DBIAS_VOL_GAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; +#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_TEMPERATURE_SENSOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; +extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_XTS_KEY_LENGTH_256[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; +#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; +#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; +#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; +#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; +#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; +#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5 +extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_ENABLE_SOFT_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_HP_PWR_SRC_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_WDT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_SWD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; +#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR_LO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR_HI[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_DREF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_DREF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_MUL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_MUL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_VOS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_C[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_VOS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_C[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LP_DCDC_DBIAS_VOL_GAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; +#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA +extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; +#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM +#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM +extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; +#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; +#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; +#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; +#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; +#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; +#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[]; + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32p4/include/esp_efuse_table_v3.0.h b/components/efuse/esp32p4/include/esp_efuse_table_v3.0.h new file mode 100644 index 00000000000..d209ce8c990 --- /dev/null +++ b/components/efuse/esp32p4/include/esp_efuse_table_v3.0.h @@ -0,0 +1,244 @@ +/* + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "esp_efuse.h" + +// md5_digest_table 546834ca62bf5546bc26447554d7a099 +// This file was generated from the file esp_efuse_table_v3.0.csv. DO NOT CHANGE THIS FILE MANUALLY. +// If you want to change some fields, you need to change esp_efuse_table_v3.0.csv file +// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. +// To show efuse_table run the command 'show_efuse_table'. + + +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_XTS_KEY_LENGTH_256[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE_H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY_H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE_H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WDT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[]; +#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0_H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[]; +#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1_H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[]; +#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2_H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[]; +#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3_H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; +#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4_H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; +#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5_H[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HUK_GEN_STATE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_LO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_HI[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; +#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; +#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[]; +#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[]; +#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[]; +#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[]; +#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[]; +#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[]; +#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[]; +#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_USB_DEVICE_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_USB_OTG11_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[]; +extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_HUK_GEN_STATE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KM_XTS_KEY_LENGTH_256[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; +#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; +#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; +#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; +#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; +#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; +#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5 +extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_HP_PWR_SRC_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_SHA384_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_WDT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_SWD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; +#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; +#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA +extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; +#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM +#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM +extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; +#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; +#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; +#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; +#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; +#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; +#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5 +extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[]; + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32p4/sources.cmake b/components/efuse/esp32p4/sources.cmake index 9dffd72008d..c05edde1192 100644 --- a/components/efuse/esp32p4/sources.cmake +++ b/components/efuse/esp32p4/sources.cmake @@ -1,4 +1,15 @@ -set(EFUSE_SOC_SRCS "esp_efuse_table.c" - "esp_efuse_fields.c" - "esp_efuse_rtc_calib.c" - "esp_efuse_utility.c") +set(EFUSE_SOC_SRCS + "esp_efuse_utility.c" + "esp_efuse_fields.c" +) + +if(CONFIG_ESP32P4_REV_MIN_FULL GREATER_EQUAL 300) + list(APPEND EFUSE_SOC_SRCS + "esp_efuse_table_v3.0.c" + ) +else() + list(APPEND EFUSE_SOC_SRCS + "esp_efuse_table.c" + "esp_efuse_rtc_calib.c" + ) +endif() diff --git a/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c b/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c index 1fa4b07a679..292ac043642 100644 --- a/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c +++ b/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c @@ -177,7 +177,7 @@ esp_efuse_purpose_t esp_efuse_get_key_purpose(esp_efuse_block_t block) } unsigned idx = block - EFUSE_BLK_KEY0; uint8_t value = 0; - esp_err_t err = esp_efuse_read_field_blob(s_table[idx].keypurpose, &value, s_table[idx].keypurpose[0]->bit_count); + esp_err_t err = esp_efuse_read_field_blob(s_table[idx].keypurpose, &value, esp_efuse_get_field_size(s_table[idx].keypurpose)); if (err != ESP_OK) { return ESP_EFUSE_KEY_PURPOSE_MAX; } @@ -190,7 +190,7 @@ esp_err_t esp_efuse_set_key_purpose(esp_efuse_block_t block, esp_efuse_purpose_t return ESP_ERR_INVALID_ARG; } unsigned idx = block - EFUSE_BLK_KEY0; - return esp_efuse_write_field_blob(s_table[idx].keypurpose, &purpose, s_table[idx].keypurpose[0]->bit_count); + return esp_efuse_write_field_blob(s_table[idx].keypurpose, &purpose, esp_efuse_get_field_size(s_table[idx].keypurpose)); } bool esp_efuse_get_keypurpose_dis_write(esp_efuse_block_t block) diff --git a/components/hal/esp32p4/include/hal/ecdsa_ll.h b/components/hal/esp32p4/include/hal/ecdsa_ll.h index b7d16aae0e7..39205c4efd4 100644 --- a/components/hal/esp32p4/include/hal/ecdsa_ll.h +++ b/components/hal/esp32p4/include/hal/ecdsa_ll.h @@ -11,6 +11,7 @@ #include "soc/ecdsa_reg.h" #include "soc/hp_sys_clkrst_struct.h" #include "soc/soc_caps.h" +#include "soc/efuse_reg.h" #include "hal/ecdsa_types.h" #ifdef __cplusplus @@ -440,6 +441,41 @@ static inline bool ecdsa_ll_is_deterministic_mode_supported(void) return true; } +/** + * @brief Set the ECDSA key block in eFuse + * + * @param curve ECDSA curve type + * @param efuse_blk eFuse block number + */ +__attribute__((always_inline)) static inline void ecdsa_ll_set_ecdsa_key_blk(ecdsa_curve_t curve, int efuse_blk) +{ +#ifdef EFUSE_CFG_ECDSA_BLK + (void) curve; + EFUSE.conf.cfg_ecdsa_blk = efuse_blk; +#else + uint8_t efuse_blk_low = 0; + uint8_t efuse_blk_high = 0; + switch (curve) { + case ECDSA_CURVE_SECP192R1: + EFUSE.ecdsa.cfg_ecdsa_p192_blk = efuse_blk; + break; + case ECDSA_CURVE_SECP256R1: + EFUSE.ecdsa.cfg_ecdsa_p256_blk = efuse_blk; + break; + case ECDSA_CURVE_SECP384R1: + // ECDSA-p384 uses two efuse blocks to store the key. These two blocks are stored in a single integer + // where the least significant 4 bits store the low key block number and the next 4 more significant bits store the high key block number. + HAL_ECDSA_EXTRACT_KEY_BLOCKS(efuse_blk, efuse_blk_high, efuse_blk_low); + EFUSE.ecdsa.cfg_ecdsa_p384_h_blk = efuse_blk_high; + EFUSE.ecdsa.cfg_ecdsa_p384_l_blk = efuse_blk_low; + break; + default: + HAL_ASSERT(false && "Unsupported curve"); + break; + } +#endif +} + /** * @brief Check if the ECDSA peripheral uses MPI module's memory */ diff --git a/components/hal/esp32p4/include/hal/efuse_ll.h b/components/hal/esp32p4/include/hal/efuse_ll.h index 9011a8c50cb..52b7d9aac25 100644 --- a/components/hal/esp32p4/include/hal/efuse_ll.h +++ b/components/hal/esp32p4/include/hal/efuse_ll.h @@ -148,17 +148,29 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_controller_st __attribute__((always_inline)) static inline uint32_t efuse_ll_get_active_hp_dbias(void) { +#ifdef EFUSE_ACTIVE_HP_DBIAS return EFUSE.rd_mac_sys_4.active_hp_dbias; +#else + return 0; +#endif } __attribute__((always_inline)) static inline uint32_t efuse_ll_get_active_lp_dbias(void) { +#ifdef EFUSE_ACTIVE_LP_DBIAS return EFUSE.rd_mac_sys_4.active_lp_dbias; +#else + return 0; +#endif } __attribute__((always_inline)) static inline int32_t efuse_ll_get_dbias_vol_gap(void) { +#ifdef EFUSE_LP_DCDC_DBIAS_VOL_GAP return EFUSE.rd_mac_sys_5.lp_dcdc_dbias_vol_gap; +#else + return 0; +#endif } /******************* eFuse control functions *************************/ diff --git a/components/hal/esp32p4/include/hal/ldo_ll.h b/components/hal/esp32p4/include/hal/ldo_ll.h index 2b443b49ba0..3741da3dd07 100644 --- a/components/hal/esp32p4/include/hal/ldo_ll.h +++ b/components/hal/esp32p4/include/hal/ldo_ll.h @@ -15,6 +15,7 @@ #include "hal/pmu_types.h" #include "soc/pmu_struct.h" #include "soc/efuse_struct.h" +#include "hal/config.h" #ifdef __cplusplus extern "C" { @@ -68,14 +69,16 @@ static inline bool ldo_ll_is_valid_ldo_channel(int ldo_chan) __attribute__((always_inline)) static inline void ldo_ll_voltage_to_dref_mul(int ldo_unit, int voltage_mv, uint8_t *dref, uint8_t *mul, bool *use_rail_voltage) { - uint8_t efuse_k = 0; - uint8_t efuse_vos = 0; - uint8_t efuse_c = 0; // to avoid using FPU, enlarge the constants by 1000 as fixed point int K_1000 = 1000; int Vos_1000 = 0; int C_1000 = 1000; +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) < 300 + uint8_t efuse_k = 0; + uint8_t efuse_vos = 0; + uint8_t efuse_c = 0; + if (efuse_hal_blk_version() >= 1) { // load the calibration values from the eFuse if (ldo_unit == 2) { @@ -99,6 +102,7 @@ static inline void ldo_ll_voltage_to_dref_mul(int ldo_unit, int voltage_mv, uint C_1000 = efuse_c & 0x20 ? -1 * (efuse_c & 0x1F) + 990 : efuse_c + 990; } } +#endif // iterate all the possible dref and mul values to find the best match int min_voltage_diff = 400000000; @@ -120,6 +124,7 @@ static inline void ldo_ll_voltage_to_dref_mul(int ldo_unit, int voltage_mv, uint } } +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) < 300 if (efuse_hal_blk_version() >= 1) { // For unit0 and unit1, the mul and dref value are calibrated and saved in the efuse, load them when available if (ldo_unit == 0 && voltage_mv == 1800) { @@ -135,6 +140,7 @@ static inline void ldo_ll_voltage_to_dref_mul(int ldo_unit, int voltage_mv, uint } } } +#endif *dref = matched_dref; *mul = matched_mul; diff --git a/components/hal/esp32p4/include/hal/temperature_sensor_ll.h b/components/hal/esp32p4/include/hal/temperature_sensor_ll.h index 72c76d22732..90ce875c511 100644 --- a/components/hal/esp32p4/include/hal/temperature_sensor_ll.h +++ b/components/hal/esp32p4/include/hal/temperature_sensor_ll.h @@ -25,6 +25,7 @@ #include "soc/soc_caps.h" #include "soc/interrupts.h" #include "soc/soc_etm_source.h" +#include "soc/efuse_reg.h" #include "hal/temperature_sensor_types.h" #include "hal/assert.h" #include "hal/misc.h" @@ -258,6 +259,23 @@ static inline void temperature_sensor_ll_set_sample_rate(uint16_t rate) HAL_FORCE_MODIFY_U32_REG_FIELD(LP_TSENS.sample_rate, sample_rate, rate); } +/** + * @brief Retrieve and calculate the temperature sensor calibration value. + * + * @return Temperature calibration value. + */ +static inline int temperature_sensor_ll_load_calib_param(void) +{ +#ifdef EFUSE_TEMPERATURE_SENSOR + uint32_t cal_temp = EFUSE.rd_sys_part2_data3.temperature_sensor; + // BIT(8) stands for sign: 1: negative, 0: positive + int tsens_cal = ((cal_temp & BIT(8)) != 0)? -(uint8_t)cal_temp: (uint8_t)cal_temp; + return tsens_cal; +#else + return 0; +#endif +} + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/efuse_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/efuse_eco5_struct.h deleted file mode 100644 index e24109ae081..00000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/efuse_eco5_struct.h +++ /dev/null @@ -1,3689 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: program_data registers */ -/** Type of pgm_datan register - * Represents pgm_datan - */ -typedef union { - struct { - /** pgm_data_n : R/W; bitpos: [31:0]; default: 0; - * Configures the nth 32-bit data to be programmed. - */ - uint32_t pgm_data_n:32; - }; - uint32_t val; -} efuse_pgm_datan_reg_t; - -/** Type of pgm_check_valuen register - * Represents pgm_check_valuen - */ -typedef union { - struct { - /** pgm_rs_data_n : R/W; bitpos: [31:0]; default: 0; - * Configures the nth RS code to be programmed. - */ - uint32_t pgm_rs_data_n:32; - }; - uint32_t val; -} efuse_pgm_check_valuen_reg_t; - - -/** Group: block0 registers */ -/** Type of rd_wr_dis register - * Represents rd_wr_dis - */ -typedef union { - struct { - /** wr_dis : RO; bitpos: [31:0]; default: 0; - * Represents whether programming of individual eFuse memory bit is disabled. For - * mapping between the bits of this field and the eFuse memory bits, please refer to - * Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}. - * 1: Disabled - * 0: Enabled - */ - uint32_t wr_dis:32; - }; - uint32_t val; -} efuse_rd_wr_dis_reg_t; - -/** Type of rd_repeat_data0 register - * Represents rd_repeat_data - */ -typedef union { - struct { - /** rd_dis : RO; bitpos: [6:0]; default: 0; - * Represents whether reading of individual eFuse block(block4~block10) is disabled or - * enabled. - * 1: disabled - * 0: enabled - */ - uint32_t rd_dis:7; - /** recovery_bootloader_flash_sector_0_1 : RO; bitpos: [8:7]; default: 0; - * Represents the starting flash sector (flash sector size is 0x1000) of the recovery - * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - * - this feature is disabled. - */ - uint32_t recovery_bootloader_flash_sector_0_1:2; - /** dis_usb_jtag : RO; bitpos: [9]; default: 0; - * Set this bit to disable function of usb switch to jtag in module of usb device. - */ - uint32_t dis_usb_jtag:1; - /** recovery_bootloader_flash_sector_2_2 : RO; bitpos: [10]; default: 0; - * Represents the starting flash sector (flash sector size is 0x1000) of the recovery - * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - * - this feature is disabled. - */ - uint32_t recovery_bootloader_flash_sector_2_2:1; - uint32_t reserved_11:1; - /** dis_force_download : RO; bitpos: [12]; default: 0; - * Set this bit to disable the function that forces chip into download mode. - */ - uint32_t dis_force_download:1; - /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; - * Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during - * boot_mode_download. - */ - uint32_t spi_download_mspi_dis:1; - /** dis_twai : RO; bitpos: [14]; default: 0; - * Set this bit to disable TWAI function. - */ - uint32_t dis_twai:1; - /** jtag_sel_enable : RO; bitpos: [15]; default: 0; - * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through - * strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0. - */ - uint32_t jtag_sel_enable:1; - /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; - * Set odd bits to disable JTAG in the soft way. JTAG can be enabled in HMAC module. - */ - uint32_t soft_dis_jtag:3; - /** dis_pad_jtag : RO; bitpos: [19]; default: 0; - * Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. - */ - uint32_t dis_pad_jtag:1; - /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; - * Set this bit to disable flash manual encrypt function (except in SPI boot mode). - */ - uint32_t dis_download_manual_encrypt:1; - /** recovery_bootloader_flash_sector_3_6 : RO; bitpos: [24:21]; default: 0; - * Represents the starting flash sector (flash sector size is 0x1000) of the recovery - * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - * - this feature is disabled. - */ - uint32_t recovery_bootloader_flash_sector_3_6:4; - /** usb_phy_sel : RO; bitpos: [25]; default: 0; - * 0: intphy(gpio24/25) <---> usb_device - * 1: intphy(26/27) <---> usb_otg11.1: intphy(gpio26/27) <---> usb_device - * 1: intphy(24/25) <---> usb_otg11. - */ - uint32_t usb_phy_sel:1; - /** huk_gen_state : RO; bitpos: [30:26]; default: 0; - * Set the bits to control validation of HUK generate mode. Odd of 1 is invalid, even - * of 1 is valid. - */ - uint32_t huk_gen_state:5; - /** recovery_bootloader_flash_sector_7_7 : RO; bitpos: [31]; default: 0; - * Represents the starting flash sector (flash sector size is 0x1000) of the recovery - * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - * - this feature is disabled. - */ - uint32_t recovery_bootloader_flash_sector_7_7:1; - }; - uint32_t val; -} efuse_rd_repeat_data0_reg_t; - -/** Type of rd_repeat_data1 register - * Represents rd_repeat_data - */ -typedef union { - struct { - /** recovery_bootloader_flash_sector_8_10 : RO; bitpos: [2:0]; default: 0; - * Represents the starting flash sector (flash sector size is 0x1000) of the recovery - * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - * - this feature is disabled. - */ - uint32_t recovery_bootloader_flash_sector_8_10:3; - /** recovery_bootloader_flash_sector_11_11 : RO; bitpos: [3]; default: 0; - * Represents the starting flash sector (flash sector size is 0x1000) of the recovery - * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - * - this feature is disabled. - */ - uint32_t recovery_bootloader_flash_sector_11_11:1; - /** km_rnd_switch_cycle : RO; bitpos: [4]; default: 0; - * Set the bits to control key manager random number switch cycle. 0: control by - * register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles - */ - uint32_t km_rnd_switch_cycle:1; - /** km_deploy_only_once : RO; bitpos: [8:5]; default: 0; - * EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: - * {EFUSE_KM_DEPLOY_ONLY_ONCE_H, EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to - * control whether corresponding key can only be deployed once. 1 is true, 0 is false. - * bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, bit4:psram - */ - uint32_t km_deploy_only_once:4; - /** force_use_key_manager_key : RO; bitpos: [12:9]; default: 0; - * EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form - * one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H, - * EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether - * corresponding key must come from key manager. 1 is true, 0 is false. bit 0: ecsda, - * bit 1: xts, bit2: hmac, bit3: ds, bit4:psram - */ - uint32_t force_use_key_manager_key:4; - /** force_disable_sw_init_key : RO; bitpos: [13]; default: 0; - * Set this bit to disable software written init key, and force use efuse_init_key. - */ - uint32_t force_disable_sw_init_key:1; - /** km_xts_key_length_256 : RO; bitpos: [14]; default: 0; - * Set this bit to config flash encryption xts-512 key, else use xts-256 key when - * using the key manager - */ - uint32_t km_xts_key_length_256:1; - /** ecc_force_const_time : RO; bitpos: [15]; default: 0; - * Set this bit to permanently turn on ECC const-time mode. - */ - uint32_t ecc_force_const_time:1; - uint32_t reserved_16:1; - /** wdt_delay_sel : RO; bitpos: [17]; default: 0; - * Select lp wdt timeout threshold at startup = initial timeout value * (2 ^ - * (EFUSE_WDT_DELAY_SEL + 1)) - */ - uint32_t wdt_delay_sel:1; - /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; - * Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even - * number of 1: disable. - */ - uint32_t spi_boot_crypt_cnt:3; - /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; - * Set this bit to enable revoking first secure boot key. - */ - uint32_t secure_boot_key_revoke0:1; - /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; - * Set this bit to enable revoking second secure boot key. - */ - uint32_t secure_boot_key_revoke1:1; - /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; - * Set this bit to enable revoking third secure boot key. - */ - uint32_t secure_boot_key_revoke2:1; - /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; - * Purpose of Key0. - */ - uint32_t key_purpose_0:4; - /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; - * Purpose of Key1. - */ - uint32_t key_purpose_1:4; - }; - uint32_t val; -} efuse_rd_repeat_data1_reg_t; - -/** Type of rd_repeat_data2 register - * Represents rd_repeat_data - */ -typedef union { - struct { - /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; - * Purpose of Key2. - */ - uint32_t key_purpose_2:4; - /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; - * Purpose of Key3. - */ - uint32_t key_purpose_3:4; - /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; - * Purpose of Key4. - */ - uint32_t key_purpose_4:4; - /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; - * Purpose of Key5. - */ - uint32_t key_purpose_5:4; - /** sec_dpa_level : RO; bitpos: [17:16]; default: 0; - * Configures the clock random divide mode to determine the dpa secure level - */ - uint32_t sec_dpa_level:2; - uint32_t reserved_18:1; - /** xts_dpa_clk_enable : RO; bitpos: [19]; default: 0; - * Sets this bit to enable xts clock anti-dpa attack function. - */ - uint32_t xts_dpa_clk_enable:1; - /** secure_boot_en : RO; bitpos: [20]; default: 0; - * Set this bit to enable secure boot. - */ - uint32_t secure_boot_en:1; - /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; - * Set this bit to enable revoking aggressive secure boot. - */ - uint32_t secure_boot_aggressive_revoke:1; - /** km_deploy_only_once_h : RO; bitpos: [22]; default: 0; - * EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: - * {EFUSE_KM_DEPLOY_ONLY_ONCE_H, EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to - * control whether corresponding key can only be deployed once. 1 is true, 0 is false. - * bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, bit4:psram - */ - uint32_t km_deploy_only_once_h:1; - /** force_use_key_manager_key_h : RO; bitpos: [23]; default: 0; - * EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form - * one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H, - * EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether - * corresponding key must come from key manager. 1 is true, 0 is false. bit 0: ecsda, - * bit 1: xts, bit2: hmac, bit3: ds, bit4:psram - */ - uint32_t force_use_key_manager_key_h:1; - uint32_t reserved_24:2; - /** flash_ecc_en : RO; bitpos: [26]; default: 0; - * Set this bit to enable ECC for flash boot. - */ - uint32_t flash_ecc_en:1; - /** dis_usb_otg_download_mode : RO; bitpos: [27]; default: 0; - * Set this bit to disable download via USB-OTG. - */ - uint32_t dis_usb_otg_download_mode:1; - /** flash_tpuw : RO; bitpos: [31:28]; default: 0; - * Configures flash waiting time after power-up, in unit of ms. When the value less - * than 15, the waiting time is the configurable value. Otherwise, the waiting time is - * 30. - */ - uint32_t flash_tpuw:4; - }; - uint32_t val; -} efuse_rd_repeat_data2_reg_t; - -/** Type of rd_repeat_data3 register - * Represents rd_repeat_data - */ -typedef union { - struct { - /** dis_download_mode : RO; bitpos: [0]; default: 0; - * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7). - */ - uint32_t dis_download_mode:1; - /** dis_direct_boot : RO; bitpos: [1]; default: 0; - * Set this bit to disable direct boot mode - */ - uint32_t dis_direct_boot:1; - /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; - * Set this bit to disable USB-Serial-JTAG print during rom boot. - */ - uint32_t dis_usb_serial_jtag_rom_print:1; - /** lock_km_key : RO; bitpos: [3]; default: 0; - * set this bit to lock the key manager key after deploy - */ - uint32_t lock_km_key:1; - /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; - * Set this bit to disable the USB-Serial-JTAG download function. - */ - uint32_t dis_usb_serial_jtag_download_mode:1; - /** enable_security_download : RO; bitpos: [5]; default: 0; - * Set this bit to enable security download mode. - */ - uint32_t enable_security_download:1; - /** uart_print_control : RO; bitpos: [7:6]; default: 0; - * Set the type of UART printing, 00: force enable printing, 01: enable printing when - * GPIO8 is reset at low level, 10: enable printing when GPIO8 is reset at high level, - * 11: force disable printing - */ - uint32_t uart_print_control:2; - /** force_send_resume : RO; bitpos: [8]; default: 0; - * Set this bit to force ROM code to send a resume command during SPI boot. - */ - uint32_t force_send_resume:1; - /** secure_version : RO; bitpos: [24:9]; default: 0; - * Secure version used by ESP-IDF anti-rollback feature. - */ - uint32_t secure_version:16; - /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0; - * Represents whether secure boot do fast verification on wake is disabled. 0: enabled - * 1: disabled - */ - uint32_t secure_boot_disable_fast_wake:1; - /** hys_en_pad : RO; bitpos: [26]; default: 0; - * Set bits to enable hysteresis function of PAD0~27 - */ - uint32_t hys_en_pad:1; - /** key_purpose_0_h : RO; bitpos: [27]; default: 0; - * Purpose of Key0. The 5-th bit. - */ - uint32_t key_purpose_0_h:1; - /** key_purpose_1_h : RO; bitpos: [28]; default: 0; - * Purpose of Key1. The 5-th bit. - */ - uint32_t key_purpose_1_h:1; - /** key_purpose_2_h : RO; bitpos: [29]; default: 0; - * Purpose of Key2. The 5-th bit. - */ - uint32_t key_purpose_2_h:1; - /** key_purpose_3_h : RO; bitpos: [30]; default: 0; - * Purpose of Key3. The 5-th bit. - */ - uint32_t key_purpose_3_h:1; - /** key_purpose_4_h : RO; bitpos: [31]; default: 0; - * Purpose of Key4. The 5-th bit. - */ - uint32_t key_purpose_4_h:1; - }; - uint32_t val; -} efuse_rd_repeat_data3_reg_t; - -/** Type of rd_repeat_data4 register - * Represents rd_repeat_data - */ -typedef union { - struct { - /** pxa0_tieh_sel_0 : RO; bitpos: [1:0]; default: 0; - * Output LDO VO0 tieh source select. 0: 1'b1 1: sdmmc1 2: reg 3:sdmmc0 - */ - uint32_t pxa0_tieh_sel_0:2; - /** pvt_glitch_en : RO; bitpos: [2]; default: 0; - * Represents whether to enable PVT power glitch monitor function. - * 1:Enable. - * 0:Disable - */ - uint32_t pvt_glitch_en:1; - uint32_t reserved_3:1; - /** key_purpose_5_h : RO; bitpos: [4]; default: 0; - * Purpose of Key5. The 5-th bit. - */ - uint32_t key_purpose_5_h:1; - uint32_t reserved_5:2; - /** km_disable_deploy_mode_h : RO; bitpos: [7]; default: 0; - * EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one - * field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H, EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set - * each bit to control whether corresponding key's deploy mode of new value deployment - * is disabled. 1 is true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, - * bit4:psram - */ - uint32_t km_disable_deploy_mode_h:1; - /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0; - * EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one - * field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H, EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set - * each bit to control whether corresponding key's deploy mode of new value deployment - * is disabled. 1 is true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, - * bit4:psram - */ - uint32_t km_disable_deploy_mode:4; - uint32_t reserved_12:4; - /** xts_dpa_pseudo_level : RO; bitpos: [17:16]; default: 0; - * Sets this bit to control the xts pseudo-round anti-dpa attack function. 0: - * controlled by register. 1-3: the higher the value is, the more pseudo-rounds are - * inserted to the xts-aes calculation - */ - uint32_t xts_dpa_pseudo_level:2; - /** hp_pwr_src_sel : RO; bitpos: [18]; default: 0; - * HP system power source select. 0:LDO 1: DCDC - */ - uint32_t hp_pwr_src_sel:1; - /** secure_boot_sha384_en : RO; bitpos: [19]; default: 0; - * Represents whether secure boot using SHA-384 is enabled. 0: disable 1: enable - */ - uint32_t secure_boot_sha384_en:1; - /** dis_wdt : RO; bitpos: [20]; default: 0; - * Set this bit to disable watch dog. - */ - uint32_t dis_wdt:1; - /** dis_swd : RO; bitpos: [21]; default: 0; - * Set bit to disable super-watchdog - */ - uint32_t dis_swd:1; - /** pvt_glitch_mode : RO; bitpos: [23:22]; default: 0; - * Use to configure glitch mode - */ - uint32_t pvt_glitch_mode:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} efuse_rd_repeat_data4_reg_t; - - -/** Group: block1 registers */ -/** Type of rd_mac_sys0 register - * Represents rd_mac_sys - */ -typedef union { - struct { - /** mac_0 : RO; bitpos: [31:0]; default: 0; - * Represents MAC address. Low 32-bit. - */ - uint32_t mac_0:32; - }; - uint32_t val; -} efuse_rd_mac_sys0_reg_t; - -/** Type of rd_mac_sys1 register - * Represents rd_mac_sys - */ -typedef union { - struct { - /** mac_1 : RO; bitpos: [15:0]; default: 0; - * Represents MAC address. High 16-bit. - */ - uint32_t mac_1:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} efuse_rd_mac_sys1_reg_t; - -/** Type of rd_mac_sys3 register - * Represents rd_mac_sys - */ -typedef union { - struct { - uint32_t reserved_0:18; - /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; - * Represents the first 14-bit of zeroth part of system data. - */ - uint32_t sys_data_part0_0:14; - }; - uint32_t val; -} efuse_rd_mac_sys3_reg_t; - -/** Type of rd_mac_sys4 register - * Represents rd_mac_sys - */ -typedef union { - struct { - /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0; - * Represents the second 32-bit of zeroth part of system data. - */ - uint32_t sys_data_part0_1:32; - }; - uint32_t val; -} efuse_rd_mac_sys4_reg_t; - -/** Type of rd_mac_sys5 register - * Represents rd_mac_sys - */ -typedef union { - struct { - /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; - * Represents the third 32-bit of zeroth part of system data. - */ - uint32_t sys_data_part0_2:32; - }; - uint32_t val; -} efuse_rd_mac_sys5_reg_t; - - -/** Group: block2 registers */ -/** Type of rd_sys_part1_datan register - * Represents rd_sys_part1_datan - */ -typedef union { - struct { - /** sys_data_part1_n : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. - */ - uint32_t sys_data_part1_n:32; - }; - uint32_t val; -} efuse_rd_sys_part1_datan_reg_t; - - -/** Group: block3 registers */ -/** Type of rd_usr_datan register - * Represents rd_usr_datan - */ -typedef union { - struct { - /** usr_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of block3 (user). - */ - uint32_t usr_datan:32; - }; - uint32_t val; -} efuse_rd_usr_datan_reg_t; - - -/** Group: block4 registers */ -/** Type of rd_key0_datan register - * Represents rd_key0_datan - */ -typedef union { - struct { - /** key0_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key0. - */ - uint32_t key0_datan:32; - }; - uint32_t val; -} efuse_rd_key0_datan_reg_t; - - -/** Group: block5 registers */ -/** Type of rd_key1_datan register - * Represents rd_key1_datan - */ -typedef union { - struct { - /** key1_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key1. - */ - uint32_t key1_datan:32; - }; - uint32_t val; -} efuse_rd_key1_datan_reg_t; - - -/** Group: block6 registers */ -/** Type of rd_key2_datan register - * Represents rd_key2_datan - */ -typedef union { - struct { - /** key2_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key2. - */ - uint32_t key2_datan:32; - }; - uint32_t val; -} efuse_rd_key2_datan_reg_t; - - -/** Group: block7 registers */ -/** Type of rd_key3_datan register - * Represents rd_key3_datan - */ -typedef union { - struct { - /** key3_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key3. - */ - uint32_t key3_datan:32; - }; - uint32_t val; -} efuse_rd_key3_datan_reg_t; - - -/** Group: block8 registers */ -/** Type of rd_key4_datan register - * Represents rd_key4_datan - */ -typedef union { - struct { - /** key4_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key4. - */ - uint32_t key4_datan:32; - }; - uint32_t val; -} efuse_rd_key4_datan_reg_t; - - -/** Group: block9 registers */ -/** Type of rd_key5_datan register - * Represents rd_key5_datan - */ -typedef union { - struct { - /** key5_datan : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of key5. - */ - uint32_t key5_datan:32; - }; - uint32_t val; -} efuse_rd_key5_datan_reg_t; - - -/** Group: block10 registers */ -/** Type of rd_sys_part2_data0 register - * Represents rd_sys_part2_data - */ -typedef union { - struct { - /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; - * Represents the first 32-bit of second part of system data. - */ - uint32_t sys_data_part2_0:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data0_reg_t; - -/** Type of rd_sys_part2_data1 register - * Represents rd_sys_part2_data - */ -typedef union { - struct { - /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; - * Represents the first 32-bit of second part of system data. - */ - uint32_t sys_data_part2_1:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data1_reg_t; - -/** Type of rd_sys_part2_data2 register - * Represents rd_sys_part2_data - */ -typedef union { - struct { - /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; - * Represents the second 32-bit of second part of system data. - */ - uint32_t sys_data_part2_2:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data2_reg_t; - -/** Type of rd_sys_part2_data3 register - * Represents rd_sys_part2_data - */ -typedef union { - struct { - /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; - * Represents the third 32-bit of second part of system data. - */ - uint32_t sys_data_part2_3:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data3_reg_t; - -/** Type of rd_sys_part2_data4 register - * Represents rd_sys_part2_data - */ -typedef union { - struct { - /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; - * Represents the fourth 32-bit of second part of system data. - */ - uint32_t sys_data_part2_4:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data4_reg_t; - -/** Type of rd_sys_part2_data5 register - * Represents rd_sys_part2_data - */ -typedef union { - struct { - /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; - * Represents the fifth 32-bit of second part of system data. - */ - uint32_t sys_data_part2_5:32; - }; - uint32_t val; -} efuse_rd_sys_part2_data5_reg_t; - -/** Type of rd_sys_part2_data7 register - * Represents rd_sys_part2_data - */ -typedef union { - struct { - uint32_t reserved_0:4; - /** usb_device_exchg_pins : RO; bitpos: [4]; default: 0; - * Enable usb device exchange pins of D+ and D-. - */ - uint32_t usb_device_exchg_pins:1; - /** usb_otg11_exchg_pins : RO; bitpos: [5]; default: 0; - * Enable usb otg11 exchange pins of D+ and D-. - */ - uint32_t usb_otg11_exchg_pins:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} efuse_rd_sys_part2_data7_reg_t; - - -/** Group: block0 error report registers */ -/** Type of rd_repeat_data_err0 register - * Represents rd_repeat_data_err - */ -typedef union { - struct { - /** rd_dis_err : RO; bitpos: [6:0]; default: 0; - * Represents the programming error of EFUSE_RD_DIS - */ - uint32_t rd_dis_err:7; - /** recovery_bootloader_flash_sector_0_1_err : RO; bitpos: [8:7]; default: 0; - * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1 - */ - uint32_t recovery_bootloader_flash_sector_0_1_err:2; - /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_JTAG - */ - uint32_t dis_usb_jtag_err:1; - /** recovery_bootloader_flash_sector_2_2_err : RO; bitpos: [10]; default: 0; - * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2 - */ - uint32_t recovery_bootloader_flash_sector_2_2_err:1; - uint32_t reserved_11:1; - /** dis_force_download_err : RO; bitpos: [12]; default: 0; - * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD - */ - uint32_t dis_force_download_err:1; - /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0; - * Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS - */ - uint32_t spi_download_mspi_dis_err:1; - /** dis_twai_err : RO; bitpos: [14]; default: 0; - * Represents the programming error of EFUSE_DIS_TWAI - */ - uint32_t dis_twai_err:1; - /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; - * Represents the programming error of EFUSE_JTAG_SEL_ENABLE - */ - uint32_t jtag_sel_enable_err:1; - /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; - * Represents the programming error of EFUSE_SOFT_DIS_JTAG - */ - uint32_t soft_dis_jtag_err:3; - /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; - * Represents the programming error of EFUSE_DIS_PAD_JTAG - */ - uint32_t dis_pad_jtag_err:1; - /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; - * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT - */ - uint32_t dis_download_manual_encrypt_err:1; - /** recovery_bootloader_flash_sector_3_6_err : RO; bitpos: [24:21]; default: 0; - * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6 - */ - uint32_t recovery_bootloader_flash_sector_3_6_err:4; - /** usb_phy_sel_err : RO; bitpos: [25]; default: 0; - * Represents the programming error of EFUSE_USB_PHY_SEL - */ - uint32_t usb_phy_sel_err:1; - /** huk_gen_state_err : RO; bitpos: [30:26]; default: 0; - * Represents the programming error of EFUSE_HUK_GEN_STATE - */ - uint32_t huk_gen_state_err:5; - /** recovery_bootloader_flash_sector_7_7_err : RO; bitpos: [31]; default: 0; - * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7 - */ - uint32_t recovery_bootloader_flash_sector_7_7_err:1; - }; - uint32_t val; -} efuse_rd_repeat_data_err0_reg_t; - -/** Type of rd_repeat_data_err1 register - * Represents rd_repeat_data_err - */ -typedef union { - struct { - /** recovery_bootloader_flash_sector_8_10_err : RO; bitpos: [2:0]; default: 0; - * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10 - */ - uint32_t recovery_bootloader_flash_sector_8_10_err:3; - /** recovery_bootloader_flash_sector_11_11_err : RO; bitpos: [3]; default: 0; - * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11 - */ - uint32_t recovery_bootloader_flash_sector_11_11_err:1; - /** km_rnd_switch_cycle_err : RO; bitpos: [4]; default: 0; - * Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE - */ - uint32_t km_rnd_switch_cycle_err:1; - /** km_deploy_only_once_err : RO; bitpos: [8:5]; default: 0; - * Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE - */ - uint32_t km_deploy_only_once_err:4; - /** force_use_key_manager_key_err : RO; bitpos: [12:9]; default: 0; - * Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY - */ - uint32_t force_use_key_manager_key_err:4; - /** force_disable_sw_init_key_err : RO; bitpos: [13]; default: 0; - * Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY - */ - uint32_t force_disable_sw_init_key_err:1; - /** km_xts_key_length_256_err : RO; bitpos: [14]; default: 0; - * Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256 - */ - uint32_t km_xts_key_length_256_err:1; - /** ecc_force_const_time_err : RO; bitpos: [15]; default: 0; - * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME - */ - uint32_t ecc_force_const_time_err:1; - uint32_t reserved_16:1; - /** wdt_delay_sel_err : RO; bitpos: [17]; default: 0; - * Represents the programming error of EFUSE_WDT_DELAY_SEL - */ - uint32_t wdt_delay_sel_err:1; - /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; - * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT - */ - uint32_t spi_boot_crypt_cnt_err:3; - /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 - */ - uint32_t secure_boot_key_revoke0_err:1; - /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 - */ - uint32_t secure_boot_key_revoke1_err:1; - /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 - */ - uint32_t secure_boot_key_revoke2_err:1; - /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_0 - */ - uint32_t key_purpose_0_err:4; - /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_1 - */ - uint32_t key_purpose_1_err:4; - }; - uint32_t val; -} efuse_rd_repeat_data_err1_reg_t; - -/** Type of rd_repeat_data_err2 register - * Represents rd_repeat_data_err - */ -typedef union { - struct { - /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_2 - */ - uint32_t key_purpose_2_err:4; - /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_3 - */ - uint32_t key_purpose_3_err:4; - /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_4 - */ - uint32_t key_purpose_4_err:4; - /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_5 - */ - uint32_t key_purpose_5_err:4; - /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0; - * Represents the programming error of EFUSE_SEC_DPA_LEVEL - */ - uint32_t sec_dpa_level_err:2; - uint32_t reserved_18:1; - /** xts_dpa_clk_enable_err : RO; bitpos: [19]; default: 0; - * Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE - */ - uint32_t xts_dpa_clk_enable_err:1; - /** secure_boot_en_err : RO; bitpos: [20]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_EN - */ - uint32_t secure_boot_en_err:1; - /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE - */ - uint32_t secure_boot_aggressive_revoke_err:1; - /** km_deploy_only_once_h_err : RO; bitpos: [22]; default: 0; - * Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE_H - */ - uint32_t km_deploy_only_once_h_err:1; - /** force_use_key_manager_key_h_err : RO; bitpos: [23]; default: 0; - * Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY_H - */ - uint32_t force_use_key_manager_key_h_err:1; - uint32_t reserved_24:2; - /** flash_ecc_en_err : RO; bitpos: [26]; default: 0; - * Represents the programming error of EFUSE_FLASH_ECC_EN - */ - uint32_t flash_ecc_en_err:1; - /** dis_usb_otg_download_mode_err : RO; bitpos: [27]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_OTG_DOWNLOAD_MODE - */ - uint32_t dis_usb_otg_download_mode_err:1; - /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; - * Represents the programming error of EFUSE_FLASH_TPUW - */ - uint32_t flash_tpuw_err:4; - }; - uint32_t val; -} efuse_rd_repeat_data_err2_reg_t; - -/** Type of rd_repeat_data_err3 register - * Represents rd_repeat_data_err - */ -typedef union { - struct { - /** dis_download_mode_err : RO; bitpos: [0]; default: 0; - * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE - */ - uint32_t dis_download_mode_err:1; - /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; - * Represents the programming error of EFUSE_DIS_DIRECT_BOOT - */ - uint32_t dis_direct_boot_err:1; - /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT - */ - uint32_t dis_usb_serial_jtag_rom_print_err:1; - /** lock_km_key_err : RO; bitpos: [3]; default: 0; - * Represents the programming error of EFUSE_LOCK_KM_KEY - */ - uint32_t lock_km_key_err:1; - /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0; - * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE - */ - uint32_t dis_usb_serial_jtag_download_mode_err:1; - /** enable_security_download_err : RO; bitpos: [5]; default: 0; - * Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD - */ - uint32_t enable_security_download_err:1; - /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; - * Represents the programming error of EFUSE_UART_PRINT_CONTROL - */ - uint32_t uart_print_control_err:2; - /** force_send_resume_err : RO; bitpos: [8]; default: 0; - * Represents the programming error of EFUSE_FORCE_SEND_RESUME - */ - uint32_t force_send_resume_err:1; - /** secure_version_err : RO; bitpos: [24:9]; default: 0; - * Represents the programming error of EFUSE_SECURE_VERSION - */ - uint32_t secure_version_err:16; - /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE - */ - uint32_t secure_boot_disable_fast_wake_err:1; - /** hys_en_pad_err : RO; bitpos: [26]; default: 0; - * Represents the programming error of EFUSE_HYS_EN_PAD - */ - uint32_t hys_en_pad_err:1; - /** key_purpose_0_h_err : RO; bitpos: [27]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_0_H - */ - uint32_t key_purpose_0_h_err:1; - /** key_purpose_1_h_err : RO; bitpos: [28]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_1_H - */ - uint32_t key_purpose_1_h_err:1; - /** key_purpose_2_h_err : RO; bitpos: [29]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_2_H - */ - uint32_t key_purpose_2_h_err:1; - /** key_purpose_3_h_err : RO; bitpos: [30]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_3_H - */ - uint32_t key_purpose_3_h_err:1; - /** key_purpose_4_h_err : RO; bitpos: [31]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_4_H - */ - uint32_t key_purpose_4_h_err:1; - }; - uint32_t val; -} efuse_rd_repeat_data_err3_reg_t; - -/** Type of rd_repeat_data_err4 register - * Represents rd_repeat_data_err - */ -typedef union { - struct { - /** pxa0_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0; - * Represents the programming error of 0PXA_TIEH_SEL_0 - */ - uint32_t pxa0_tieh_sel_0_err:2; - /** pvt_glitch_en_err : RO; bitpos: [2]; default: 0; - * Represents the programming error of EFUSE_PVT_GLITCH_EN - */ - uint32_t pvt_glitch_en_err:1; - uint32_t reserved_3:1; - /** key_purpose_5_h_err : RO; bitpos: [4]; default: 0; - * Represents the programming error of EFUSE_KEY_PURPOSE_5_H - */ - uint32_t key_purpose_5_h_err:1; - uint32_t reserved_5:2; - /** km_disable_deploy_mode_h_err : RO; bitpos: [7]; default: 0; - * Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE_H - */ - uint32_t km_disable_deploy_mode_h_err:1; - /** km_disable_deploy_mode_err : RO; bitpos: [11:8]; default: 0; - * Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE - */ - uint32_t km_disable_deploy_mode_err:4; - uint32_t reserved_12:4; - /** xts_dpa_pseudo_level_err : RO; bitpos: [17:16]; default: 0; - * Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL - */ - uint32_t xts_dpa_pseudo_level_err:2; - /** hp_pwr_src_sel_err : RO; bitpos: [18]; default: 0; - * Represents the programming error of EFUSE_HP_PWR_SRC_SEL - */ - uint32_t hp_pwr_src_sel_err:1; - /** secure_boot_sha384_en_err : RO; bitpos: [19]; default: 0; - * Represents the programming error of EFUSE_SECURE_BOOT_SHA384_EN - */ - uint32_t secure_boot_sha384_en_err:1; - /** dis_wdt_err : RO; bitpos: [20]; default: 0; - * Represents the programming error of EFUSE_DIS_WDT - */ - uint32_t dis_wdt_err:1; - /** dis_swd_err : RO; bitpos: [21]; default: 0; - * Represents the programming error of EFUSE_DIS_SWD - */ - uint32_t dis_swd_err:1; - /** pvt_glitch_mode_err : RO; bitpos: [23:22]; default: 0; - * Represents the programming error of EFUSE_PVT_GLITCH_MODE - */ - uint32_t pvt_glitch_mode_err:2; - uint32_t reserved_24:8; - }; - uint32_t val; -} efuse_rd_repeat_data_err4_reg_t; - - -/** Group: EFUSE ECDSA Configure Registers */ -/** Type of ecdsa register - * eFuse status register. - */ -typedef union { - struct { - /** cfg_ecdsa_p192_blk : R/W; bitpos: [3:0]; default: 0; - * Configures which block to use for ECDSA P192 key output. - */ - uint32_t cfg_ecdsa_p192_blk:4; - /** cfg_ecdsa_p256_blk : R/W; bitpos: [7:4]; default: 0; - * Configures which block to use for ECDSA P256 key output. - */ - uint32_t cfg_ecdsa_p256_blk:4; - /** cfg_ecdsa_p384_l_blk : R/W; bitpos: [11:8]; default: 0; - * Configures which block to use for ECDSA P384 key low part output. - */ - uint32_t cfg_ecdsa_p384_l_blk:4; - /** cfg_ecdsa_p384_h_blk : R/W; bitpos: [15:12]; default: 0; - * Configures which block to use for ECDSA P256 key high part output. - */ - uint32_t cfg_ecdsa_p384_h_blk:4; - /** cur_ecdsa_p192_blk : RO; bitpos: [19:16]; default: 0; - * Represents which block is used for ECDSA P192 key output. - */ - uint32_t cur_ecdsa_p192_blk:4; - /** cur_ecdsa_p256_blk : RO; bitpos: [23:20]; default: 0; - * Represents which block is used for ECDSA P256 key output. - */ - uint32_t cur_ecdsa_p256_blk:4; - /** cur_ecdsa_p384_l_blk : RO; bitpos: [27:24]; default: 0; - * Represents which block is used for ECDSA P384 key low part output. - */ - uint32_t cur_ecdsa_p384_l_blk:4; - /** cur_ecdsa_p384_h_blk : RO; bitpos: [31:28]; default: 0; - * Represents which block is used for ECDSA P384 key high part output. - */ - uint32_t cur_ecdsa_p384_h_blk:4; - }; - uint32_t val; -} efuse_ecdsa_reg_t; - - -/** Group: RS block error report registers */ -/** Type of rd_rs_data_err0 register - * Represents rd_rs_data_err - */ -typedef union { - struct { - /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_mac_sys - */ - uint32_t rd_mac_sys_err_num:3; - /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_mac_sys is reliable - * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. - */ - uint32_t rd_mac_sys_fail:1; - /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part1_data - */ - uint32_t rd_sys_part1_data_err_num:3; - /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part1_data is reliable - * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is - * over 6. - */ - uint32_t rd_sys_part1_data_fail:1; - /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_usr_data - */ - uint32_t rd_usr_data_err_num:3; - /** rd_usr_data_fail : RO; bitpos: [11]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_usr_data is reliable - * 1: Means that programming rd_usr_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_usr_data_fail:1; - /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key0_data - */ - uint32_t rd_key0_data_err_num:3; - /** rd_key0_data_fail : RO; bitpos: [15]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key0_data is reliable - * 1: Means that programming rd_key0_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key0_data_fail:1; - /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key1_data - */ - uint32_t rd_key1_data_err_num:3; - /** rd_key1_data_fail : RO; bitpos: [19]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key1_data is reliable - * 1: Means that programming rd_key1_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key1_data_fail:1; - /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key2_data - */ - uint32_t rd_key2_data_err_num:3; - /** rd_key2_data_fail : RO; bitpos: [23]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key2_data is reliable - * 1: Means that programming rd_key2_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key2_data_fail:1; - /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key3_data - */ - uint32_t rd_key3_data_err_num:3; - /** rd_key3_data_fail : RO; bitpos: [27]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key3_data is reliable - * 1: Means that programming rd_key3_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key3_data_fail:1; - /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key4_data - */ - uint32_t rd_key4_data_err_num:3; - /** rd_key4_data_fail : RO; bitpos: [31]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key4_data is reliable - * 1: Means that programming rd_key4_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key4_data_fail:1; - }; - uint32_t val; -} efuse_rd_rs_data_err0_reg_t; - -/** Type of rd_rs_data_err1 register - * Represents rd_rs_data_err - */ -typedef union { - struct { - /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_key5_data - */ - uint32_t rd_key5_data_err_num:3; - /** rd_key5_data_fail : RO; bitpos: [3]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_key5_data is reliable - * 1: Means that programming rd_key5_data failed and the number of error bytes is over - * 6. - */ - uint32_t rd_key5_data_fail:1; - /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers. - * The value of this signal means the number of error bytes in rd_sys_part2_data - */ - uint32_t rd_sys_part2_data_err_num:3; - /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0; - * Represents error status of register. - * 0: Means no failure and that the data of rd_sys_part2_data is reliable - * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is - * over 6. - */ - uint32_t rd_sys_part2_data_fail:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} efuse_rd_rs_data_err1_reg_t; - - -/** Group: ******** Registers */ -/** Type of clk register - * eFuse clcok configuration register. - */ -typedef union { - struct { - /** mem_force_pd : R/W; bitpos: [0]; default: 0; - * Set this bit to force eFuse SRAM into power-saving mode. - */ - uint32_t mem_force_pd:1; - /** mem_clk_force_on : R/W; bitpos: [1]; default: 0; - * Set this bit and force to activate clock signal of eFuse SRAM. - */ - uint32_t mem_clk_force_on:1; - /** mem_force_pu : R/W; bitpos: [2]; default: 0; - * Set this bit to force eFuse SRAM into working mode. - */ - uint32_t mem_force_pu:1; - uint32_t reserved_3:13; - /** clk_en : R/W; bitpos: [16]; default: 0; - * Set this bit to force enable eFuse register configuration clock signal. - */ - uint32_t clk_en:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} efuse_clk_reg_t; - -/** Type of conf register - * eFuse operation mode configuration register - */ -typedef union { - struct { - /** op_code : R/W; bitpos: [15:0]; default: 0; - * 0x5A5A: programming operation command 0x5AA5: read operation command. - */ - uint32_t op_code:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} efuse_conf_reg_t; - -/** Type of status register - * eFuse status register. - */ -typedef union { - struct { - /** state : RO; bitpos: [3:0]; default: 0; - * Indicates the state of the eFuse state machine. - */ - uint32_t state:4; - uint32_t reserved_4:6; - /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; - * Indicates the number of block valid bit. - */ - uint32_t blk0_valid_bit_cnt:10; - uint32_t reserved_20:12; - }; - uint32_t val; -} efuse_status_reg_t; - -/** Type of cmd register - * eFuse command register. - */ -typedef union { - struct { - /** read_cmd : R/W/SC; bitpos: [0]; default: 0; - * Set this bit to send read command. - */ - uint32_t read_cmd:1; - /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; - * Set this bit to send programming command. - */ - uint32_t pgm_cmd:1; - /** blk_num : R/W; bitpos: [5:2]; default: 0; - * The serial number of the block to be programmed. Value 0-10 corresponds to block - * number 0-10, respectively. - */ - uint32_t blk_num:4; - uint32_t reserved_6:26; - }; - uint32_t val; -} efuse_cmd_reg_t; - -/** Type of int_raw register - * eFuse raw interrupt register. - */ -typedef union { - struct { - /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0; - * The raw bit signal for read_done interrupt. - */ - uint32_t read_done_int_raw:1; - /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0; - * The raw bit signal for pgm_done interrupt. - */ - uint32_t pgm_done_int_raw:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_raw_reg_t; - -/** Type of int_st register - * eFuse interrupt status register. - */ -typedef union { - struct { - /** read_done_int_st : RO; bitpos: [0]; default: 0; - * The status signal for read_done interrupt. - */ - uint32_t read_done_int_st:1; - /** pgm_done_int_st : RO; bitpos: [1]; default: 0; - * The status signal for pgm_done interrupt. - */ - uint32_t pgm_done_int_st:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_st_reg_t; - -/** Type of int_ena register - * eFuse interrupt enable register. - */ -typedef union { - struct { - /** read_done_int_ena : R/W; bitpos: [0]; default: 0; - * The enable signal for read_done interrupt. - */ - uint32_t read_done_int_ena:1; - /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; - * The enable signal for pgm_done interrupt. - */ - uint32_t pgm_done_int_ena:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_ena_reg_t; - -/** Type of int_clr register - * eFuse interrupt clear register. - */ -typedef union { - struct { - /** read_done_int_clr : WT; bitpos: [0]; default: 0; - * The clear signal for read_done interrupt. - */ - uint32_t read_done_int_clr:1; - /** pgm_done_int_clr : WT; bitpos: [1]; default: 0; - * The clear signal for pgm_done interrupt. - */ - uint32_t pgm_done_int_clr:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} efuse_int_clr_reg_t; - -/** Type of dac_conf register - * Controls the eFuse programming voltage. - */ -typedef union { - struct { - /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; - * Controls the division factor of the rising clock of the programming voltage. - */ - uint32_t dac_clk_div:8; - /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; - * Don't care. - */ - uint32_t dac_clk_pad_sel:1; - /** dac_num : R/W; bitpos: [16:9]; default: 255; - * Controls the rising period of the programming voltage. - */ - uint32_t dac_num:8; - /** oe_clr : R/W; bitpos: [17]; default: 0; - * Reduces the power supply of the programming voltage. - */ - uint32_t oe_clr:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} efuse_dac_conf_reg_t; - -/** Type of rd_tim_conf register - * Configures read timing parameters. - */ -typedef union { - struct { - /** thr_a : R/W; bitpos: [7:0]; default: 1; - * Configures the read hold time. - */ - uint32_t thr_a:8; - /** trd : R/W; bitpos: [15:8]; default: 2; - * Configures the read time. - */ - uint32_t trd:8; - /** tsur_a : R/W; bitpos: [23:16]; default: 1; - * Configures the read setup time. - */ - uint32_t tsur_a:8; - /** read_init_num : R/W; bitpos: [31:24]; default: 15; - * Configures the waiting time of reading eFuse memory. - */ - uint32_t read_init_num:8; - }; - uint32_t val; -} efuse_rd_tim_conf_reg_t; - -/** Type of wr_tim_conf1 register - * Configurarion register 1 of eFuse programming timing parameters. - */ -typedef union { - struct { - /** tsup_a : R/W; bitpos: [7:0]; default: 1; - * Configures the programming setup time. - */ - uint32_t tsup_a:8; - /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831; - * Configures the power up time for VDDQ. - */ - uint32_t pwr_on_num:16; - /** thp_a : R/W; bitpos: [31:24]; default: 1; - * Configures the programming hold time. - */ - uint32_t thp_a:8; - }; - uint32_t val; -} efuse_wr_tim_conf1_reg_t; - -/** Type of wr_tim_conf2 register - * Configurarion register 2 of eFuse programming timing parameters. - */ -typedef union { - struct { - /** pwr_off_num : R/W; bitpos: [15:0]; default: 320; - * Configures the power outage time for VDDQ. - */ - uint32_t pwr_off_num:16; - /** tpgm : R/W; bitpos: [31:16]; default: 160; - * Configures the active programming time. - */ - uint32_t tpgm:16; - }; - uint32_t val; -} efuse_wr_tim_conf2_reg_t; - -/** Type of wr_tim_conf0_rs_bypass register - * Configurarion register0 of eFuse programming time parameters and rs bypass - * operation. - */ -typedef union { - struct { - /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; - * Set this bit to bypass reed solomon correction step. - */ - uint32_t bypass_rs_correction:1; - /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; - * Configures block number of programming twice operation. - */ - uint32_t bypass_rs_blk_num:11; - /** update : WT; bitpos: [12]; default: 0; - * Set this bit to update multi-bit register signals. - */ - uint32_t update:1; - /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; - * Configures the inactive programming time. - */ - uint32_t tpgm_inactive:8; - uint32_t reserved_21:11; - }; - uint32_t val; -} efuse_wr_tim_conf0_rs_bypass_reg_t; - - -/** Group: EFUSE Version Register */ -/** Type of date register - * eFuse version register. - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 38805904; - * Stores eFuse version. - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} efuse_date_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Write Disable Data */ -/** Type of apb2otp_wr_dis register - * eFuse apb2otp block0 data register1. - */ -typedef union { - struct { - /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0; - * Otp block0 write disable data. - */ - uint32_t apb2otp_block0_wr_dis:32; - }; - uint32_t val; -} efuse_apb2otp_wr_dis_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */ -/** Type of apb2otp_blk0_backup1_w1 register - * eFuse apb2otp block0 data register2. - */ -typedef union { - struct { - /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word1 data. - */ - uint32_t apb2otp_block0_backup1_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup1_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */ -/** Type of apb2otp_blk0_backup1_w2 register - * eFuse apb2otp block0 data register3. - */ -typedef union { - struct { - /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word2 data. - */ - uint32_t apb2otp_block0_backup1_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup1_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */ -/** Type of apb2otp_blk0_backup1_w3 register - * eFuse apb2otp block0 data register4. - */ -typedef union { - struct { - /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word3 data. - */ - uint32_t apb2otp_block0_backup1_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup1_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */ -/** Type of apb2otp_blk0_backup1_w4 register - * eFuse apb2otp block0 data register5. - */ -typedef union { - struct { - /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word4 data. - */ - uint32_t apb2otp_block0_backup1_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup1_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */ -/** Type of apb2otp_blk0_backup1_w5 register - * eFuse apb2otp block0 data register6. - */ -typedef union { - struct { - /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup1 word5 data. - */ - uint32_t apb2otp_block0_backup1_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup1_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */ -/** Type of apb2otp_blk0_backup2_w1 register - * eFuse apb2otp block0 data register7. - */ -typedef union { - struct { - /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word1 data. - */ - uint32_t apb2otp_block0_backup2_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup2_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */ -/** Type of apb2otp_blk0_backup2_w2 register - * eFuse apb2otp block0 data register8. - */ -typedef union { - struct { - /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word2 data. - */ - uint32_t apb2otp_block0_backup2_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup2_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */ -/** Type of apb2otp_blk0_backup2_w3 register - * eFuse apb2otp block0 data register9. - */ -typedef union { - struct { - /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word3 data. - */ - uint32_t apb2otp_block0_backup2_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup2_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */ -/** Type of apb2otp_blk0_backup2_w4 register - * eFuse apb2otp block0 data register10. - */ -typedef union { - struct { - /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word4 data. - */ - uint32_t apb2otp_block0_backup2_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup2_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */ -/** Type of apb2otp_blk0_backup2_w5 register - * eFuse apb2otp block0 data register11. - */ -typedef union { - struct { - /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup2 word5 data. - */ - uint32_t apb2otp_block0_backup2_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup2_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */ -/** Type of apb2otp_blk0_backup3_w1 register - * eFuse apb2otp block0 data register12. - */ -typedef union { - struct { - /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word1 data. - */ - uint32_t apb2otp_block0_backup3_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup3_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */ -/** Type of apb2otp_blk0_backup3_w2 register - * eFuse apb2otp block0 data register13. - */ -typedef union { - struct { - /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word2 data. - */ - uint32_t apb2otp_block0_backup3_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup3_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */ -/** Type of apb2otp_blk0_backup3_w3 register - * eFuse apb2otp block0 data register14. - */ -typedef union { - struct { - /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word3 data. - */ - uint32_t apb2otp_block0_backup3_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup3_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */ -/** Type of apb2otp_blk0_backup3_w4 register - * eFuse apb2otp block0 data register15. - */ -typedef union { - struct { - /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word4 data. - */ - uint32_t apb2otp_block0_backup3_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup3_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */ -/** Type of apb2otp_blk0_backup3_w5 register - * eFuse apb2otp block0 data register16. - */ -typedef union { - struct { - /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup3 word5 data. - */ - uint32_t apb2otp_block0_backup3_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup3_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */ -/** Type of apb2otp_blk0_backup4_w1 register - * eFuse apb2otp block0 data register17. - */ -typedef union { - struct { - /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word1 data. - */ - uint32_t apb2otp_block0_backup4_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup4_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */ -/** Type of apb2otp_blk0_backup4_w2 register - * eFuse apb2otp block0 data register18. - */ -typedef union { - struct { - /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word2 data. - */ - uint32_t apb2otp_block0_backup4_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup4_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */ -/** Type of apb2otp_blk0_backup4_w3 register - * eFuse apb2otp block0 data register19. - */ -typedef union { - struct { - /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word3 data. - */ - uint32_t apb2otp_block0_backup4_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup4_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */ -/** Type of apb2otp_blk0_backup4_w4 register - * eFuse apb2otp block0 data register20. - */ -typedef union { - struct { - /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word4 data. - */ - uint32_t apb2otp_block0_backup4_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup4_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */ -/** Type of apb2otp_blk0_backup4_w5 register - * eFuse apb2otp block0 data register21. - */ -typedef union { - struct { - /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block0 backup4 word5 data. - */ - uint32_t apb2otp_block0_backup4_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk0_backup4_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word1 Data */ -/** Type of apb2otp_blk1_w1 register - * eFuse apb2otp block1 data register1. - */ -typedef union { - struct { - /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word1 data. - */ - uint32_t apb2otp_block1_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word2 Data */ -/** Type of apb2otp_blk1_w2 register - * eFuse apb2otp block1 data register2. - */ -typedef union { - struct { - /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word2 data. - */ - uint32_t apb2otp_block1_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word3 Data */ -/** Type of apb2otp_blk1_w3 register - * eFuse apb2otp block1 data register3. - */ -typedef union { - struct { - /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word3 data. - */ - uint32_t apb2otp_block1_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word4 Data */ -/** Type of apb2otp_blk1_w4 register - * eFuse apb2otp block1 data register4. - */ -typedef union { - struct { - /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word4 data. - */ - uint32_t apb2otp_block1_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word5 Data */ -/** Type of apb2otp_blk1_w5 register - * eFuse apb2otp block1 data register5. - */ -typedef union { - struct { - /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word5 data. - */ - uint32_t apb2otp_block1_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word6 Data */ -/** Type of apb2otp_blk1_w6 register - * eFuse apb2otp block1 data register6. - */ -typedef union { - struct { - /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word6 data. - */ - uint32_t apb2otp_block1_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word7 Data */ -/** Type of apb2otp_blk1_w7 register - * eFuse apb2otp block1 data register7. - */ -typedef union { - struct { - /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word7 data. - */ - uint32_t apb2otp_block1_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word8 Data */ -/** Type of apb2otp_blk1_w8 register - * eFuse apb2otp block1 data register8. - */ -typedef union { - struct { - /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word8 data. - */ - uint32_t apb2otp_block1_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block1 Word9 Data */ -/** Type of apb2otp_blk1_w9 register - * eFuse apb2otp block1 data register9. - */ -typedef union { - struct { - /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block1 word9 data. - */ - uint32_t apb2otp_block1_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk1_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word1 Data */ -/** Type of apb2otp_blk2_w1 register - * eFuse apb2otp block2 data register1. - */ -typedef union { - struct { - /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word1 data. - */ - uint32_t apb2otp_block2_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word2 Data */ -/** Type of apb2otp_blk2_w2 register - * eFuse apb2otp block2 data register2. - */ -typedef union { - struct { - /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word2 data. - */ - uint32_t apb2otp_block2_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word3 Data */ -/** Type of apb2otp_blk2_w3 register - * eFuse apb2otp block2 data register3. - */ -typedef union { - struct { - /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word3 data. - */ - uint32_t apb2otp_block2_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word4 Data */ -/** Type of apb2otp_blk2_w4 register - * eFuse apb2otp block2 data register4. - */ -typedef union { - struct { - /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word4 data. - */ - uint32_t apb2otp_block2_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word5 Data */ -/** Type of apb2otp_blk2_w5 register - * eFuse apb2otp block2 data register5. - */ -typedef union { - struct { - /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word5 data. - */ - uint32_t apb2otp_block2_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word6 Data */ -/** Type of apb2otp_blk2_w6 register - * eFuse apb2otp block2 data register6. - */ -typedef union { - struct { - /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word6 data. - */ - uint32_t apb2otp_block2_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word7 Data */ -/** Type of apb2otp_blk2_w7 register - * eFuse apb2otp block2 data register7. - */ -typedef union { - struct { - /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word7 data. - */ - uint32_t apb2otp_block2_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word8 Data */ -/** Type of apb2otp_blk2_w8 register - * eFuse apb2otp block2 data register8. - */ -typedef union { - struct { - /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word8 data. - */ - uint32_t apb2otp_block2_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word9 Data */ -/** Type of apb2otp_blk2_w9 register - * eFuse apb2otp block2 data register9. - */ -typedef union { - struct { - /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word9 data. - */ - uint32_t apb2otp_block2_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word10 Data */ -/** Type of apb2otp_blk2_w10 register - * eFuse apb2otp block2 data register10. - */ -typedef union { - struct { - /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word10 data. - */ - uint32_t apb2otp_block2_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block2 Word11 Data */ -/** Type of apb2otp_blk2_w11 register - * eFuse apb2otp block2 data register11. - */ -typedef union { - struct { - /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block2 word11 data. - */ - uint32_t apb2otp_block2_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk2_w11_reg_t; - -/** Type of apb2otp_blk10_w11 register - * eFuse apb2otp block10 data register11. - */ -typedef union { - struct { - /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word11 data. - */ - uint32_t apb2otp_block10_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word1 Data */ -/** Type of apb2otp_blk3_w1 register - * eFuse apb2otp block3 data register1. - */ -typedef union { - struct { - /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word1 data. - */ - uint32_t apb2otp_block3_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word2 Data */ -/** Type of apb2otp_blk3_w2 register - * eFuse apb2otp block3 data register2. - */ -typedef union { - struct { - /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word2 data. - */ - uint32_t apb2otp_block3_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word3 Data */ -/** Type of apb2otp_blk3_w3 register - * eFuse apb2otp block3 data register3. - */ -typedef union { - struct { - /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word3 data. - */ - uint32_t apb2otp_block3_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word4 Data */ -/** Type of apb2otp_blk3_w4 register - * eFuse apb2otp block3 data register4. - */ -typedef union { - struct { - /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word4 data. - */ - uint32_t apb2otp_block3_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word5 Data */ -/** Type of apb2otp_blk3_w5 register - * eFuse apb2otp block3 data register5. - */ -typedef union { - struct { - /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word5 data. - */ - uint32_t apb2otp_block3_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word6 Data */ -/** Type of apb2otp_blk3_w6 register - * eFuse apb2otp block3 data register6. - */ -typedef union { - struct { - /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word6 data. - */ - uint32_t apb2otp_block3_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word7 Data */ -/** Type of apb2otp_blk3_w7 register - * eFuse apb2otp block3 data register7. - */ -typedef union { - struct { - /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word7 data. - */ - uint32_t apb2otp_block3_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word8 Data */ -/** Type of apb2otp_blk3_w8 register - * eFuse apb2otp block3 data register8. - */ -typedef union { - struct { - /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word8 data. - */ - uint32_t apb2otp_block3_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word9 Data */ -/** Type of apb2otp_blk3_w9 register - * eFuse apb2otp block3 data register9. - */ -typedef union { - struct { - /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word9 data. - */ - uint32_t apb2otp_block3_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word10 Data */ -/** Type of apb2otp_blk3_w10 register - * eFuse apb2otp block3 data register10. - */ -typedef union { - struct { - /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word10 data. - */ - uint32_t apb2otp_block3_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block3 Word11 Data */ -/** Type of apb2otp_blk3_w11 register - * eFuse apb2otp block3 data register11. - */ -typedef union { - struct { - /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block3 word11 data. - */ - uint32_t apb2otp_block3_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk3_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word1 Data */ -/** Type of apb2otp_blk4_w1 register - * eFuse apb2otp block4 data register1. - */ -typedef union { - struct { - /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word1 data. - */ - uint32_t apb2otp_block4_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word2 Data */ -/** Type of apb2otp_blk4_w2 register - * eFuse apb2otp block4 data register2. - */ -typedef union { - struct { - /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word2 data. - */ - uint32_t apb2otp_block4_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word3 Data */ -/** Type of apb2otp_blk4_w3 register - * eFuse apb2otp block4 data register3. - */ -typedef union { - struct { - /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word3 data. - */ - uint32_t apb2otp_block4_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word4 Data */ -/** Type of apb2otp_blk4_w4 register - * eFuse apb2otp block4 data register4. - */ -typedef union { - struct { - /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word4 data. - */ - uint32_t apb2otp_block4_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word5 Data */ -/** Type of apb2otp_blk4_w5 register - * eFuse apb2otp block4 data register5. - */ -typedef union { - struct { - /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word5 data. - */ - uint32_t apb2otp_block4_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word6 Data */ -/** Type of apb2otp_blk4_w6 register - * eFuse apb2otp block4 data register6. - */ -typedef union { - struct { - /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word6 data. - */ - uint32_t apb2otp_block4_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word7 Data */ -/** Type of apb2otp_blk4_w7 register - * eFuse apb2otp block4 data register7. - */ -typedef union { - struct { - /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word7 data. - */ - uint32_t apb2otp_block4_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word8 Data */ -/** Type of apb2otp_blk4_w8 register - * eFuse apb2otp block4 data register8. - */ -typedef union { - struct { - /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word8 data. - */ - uint32_t apb2otp_block4_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word9 Data */ -/** Type of apb2otp_blk4_w9 register - * eFuse apb2otp block4 data register9. - */ -typedef union { - struct { - /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word9 data. - */ - uint32_t apb2otp_block4_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word10 Data */ -/** Type of apb2otp_blk4_w10 register - * eFuse apb2otp block4 data registe10. - */ -typedef union { - struct { - /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word10 data. - */ - uint32_t apb2otp_block4_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block4 Word11 Data */ -/** Type of apb2otp_blk4_w11 register - * eFuse apb2otp block4 data register11. - */ -typedef union { - struct { - /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block4 word11 data. - */ - uint32_t apb2otp_block4_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk4_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word1 Data */ -/** Type of apb2otp_blk5_w1 register - * eFuse apb2otp block5 data register1. - */ -typedef union { - struct { - /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word1 data. - */ - uint32_t apb2otp_block5_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word2 Data */ -/** Type of apb2otp_blk5_w2 register - * eFuse apb2otp block5 data register2. - */ -typedef union { - struct { - /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word2 data. - */ - uint32_t apb2otp_block5_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word3 Data */ -/** Type of apb2otp_blk5_w3 register - * eFuse apb2otp block5 data register3. - */ -typedef union { - struct { - /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word3 data. - */ - uint32_t apb2otp_block5_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word4 Data */ -/** Type of apb2otp_blk5_w4 register - * eFuse apb2otp block5 data register4. - */ -typedef union { - struct { - /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word4 data. - */ - uint32_t apb2otp_block5_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word5 Data */ -/** Type of apb2otp_blk5_w5 register - * eFuse apb2otp block5 data register5. - */ -typedef union { - struct { - /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word5 data. - */ - uint32_t apb2otp_block5_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word6 Data */ -/** Type of apb2otp_blk5_w6 register - * eFuse apb2otp block5 data register6. - */ -typedef union { - struct { - /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word6 data. - */ - uint32_t apb2otp_block5_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word7 Data */ -/** Type of apb2otp_blk5_w7 register - * eFuse apb2otp block5 data register7. - */ -typedef union { - struct { - /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word7 data. - */ - uint32_t apb2otp_block5_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word8 Data */ -/** Type of apb2otp_blk5_w8 register - * eFuse apb2otp block5 data register8. - */ -typedef union { - struct { - /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word8 data. - */ - uint32_t apb2otp_block5_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word9 Data */ -/** Type of apb2otp_blk5_w9 register - * eFuse apb2otp block5 data register9. - */ -typedef union { - struct { - /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word9 data. - */ - uint32_t apb2otp_block5_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word10 Data */ -/** Type of apb2otp_blk5_w10 register - * eFuse apb2otp block5 data register10. - */ -typedef union { - struct { - /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word10 data. - */ - uint32_t apb2otp_block5_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block5 Word11 Data */ -/** Type of apb2otp_blk5_w11 register - * eFuse apb2otp block5 data register11. - */ -typedef union { - struct { - /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block5 word11 data. - */ - uint32_t apb2otp_block5_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk5_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word1 Data */ -/** Type of apb2otp_blk6_w1 register - * eFuse apb2otp block6 data register1. - */ -typedef union { - struct { - /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word1 data. - */ - uint32_t apb2otp_block6_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word2 Data */ -/** Type of apb2otp_blk6_w2 register - * eFuse apb2otp block6 data register2. - */ -typedef union { - struct { - /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word2 data. - */ - uint32_t apb2otp_block6_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word3 Data */ -/** Type of apb2otp_blk6_w3 register - * eFuse apb2otp block6 data register3. - */ -typedef union { - struct { - /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word3 data. - */ - uint32_t apb2otp_block6_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word4 Data */ -/** Type of apb2otp_blk6_w4 register - * eFuse apb2otp block6 data register4. - */ -typedef union { - struct { - /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word4 data. - */ - uint32_t apb2otp_block6_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word5 Data */ -/** Type of apb2otp_blk6_w5 register - * eFuse apb2otp block6 data register5. - */ -typedef union { - struct { - /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word5 data. - */ - uint32_t apb2otp_block6_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word6 Data */ -/** Type of apb2otp_blk6_w6 register - * eFuse apb2otp block6 data register6. - */ -typedef union { - struct { - /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word6 data. - */ - uint32_t apb2otp_block6_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word7 Data */ -/** Type of apb2otp_blk6_w7 register - * eFuse apb2otp block6 data register7. - */ -typedef union { - struct { - /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word7 data. - */ - uint32_t apb2otp_block6_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word8 Data */ -/** Type of apb2otp_blk6_w8 register - * eFuse apb2otp block6 data register8. - */ -typedef union { - struct { - /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word8 data. - */ - uint32_t apb2otp_block6_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word9 Data */ -/** Type of apb2otp_blk6_w9 register - * eFuse apb2otp block6 data register9. - */ -typedef union { - struct { - /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word9 data. - */ - uint32_t apb2otp_block6_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word10 Data */ -/** Type of apb2otp_blk6_w10 register - * eFuse apb2otp block6 data register10. - */ -typedef union { - struct { - /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word10 data. - */ - uint32_t apb2otp_block6_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block6 Word11 Data */ -/** Type of apb2otp_blk6_w11 register - * eFuse apb2otp block6 data register11. - */ -typedef union { - struct { - /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block6 word11 data. - */ - uint32_t apb2otp_block6_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk6_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word1 Data */ -/** Type of apb2otp_blk7_w1 register - * eFuse apb2otp block7 data register1. - */ -typedef union { - struct { - /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word1 data. - */ - uint32_t apb2otp_block7_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word2 Data */ -/** Type of apb2otp_blk7_w2 register - * eFuse apb2otp block7 data register2. - */ -typedef union { - struct { - /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word2 data. - */ - uint32_t apb2otp_block7_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word3 Data */ -/** Type of apb2otp_blk7_w3 register - * eFuse apb2otp block7 data register3. - */ -typedef union { - struct { - /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word3 data. - */ - uint32_t apb2otp_block7_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word4 Data */ -/** Type of apb2otp_blk7_w4 register - * eFuse apb2otp block7 data register4. - */ -typedef union { - struct { - /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word4 data. - */ - uint32_t apb2otp_block7_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word5 Data */ -/** Type of apb2otp_blk7_w5 register - * eFuse apb2otp block7 data register5. - */ -typedef union { - struct { - /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word5 data. - */ - uint32_t apb2otp_block7_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word6 Data */ -/** Type of apb2otp_blk7_w6 register - * eFuse apb2otp block7 data register6. - */ -typedef union { - struct { - /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word6 data. - */ - uint32_t apb2otp_block7_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word7 Data */ -/** Type of apb2otp_blk7_w7 register - * eFuse apb2otp block7 data register7. - */ -typedef union { - struct { - /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word7 data. - */ - uint32_t apb2otp_block7_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word8 Data */ -/** Type of apb2otp_blk7_w8 register - * eFuse apb2otp block7 data register8. - */ -typedef union { - struct { - /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word8 data. - */ - uint32_t apb2otp_block7_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word9 Data */ -/** Type of apb2otp_blk7_w9 register - * eFuse apb2otp block7 data register9. - */ -typedef union { - struct { - /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word9 data. - */ - uint32_t apb2otp_block7_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word10 Data */ -/** Type of apb2otp_blk7_w10 register - * eFuse apb2otp block7 data register10. - */ -typedef union { - struct { - /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word10 data. - */ - uint32_t apb2otp_block7_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block7 Word11 Data */ -/** Type of apb2otp_blk7_w11 register - * eFuse apb2otp block7 data register11. - */ -typedef union { - struct { - /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block7 word11 data. - */ - uint32_t apb2otp_block7_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk7_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word1 Data */ -/** Type of apb2otp_blk8_w1 register - * eFuse apb2otp block8 data register1. - */ -typedef union { - struct { - /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word1 data. - */ - uint32_t apb2otp_block8_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word2 Data */ -/** Type of apb2otp_blk8_w2 register - * eFuse apb2otp block8 data register2. - */ -typedef union { - struct { - /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word2 data. - */ - uint32_t apb2otp_block8_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word3 Data */ -/** Type of apb2otp_blk8_w3 register - * eFuse apb2otp block8 data register3. - */ -typedef union { - struct { - /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word3 data. - */ - uint32_t apb2otp_block8_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word4 Data */ -/** Type of apb2otp_blk8_w4 register - * eFuse apb2otp block8 data register4. - */ -typedef union { - struct { - /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word4 data. - */ - uint32_t apb2otp_block8_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word5 Data */ -/** Type of apb2otp_blk8_w5 register - * eFuse apb2otp block8 data register5. - */ -typedef union { - struct { - /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word5 data. - */ - uint32_t apb2otp_block8_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word6 Data */ -/** Type of apb2otp_blk8_w6 register - * eFuse apb2otp block8 data register6. - */ -typedef union { - struct { - /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word6 data. - */ - uint32_t apb2otp_block8_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word7 Data */ -/** Type of apb2otp_blk8_w7 register - * eFuse apb2otp block8 data register7. - */ -typedef union { - struct { - /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word7 data. - */ - uint32_t apb2otp_block8_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word8 Data */ -/** Type of apb2otp_blk8_w8 register - * eFuse apb2otp block8 data register8. - */ -typedef union { - struct { - /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word8 data. - */ - uint32_t apb2otp_block8_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word9 Data */ -/** Type of apb2otp_blk8_w9 register - * eFuse apb2otp block8 data register9. - */ -typedef union { - struct { - /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word9 data. - */ - uint32_t apb2otp_block8_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word10 Data */ -/** Type of apb2otp_blk8_w10 register - * eFuse apb2otp block8 data register10. - */ -typedef union { - struct { - /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word10 data. - */ - uint32_t apb2otp_block8_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block8 Word11 Data */ -/** Type of apb2otp_blk8_w11 register - * eFuse apb2otp block8 data register11. - */ -typedef union { - struct { - /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block8 word11 data. - */ - uint32_t apb2otp_block8_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk8_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word1 Data */ -/** Type of apb2otp_blk9_w1 register - * eFuse apb2otp block9 data register1. - */ -typedef union { - struct { - /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word1 data. - */ - uint32_t apb2otp_block9_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word2 Data */ -/** Type of apb2otp_blk9_w2 register - * eFuse apb2otp block9 data register2. - */ -typedef union { - struct { - /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word2 data. - */ - uint32_t apb2otp_block9_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word3 Data */ -/** Type of apb2otp_blk9_w3 register - * eFuse apb2otp block9 data register3. - */ -typedef union { - struct { - /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word3 data. - */ - uint32_t apb2otp_block9_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word4 Data */ -/** Type of apb2otp_blk9_w4 register - * eFuse apb2otp block9 data register4. - */ -typedef union { - struct { - /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word4 data. - */ - uint32_t apb2otp_block9_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word5 Data */ -/** Type of apb2otp_blk9_w5 register - * eFuse apb2otp block9 data register5. - */ -typedef union { - struct { - /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word5 data. - */ - uint32_t apb2otp_block9_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word6 Data */ -/** Type of apb2otp_blk9_w6 register - * eFuse apb2otp block9 data register6. - */ -typedef union { - struct { - /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word6 data. - */ - uint32_t apb2otp_block9_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word7 Data */ -/** Type of apb2otp_blk9_w7 register - * eFuse apb2otp block9 data register7. - */ -typedef union { - struct { - /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word7 data. - */ - uint32_t apb2otp_block9_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word8 Data */ -/** Type of apb2otp_blk9_w8 register - * eFuse apb2otp block9 data register8. - */ -typedef union { - struct { - /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word8 data. - */ - uint32_t apb2otp_block9_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word9 Data */ -/** Type of apb2otp_blk9_w9 register - * eFuse apb2otp block9 data register9. - */ -typedef union { - struct { - /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word9 data. - */ - uint32_t apb2otp_block9_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word10 Data */ -/** Type of apb2otp_blk9_w10 register - * eFuse apb2otp block9 data register10. - */ -typedef union { - struct { - /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word10 data. - */ - uint32_t apb2otp_block9_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Block9 Word11 Data */ -/** Type of apb2otp_blk9_w11 register - * eFuse apb2otp block9 data register11. - */ -typedef union { - struct { - /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block9 word11 data. - */ - uint32_t apb2otp_block9_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk9_w11_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word1 Data */ -/** Type of apb2otp_blk10_w1 register - * eFuse apb2otp block10 data register1. - */ -typedef union { - struct { - /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word1 data. - */ - uint32_t apb2otp_block10_w1:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w1_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word2 Data */ -/** Type of apb2otp_blk10_w2 register - * eFuse apb2otp block10 data register2. - */ -typedef union { - struct { - /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word2 data. - */ - uint32_t apb2otp_block10_w2:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w2_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word3 Data */ -/** Type of apb2otp_blk10_w3 register - * eFuse apb2otp block10 data register3. - */ -typedef union { - struct { - /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word3 data. - */ - uint32_t apb2otp_block10_w3:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w3_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word4 Data */ -/** Type of apb2otp_blk10_w4 register - * eFuse apb2otp block10 data register4. - */ -typedef union { - struct { - /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word4 data. - */ - uint32_t apb2otp_block10_w4:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w4_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word5 Data */ -/** Type of apb2otp_blk10_w5 register - * eFuse apb2otp block10 data register5. - */ -typedef union { - struct { - /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word5 data. - */ - uint32_t apb2otp_block10_w5:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w5_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word6 Data */ -/** Type of apb2otp_blk10_w6 register - * eFuse apb2otp block10 data register6. - */ -typedef union { - struct { - /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word6 data. - */ - uint32_t apb2otp_block10_w6:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w6_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word7 Data */ -/** Type of apb2otp_blk10_w7 register - * eFuse apb2otp block10 data register7. - */ -typedef union { - struct { - /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word7 data. - */ - uint32_t apb2otp_block10_w7:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w7_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word8 Data */ -/** Type of apb2otp_blk10_w8 register - * eFuse apb2otp block10 data register8. - */ -typedef union { - struct { - /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word8 data. - */ - uint32_t apb2otp_block10_w8:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w8_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word9 Data */ -/** Type of apb2otp_blk10_w9 register - * eFuse apb2otp block10 data register9. - */ -typedef union { - struct { - /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word9 data. - */ - uint32_t apb2otp_block10_w9:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w9_reg_t; - - -/** Group: EFUSE_APB2OTP Block10 Word10 Data */ -/** Type of apb2otp_blk10_w10 register - * eFuse apb2otp block10 data register10. - */ -typedef union { - struct { - /** apb2otp_block19_w10 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word10 data. - */ - uint32_t apb2otp_block19_w10:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w10_reg_t; - - -/** Group: EFUSE_APB2OTP Function Enable Signal */ -/** Type of apb2otp_en register - * eFuse apb2otp enable configuration register. - */ -typedef union { - struct { - /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0; - * Apb2otp mode enable signal. - */ - uint32_t apb2otp_apb2otp_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} efuse_apb2otp_en_reg_t; - - -typedef struct { - volatile efuse_pgm_datan_reg_t pgm_datan[8]; - volatile efuse_pgm_check_valuen_reg_t pgm_check_valuen[3]; - volatile efuse_rd_wr_dis_reg_t rd_wr_dis; - volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; - volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; - volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; - volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; - volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; - volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0; - volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1; - uint32_t reserved_04c; - volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3; - volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4; - volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5; - volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8]; - volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8]; - volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8]; - volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8]; - volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8]; - volatile efuse_rd_key3_datan_reg_t rd_key3_datan[8]; - volatile efuse_rd_key4_datan_reg_t rd_key4_datan[8]; - volatile efuse_rd_key5_datan_reg_t rd_key5_datan[8]; - volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; - volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; - volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; - volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; - volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; - volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; - uint32_t reserved_174; - volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; - volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0; - volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1; - volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2; - volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3; - volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4; - uint32_t reserved_190[8]; - volatile efuse_ecdsa_reg_t ecdsa; - uint32_t reserved_1b4[3]; - volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0; - volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1; - volatile efuse_clk_reg_t clk; - volatile efuse_conf_reg_t conf; - volatile efuse_status_reg_t status; - volatile efuse_cmd_reg_t cmd; - volatile efuse_int_raw_reg_t int_raw; - volatile efuse_int_st_reg_t int_st; - volatile efuse_int_ena_reg_t int_ena; - volatile efuse_int_clr_reg_t int_clr; - volatile efuse_dac_conf_reg_t dac_conf; - volatile efuse_rd_tim_conf_reg_t rd_tim_conf; - volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; - volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; - volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass; - volatile efuse_date_reg_t date; - uint32_t reserved_200[384]; - volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis; - volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1; - volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2; - volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3; - volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4; - volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5; - volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1; - volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2; - volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3; - volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4; - volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5; - volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1; - volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2; - volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3; - volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4; - volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5; - volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1; - volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2; - volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3; - volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4; - volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5; - volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1; - volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2; - volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3; - volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4; - volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5; - volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6; - volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7; - volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8; - volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9; - volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1; - volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2; - volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3; - volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4; - volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5; - volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6; - volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7; - volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8; - volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9; - volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10; - volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11; - volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1; - volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2; - volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3; - volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4; - volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5; - volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6; - volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7; - volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8; - volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9; - volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10; - volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11; - volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1; - volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2; - volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3; - volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4; - volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5; - volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6; - volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7; - volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8; - volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9; - volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10; - volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11; - volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1; - volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2; - volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3; - volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4; - volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5; - volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6; - volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7; - volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8; - volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9; - volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10; - volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11; - volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1; - volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2; - volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3; - volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4; - volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5; - volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6; - volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7; - volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8; - volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9; - volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10; - volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11; - volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1; - volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2; - volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3; - volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4; - volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5; - volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6; - volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7; - volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8; - volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9; - volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10; - volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11; - volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1; - volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2; - volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3; - volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4; - volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5; - volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6; - volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7; - volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8; - volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9; - volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10; - volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11; - volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1; - volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2; - volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3; - volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4; - volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5; - volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6; - volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7; - volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8; - volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9; - volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10; - volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11; - volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1; - volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2; - volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3; - volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4; - volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5; - volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6; - volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7; - volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8; - volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9; - volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10; - volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11; - uint32_t reserved_a04; - volatile efuse_apb2otp_en_reg_t apb2otp_en; -} efuse_dev_t; - -extern efuse_dev_t EFUSE; - -#ifndef __cplusplus -_Static_assert(sizeof(efuse_dev_t) == 0xa0c, "Invalid size of efuse_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/efuse_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/efuse_reg.h index e0a0a82e4e9..9470cba0689 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/efuse_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/efuse_reg.h @@ -12,10 +12,8 @@ extern "C" { #endif -//TODO: IDF-13421 - /** EFUSE_PGM_DATA0_REG register - * Register 0 that stores data to be programmed. + * Represents pgm_data0 */ #define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) /** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; @@ -27,11 +25,11 @@ extern "C" { #define EFUSE_PGM_DATA_0_S 0 /** EFUSE_PGM_DATA1_REG register - * Register 1 that stores data to be programmed. + * Represents pgm_data1 */ #define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) /** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1st 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_1 0xFFFFFFFFU #define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) @@ -39,11 +37,11 @@ extern "C" { #define EFUSE_PGM_DATA_1_S 0 /** EFUSE_PGM_DATA2_REG register - * Register 2 that stores data to be programmed. + * Represents pgm_data2 */ #define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) /** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2nd 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_2 0xFFFFFFFFU #define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) @@ -51,11 +49,11 @@ extern "C" { #define EFUSE_PGM_DATA_2_S 0 /** EFUSE_PGM_DATA3_REG register - * Register 3 that stores data to be programmed. + * Represents pgm_data3 */ #define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) /** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; - * Configures the 3rd 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_3 0xFFFFFFFFU #define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) @@ -63,11 +61,11 @@ extern "C" { #define EFUSE_PGM_DATA_3_S 0 /** EFUSE_PGM_DATA4_REG register - * Register 4 that stores data to be programmed. + * Represents pgm_data4 */ #define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) /** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; - * Configures the 4th 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_4 0xFFFFFFFFU #define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) @@ -75,11 +73,11 @@ extern "C" { #define EFUSE_PGM_DATA_4_S 0 /** EFUSE_PGM_DATA5_REG register - * Register 5 that stores data to be programmed. + * Represents pgm_data5 */ #define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) /** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; - * Configures the 5th 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_5 0xFFFFFFFFU #define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) @@ -87,11 +85,11 @@ extern "C" { #define EFUSE_PGM_DATA_5_S 0 /** EFUSE_PGM_DATA6_REG register - * Register 6 that stores data to be programmed. + * Represents pgm_data6 */ #define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) /** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; - * Configures the 6th 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_6 0xFFFFFFFFU #define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) @@ -99,11 +97,11 @@ extern "C" { #define EFUSE_PGM_DATA_6_S 0 /** EFUSE_PGM_DATA7_REG register - * Register 7 that stores data to be programmed. + * Represents pgm_data7 */ #define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) /** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; - * Configures the 7th 32-bit data to be programmed. + * Configures the 0th 32-bit data to be programmed. */ #define EFUSE_PGM_DATA_7 0xFFFFFFFFU #define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) @@ -111,11 +109,11 @@ extern "C" { #define EFUSE_PGM_DATA_7_S 0 /** EFUSE_PGM_CHECK_VALUE0_REG register - * Register 0 that stores the RS code to be programmed. + * Represents pgm_check_value0 */ #define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) /** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit RS code to be programmed. + * Configures the 0th RS code to be programmed. */ #define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) @@ -123,11 +121,11 @@ extern "C" { #define EFUSE_PGM_RS_DATA_0_S 0 /** EFUSE_PGM_CHECK_VALUE1_REG register - * Register 1 that stores the RS code to be programmed. + * Represents pgm_check_value1 */ #define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) /** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1st 32-bit RS code to be programmed. + * Configures the 0th RS code to be programmed. */ #define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) @@ -135,11 +133,11 @@ extern "C" { #define EFUSE_PGM_RS_DATA_1_S 0 /** EFUSE_PGM_CHECK_VALUE2_REG register - * Register 2 that stores the RS code to be programmed. + * Represents pgm_check_value2 */ #define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) /** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2nd 32-bit RS code to be programmed. + * Configures the 0th RS code to be programmed. */ #define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU #define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) @@ -147,12 +145,14 @@ extern "C" { #define EFUSE_PGM_RS_DATA_2_S 0 /** EFUSE_RD_WR_DIS_REG register - * BLOCK0 data register 0. + * Represents rd_wr_dis */ #define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) /** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; - * Represents whether programming of individual eFuse memory bit is disabled or - * enabled. 1: Disabled. 0 Enabled. + * Represents whether programming of individual eFuse memory bit is disabled. For + * mapping between the bits of this field and the eFuse memory bits, please refer to + * Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}.\\1: + * Disabled\\0: Enabled\\ */ #define EFUSE_WR_DIS 0xFFFFFFFFU #define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) @@ -160,56 +160,51 @@ extern "C" { #define EFUSE_WR_DIS_S 0 /** EFUSE_RD_REPEAT_DATA0_REG register - * BLOCK0 data register 1. + * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) /** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; * Represents whether reading of individual eFuse block(block4~block10) is disabled or - * enabled. 1: disabled. 0: enabled. + * enabled.\\ 1: disabled\\ 0: enabled\\ */ #define EFUSE_RD_DIS 0x0000007FU #define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) #define EFUSE_RD_DIS_V 0x0000007FU #define EFUSE_RD_DIS_S 0 -/** EFUSE_USB_DEVICE_EXCHG_PINS : RO; bitpos: [7]; default: 0; - * Enable usb device exchange pins of D+ and D-. +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1 : RO; bitpos: [8:7]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. */ -#define EFUSE_USB_DEVICE_EXCHG_PINS (BIT(7)) -#define EFUSE_USB_DEVICE_EXCHG_PINS_M (EFUSE_USB_DEVICE_EXCHG_PINS_V << EFUSE_USB_DEVICE_EXCHG_PINS_S) -#define EFUSE_USB_DEVICE_EXCHG_PINS_V 0x00000001U -#define EFUSE_USB_DEVICE_EXCHG_PINS_S 7 -/** EFUSE_USB_OTG11_EXCHG_PINS : RO; bitpos: [8]; default: 0; - * Enable usb otg11 exchange pins of D+ and D-. - */ -#define EFUSE_USB_OTG11_EXCHG_PINS (BIT(8)) -#define EFUSE_USB_OTG11_EXCHG_PINS_M (EFUSE_USB_OTG11_EXCHG_PINS_V << EFUSE_USB_OTG11_EXCHG_PINS_S) -#define EFUSE_USB_OTG11_EXCHG_PINS_V 0x00000001U -#define EFUSE_USB_OTG11_EXCHG_PINS_S 8 +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1 0x00000003U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_V 0x00000003U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_S 7 /** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; - * Represents whether the function of usb switch to jtag is disabled or enabled. 1: - * disabled. 0: enabled. + * Set this bit to disable function of usb switch to jtag in module of usb device. */ #define EFUSE_DIS_USB_JTAG (BIT(9)) #define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) #define EFUSE_DIS_USB_JTAG_V 0x00000001U #define EFUSE_DIS_USB_JTAG_S 9 -/** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0; - * Represents whether power glitch function is enabled. 1: enabled. 0: disabled. +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2 : RO; bitpos: [10]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. */ -#define EFUSE_POWERGLITCH_EN (BIT(10)) -#define EFUSE_POWERGLITCH_EN_M (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S) -#define EFUSE_POWERGLITCH_EN_V 0x00000001U -#define EFUSE_POWERGLITCH_EN_S 10 +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2 (BIT(10)) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_V 0x00000001U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_S 10 /** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0; - * Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + * Set this bit to disable USB-Serial-JTAG. */ #define EFUSE_DIS_USB_SERIAL_JTAG (BIT(11)) #define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) #define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_S 11 /** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; - * Represents whether the function that forces chip into download mode is disabled or - * enabled. 1: disabled. 0: enabled. + * Set this bit to disable the function that forces chip into download mode. */ #define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) #define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) @@ -224,106 +219,122 @@ extern "C" { #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 /** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + * Set this bit to disable TWAI function. */ #define EFUSE_DIS_TWAI (BIT(14)) #define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) #define EFUSE_DIS_TWAI_V 0x00000001U #define EFUSE_DIS_TWAI_S 14 /** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; - * Represents whether the selection between usb_to_jtag and pad_to_jtag through - * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 - * is enabled or disabled. 1: enabled. 0: disabled. + * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through + * strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0. */ #define EFUSE_JTAG_SEL_ENABLE (BIT(15)) #define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) #define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U #define EFUSE_JTAG_SEL_ENABLE_S 15 /** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; - * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: - * enabled. + * Set odd bits to disable JTAG in the soft way. JTAG can be enabled in HMAC module. */ #define EFUSE_SOFT_DIS_JTAG 0x00000007U #define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) #define EFUSE_SOFT_DIS_JTAG_V 0x00000007U #define EFUSE_SOFT_DIS_JTAG_S 16 /** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; - * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: - * enabled. + * Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. */ #define EFUSE_DIS_PAD_JTAG (BIT(19)) #define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) #define EFUSE_DIS_PAD_JTAG_V 0x00000001U #define EFUSE_DIS_PAD_JTAG_S 19 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; - * Represents whether flash encrypt function is disabled or enabled(except in SPI boot - * mode). 1: disabled. 0: enabled. + * Set this bit to disable flash manual encrypt function (except in SPI boot mode). */ #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 -/** EFUSE_USB_DEVICE_DREFH : RO; bitpos: [22:21]; default: 0; - * USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6 : RO; bitpos: [24:21]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. */ -#define EFUSE_USB_DEVICE_DREFH 0x00000003U -#define EFUSE_USB_DEVICE_DREFH_M (EFUSE_USB_DEVICE_DREFH_V << EFUSE_USB_DEVICE_DREFH_S) -#define EFUSE_USB_DEVICE_DREFH_V 0x00000003U -#define EFUSE_USB_DEVICE_DREFH_S 21 -/** EFUSE_USB_OTG11_DREFH : RO; bitpos: [24:23]; default: 0; - * USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV - */ -#define EFUSE_USB_OTG11_DREFH 0x00000003U -#define EFUSE_USB_OTG11_DREFH_M (EFUSE_USB_OTG11_DREFH_V << EFUSE_USB_OTG11_DREFH_S) -#define EFUSE_USB_OTG11_DREFH_V 0x00000003U -#define EFUSE_USB_OTG11_DREFH_S 23 +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6 0x0000000FU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_V 0x0000000FU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_S 21 /** EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0; - * TBD + * 0: intphy(gpio24/25) <---> usb_device\\ 1: intphy(26/27) <---> usb_otg11.1: + * intphy(gpio26/27) <---> usb_device\\ 1: intphy(24/25) <---> usb_otg11. */ #define EFUSE_USB_PHY_SEL (BIT(25)) #define EFUSE_USB_PHY_SEL_M (EFUSE_USB_PHY_SEL_V << EFUSE_USB_PHY_SEL_S) #define EFUSE_USB_PHY_SEL_V 0x00000001U #define EFUSE_USB_PHY_SEL_S 25 -/** EFUSE_KM_HUK_GEN_STATE_LOW : RO; bitpos: [31:26]; default: 0; - * Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even +/** EFUSE_HUK_GEN_STATE : RO; bitpos: [30:26]; default: 0; + * Set the bits to control validation of HUK generate mode. Odd of 1 is invalid, even * of 1 is valid. */ -#define EFUSE_KM_HUK_GEN_STATE_LOW 0x0000003FU -#define EFUSE_KM_HUK_GEN_STATE_LOW_M (EFUSE_KM_HUK_GEN_STATE_LOW_V << EFUSE_KM_HUK_GEN_STATE_LOW_S) -#define EFUSE_KM_HUK_GEN_STATE_LOW_V 0x0000003FU -#define EFUSE_KM_HUK_GEN_STATE_LOW_S 26 +#define EFUSE_HUK_GEN_STATE 0x0000001FU +#define EFUSE_HUK_GEN_STATE_M (EFUSE_HUK_GEN_STATE_V << EFUSE_HUK_GEN_STATE_S) +#define EFUSE_HUK_GEN_STATE_V 0x0000001FU +#define EFUSE_HUK_GEN_STATE_S 26 +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7 : RO; bitpos: [31]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. + */ +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7 (BIT(31)) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_V 0x00000001U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_S 31 /** EFUSE_RD_REPEAT_DATA1_REG register - * BLOCK0 data register 2. + * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) -/** EFUSE_KM_HUK_GEN_STATE_HIGH : RO; bitpos: [2:0]; default: 0; - * Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even - * of 1 is valid. +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10 : RO; bitpos: [2:0]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. */ -#define EFUSE_KM_HUK_GEN_STATE_HIGH 0x00000007U -#define EFUSE_KM_HUK_GEN_STATE_HIGH_M (EFUSE_KM_HUK_GEN_STATE_HIGH_V << EFUSE_KM_HUK_GEN_STATE_HIGH_S) -#define EFUSE_KM_HUK_GEN_STATE_HIGH_V 0x00000007U -#define EFUSE_KM_HUK_GEN_STATE_HIGH_S 0 -/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [4:3]; default: 0; - * Set bits to control key manager random number switch cycle. 0: control by register. - * 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles. +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10 0x00000007U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_V 0x00000007U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_S 0 +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11 : RO; bitpos: [3]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. */ -#define EFUSE_KM_RND_SWITCH_CYCLE 0x00000003U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11 (BIT(3)) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_V 0x00000001U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_S 3 +/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [4]; default: 0; + * Set the bits to control key manager random number switch cycle. 0: control by + * register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles + */ +#define EFUSE_KM_RND_SWITCH_CYCLE (BIT(4)) #define EFUSE_KM_RND_SWITCH_CYCLE_M (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S) -#define EFUSE_KM_RND_SWITCH_CYCLE_V 0x00000003U -#define EFUSE_KM_RND_SWITCH_CYCLE_S 3 +#define EFUSE_KM_RND_SWITCH_CYCLE_V 0x00000001U +#define EFUSE_KM_RND_SWITCH_CYCLE_S 4 /** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [8:5]; default: 0; - * Set each bit to control whether corresponding key can only be deployed once. 1 is - * true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. + * EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: + * {EFUSE_KM_DEPLOY_ONLY_ONCE_H, EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to + * control whether corresponding key can only be deployed once. 1 is true, 0 is false. + * bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, bit4:psram */ #define EFUSE_KM_DEPLOY_ONLY_ONCE 0x0000000FU #define EFUSE_KM_DEPLOY_ONLY_ONCE_M (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S) #define EFUSE_KM_DEPLOY_ONLY_ONCE_V 0x0000000FU #define EFUSE_KM_DEPLOY_ONLY_ONCE_S 5 /** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [12:9]; default: 0; - * Set each bit to control whether corresponding key must come from key manager.. 1 is - * true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. + * EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form + * one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H, + * EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether + * corresponding key must come from key manager. 1 is true, 0 is false. bit 0: ecsda, + * bit 1: xts, bit2: hmac, bit3: ds, bit4:psram */ #define EFUSE_FORCE_USE_KEY_MANAGER_KEY 0x0000000FU #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S) @@ -336,69 +347,74 @@ extern "C" { #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S) #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V 0x00000001U #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S 13 -/** EFUSE_XTS_KEY_LENGTH_256 : RO; bitpos: [14]; default: 0; - * Set this bit to configure flash encryption use xts-128 key, else use xts-256 key. +/** EFUSE_KM_XTS_KEY_LENGTH_256 : RO; bitpos: [14]; default: 0; + * Set this bit to config flash encryption xts-512 key, else use xts-256 key when + * using the key manager */ -#define EFUSE_XTS_KEY_LENGTH_256 (BIT(14)) -#define EFUSE_XTS_KEY_LENGTH_256_M (EFUSE_XTS_KEY_LENGTH_256_V << EFUSE_XTS_KEY_LENGTH_256_S) -#define EFUSE_XTS_KEY_LENGTH_256_V 0x00000001U -#define EFUSE_XTS_KEY_LENGTH_256_S 14 -/** EFUSE_RD_RESERVE_0_79 : RW; bitpos: [15]; default: 0; +#define EFUSE_KM_XTS_KEY_LENGTH_256 (BIT(14)) +#define EFUSE_KM_XTS_KEY_LENGTH_256_M (EFUSE_KM_XTS_KEY_LENGTH_256_V << EFUSE_KM_XTS_KEY_LENGTH_256_S) +#define EFUSE_KM_XTS_KEY_LENGTH_256_V 0x00000001U +#define EFUSE_KM_XTS_KEY_LENGTH_256_S 14 +/** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [15]; default: 0; + * Set this bit to permanently turn on ECC const-time mode. + */ +#define EFUSE_ECC_FORCE_CONST_TIME (BIT(15)) +#define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S) +#define EFUSE_ECC_FORCE_CONST_TIME_V 0x00000001U +#define EFUSE_ECC_FORCE_CONST_TIME_S 15 +/** EFUSE_RD_RESERVE_0_80 : RW; bitpos: [16]; default: 0; * Reserved, it was created by set_missed_fields_in_regs func */ -#define EFUSE_RD_RESERVE_0_79 (BIT(15)) -#define EFUSE_RD_RESERVE_0_79_M (EFUSE_RD_RESERVE_0_79_V << EFUSE_RD_RESERVE_0_79_S) -#define EFUSE_RD_RESERVE_0_79_V 0x00000001U -#define EFUSE_RD_RESERVE_0_79_S 15 -/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; - * Represents whether RTC watchdog timeout threshold is selected at startup. 1: - * selected. 0: not selected. +#define EFUSE_RD_RESERVE_0_80 (BIT(16)) +#define EFUSE_RD_RESERVE_0_80_M (EFUSE_RD_RESERVE_0_80_V << EFUSE_RD_RESERVE_0_80_S) +#define EFUSE_RD_RESERVE_0_80_V 0x00000001U +#define EFUSE_RD_RESERVE_0_80_S 16 +/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17]; default: 0; + * Select lp wdt timeout threshold at startup = initial timeout value * (2 ^ + * (EFUSE_WDT_DELAY_SEL + 1)) */ -#define EFUSE_WDT_DELAY_SEL 0x00000003U +#define EFUSE_WDT_DELAY_SEL (BIT(17)) #define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) -#define EFUSE_WDT_DELAY_SEL_V 0x00000003U -#define EFUSE_WDT_DELAY_SEL_S 16 +#define EFUSE_WDT_DELAY_SEL_V 0x00000001U +#define EFUSE_WDT_DELAY_SEL_S 17 /** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; - * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of - * 1: enabled. Even number of 1: disabled. + * Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even + * number of 1: disable. */ #define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) #define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 /** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; - * Represents whether revoking first secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. + * Set this bit to enable revoking first secure boot key. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 /** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; - * Represents whether revoking second secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. + * Set this bit to enable revoking second secure boot key. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 /** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; - * Represents whether revoking third secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. + * Set this bit to enable revoking third secure boot key. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 /** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; - * Represents the purpose of Key0. + * Purpose of Key0. */ #define EFUSE_KEY_PURPOSE_0 0x0000000FU #define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) #define EFUSE_KEY_PURPOSE_0_V 0x0000000FU #define EFUSE_KEY_PURPOSE_0_S 24 /** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; - * Represents the purpose of Key1. + * Purpose of Key1. */ #define EFUSE_KEY_PURPOSE_1 0x0000000FU #define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) @@ -406,97 +422,102 @@ extern "C" { #define EFUSE_KEY_PURPOSE_1_S 28 /** EFUSE_RD_REPEAT_DATA2_REG register - * BLOCK0 data register 3. + * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) /** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; - * Represents the purpose of Key2. + * Purpose of Key2. */ #define EFUSE_KEY_PURPOSE_2 0x0000000FU #define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) #define EFUSE_KEY_PURPOSE_2_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_S 0 /** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; - * Represents the purpose of Key3. + * Purpose of Key3. */ #define EFUSE_KEY_PURPOSE_3 0x0000000FU #define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) #define EFUSE_KEY_PURPOSE_3_V 0x0000000FU #define EFUSE_KEY_PURPOSE_3_S 4 /** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; - * Represents the purpose of Key4. + * Purpose of Key4. */ #define EFUSE_KEY_PURPOSE_4 0x0000000FU #define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) #define EFUSE_KEY_PURPOSE_4_V 0x0000000FU #define EFUSE_KEY_PURPOSE_4_S 8 /** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; - * Represents the purpose of Key5. + * Purpose of Key5. */ #define EFUSE_KEY_PURPOSE_5 0x0000000FU #define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) #define EFUSE_KEY_PURPOSE_5_V 0x0000000FU #define EFUSE_KEY_PURPOSE_5_S 12 /** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0; - * Represents the spa secure level by configuring the clock random divide mode. + * Configures the clock random divide mode to determine the dpa secure level */ #define EFUSE_SEC_DPA_LEVEL 0x00000003U #define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S) #define EFUSE_SEC_DPA_LEVEL_V 0x00000003U #define EFUSE_SEC_DPA_LEVEL_S 16 -/** EFUSE_ECDSA_ENABLE_SOFT_K : RO; bitpos: [18]; default: 0; - * Represents whether hardware random number k is forced used in ESDCA. 1: force used. - * 0: not force used. +/** EFUSE_RD_RESERVE_0_114 : RW; bitpos: [18]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func */ -#define EFUSE_ECDSA_ENABLE_SOFT_K (BIT(18)) -#define EFUSE_ECDSA_ENABLE_SOFT_K_M (EFUSE_ECDSA_ENABLE_SOFT_K_V << EFUSE_ECDSA_ENABLE_SOFT_K_S) -#define EFUSE_ECDSA_ENABLE_SOFT_K_V 0x00000001U -#define EFUSE_ECDSA_ENABLE_SOFT_K_S 18 -/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1; - * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. +#define EFUSE_RD_RESERVE_0_114 (BIT(18)) +#define EFUSE_RD_RESERVE_0_114_M (EFUSE_RD_RESERVE_0_114_V << EFUSE_RD_RESERVE_0_114_S) +#define EFUSE_RD_RESERVE_0_114_V 0x00000001U +#define EFUSE_RD_RESERVE_0_114_S 18 +/** EFUSE_XTS_DPA_CLK_ENABLE : RO; bitpos: [19]; default: 0; + * Sets this bit to enable xts clock anti-dpa attack function. */ -#define EFUSE_CRYPT_DPA_ENABLE (BIT(19)) -#define EFUSE_CRYPT_DPA_ENABLE_M (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S) -#define EFUSE_CRYPT_DPA_ENABLE_V 0x00000001U -#define EFUSE_CRYPT_DPA_ENABLE_S 19 +#define EFUSE_XTS_DPA_CLK_ENABLE (BIT(19)) +#define EFUSE_XTS_DPA_CLK_ENABLE_M (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S) +#define EFUSE_XTS_DPA_CLK_ENABLE_V 0x00000001U +#define EFUSE_XTS_DPA_CLK_ENABLE_S 19 /** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; - * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + * Set this bit to enable secure boot. */ #define EFUSE_SECURE_BOOT_EN (BIT(20)) #define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) #define EFUSE_SECURE_BOOT_EN_V 0x00000001U #define EFUSE_SECURE_BOOT_EN_S 20 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; - * Represents whether revoking aggressive secure boot is enabled or disabled. 1: - * enabled. 0: disabled. + * Set this bit to enable revoking aggressive secure boot. */ #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 -/** EFUSE_RD_RESERVE_0_118 : RW; bitpos: [22]; default: 0; +/** EFUSE_KM_DEPLOY_ONLY_ONCE_H : RO; bitpos: [22]; default: 0; + * EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: + * {EFUSE_KM_DEPLOY_ONLY_ONCE_H, EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to + * control whether corresponding key can only be deployed once. 1 is true, 0 is false. + * bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, bit4:psram + */ +#define EFUSE_KM_DEPLOY_ONLY_ONCE_H (BIT(22)) +#define EFUSE_KM_DEPLOY_ONLY_ONCE_H_M (EFUSE_KM_DEPLOY_ONLY_ONCE_H_V << EFUSE_KM_DEPLOY_ONLY_ONCE_H_S) +#define EFUSE_KM_DEPLOY_ONLY_ONCE_H_V 0x00000001U +#define EFUSE_KM_DEPLOY_ONLY_ONCE_H_S 22 +/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_H : RO; bitpos: [23]; default: 0; + * EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form + * one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H, + * EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether + * corresponding key must come from key manager. 1 is true, 0 is false. bit 0: ecsda, + * bit 1: xts, bit2: hmac, bit3: ds, bit4:psram + */ +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_H (BIT(23)) +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_S) +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_V 0x00000001U +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_S 23 +/** EFUSE_RD_RESERVE_0_120 : RW; bitpos: [25:24]; default: 0; * Reserved, it was created by set_missed_fields_in_regs func */ -#define EFUSE_RD_RESERVE_0_118 (BIT(22)) -#define EFUSE_RD_RESERVE_0_118_M (EFUSE_RD_RESERVE_0_118_V << EFUSE_RD_RESERVE_0_118_S) -#define EFUSE_RD_RESERVE_0_118_V 0x00000001U -#define EFUSE_RD_RESERVE_0_118_S 22 -/** EFUSE_FLASH_TYPE : RO; bitpos: [23]; default: 0; - * The type of interfaced flash. 0: four data lines, 1: eight data lines. - */ -#define EFUSE_FLASH_TYPE (BIT(23)) -#define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) -#define EFUSE_FLASH_TYPE_V 0x00000001U -#define EFUSE_FLASH_TYPE_S 23 -/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [25:24]; default: 0; - * Set flash page size. - */ -#define EFUSE_FLASH_PAGE_SIZE 0x00000003U -#define EFUSE_FLASH_PAGE_SIZE_M (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S) -#define EFUSE_FLASH_PAGE_SIZE_V 0x00000003U -#define EFUSE_FLASH_PAGE_SIZE_S 24 +#define EFUSE_RD_RESERVE_0_120 0x00000003U +#define EFUSE_RD_RESERVE_0_120_M (EFUSE_RD_RESERVE_0_120_V << EFUSE_RD_RESERVE_0_120_S) +#define EFUSE_RD_RESERVE_0_120_V 0x00000003U +#define EFUSE_RD_RESERVE_0_120_S 24 /** EFUSE_FLASH_ECC_EN : RO; bitpos: [26]; default: 0; - * Set this bit to enable ecc for flash boot. + * Set this bit to enable ECC for flash boot. */ #define EFUSE_FLASH_ECC_EN (BIT(26)) #define EFUSE_FLASH_ECC_EN_M (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S) @@ -510,9 +531,9 @@ extern "C" { #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S 27 /** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; - * Represents the flash waiting time after power-up, in unit of ms. When the value - * less than 15, the waiting time is the programmed value. Otherwise, the waiting time - * is 2 times the programmed value. + * Configures flash waiting time after power-up, in unit of ms. When the value less + * than 15, the waiting time is the configurable value. Otherwise, the waiting time is + * 30. */ #define EFUSE_FLASH_TPUW 0x0000000FU #define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) @@ -520,178 +541,217 @@ extern "C" { #define EFUSE_FLASH_TPUW_S 28 /** EFUSE_RD_REPEAT_DATA3_REG register - * BLOCK0 data register 4. + * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) /** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; - * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7). */ #define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) #define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 0 /** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + * Set this bit to disable direct boot mode */ #define EFUSE_DIS_DIRECT_BOOT (BIT(1)) #define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) #define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_S 1 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. - * 0: enabled. + * Set this bit to disable USB-Serial-JTAG print during rom boot. */ #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 /** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0; - * TBD + * set this bit to lock the key manager key after deploy */ #define EFUSE_LOCK_KM_KEY (BIT(3)) #define EFUSE_LOCK_KM_KEY_M (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S) #define EFUSE_LOCK_KM_KEY_V 0x00000001U #define EFUSE_LOCK_KM_KEY_S 3 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: - * disabled. 0: enabled. + * Set this bit to disable the USB-Serial-JTAG download function. */ #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 /** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; - * Represents whether security download is enabled or disabled. 1: enabled. 0: - * disabled. + * Set this bit to enable security download mode. */ #define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U #define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 /** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; - * Represents the type of UART printing. 00: force enable printing. 01: enable - * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset - * at high level. 11: force disable printing. + * Set the type of UART printing, 00: force enable printing, 01: enable printing when + * GPIO8 is reset at low level, 10: enable printing when GPIO8 is reset at high level, + * 11: force disable printing */ #define EFUSE_UART_PRINT_CONTROL 0x00000003U #define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) #define EFUSE_UART_PRINT_CONTROL_V 0x00000003U #define EFUSE_UART_PRINT_CONTROL_S 6 /** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. 1: - * forced. 0:not forced. + * Set this bit to force ROM code to send a resume command during SPI boot. */ #define EFUSE_FORCE_SEND_RESUME (BIT(8)) #define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) #define EFUSE_FORCE_SEND_RESUME_V 0x00000001U #define EFUSE_FORCE_SEND_RESUME_S 8 /** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0; - * Represents the version used by ESP-IDF anti-rollback feature. + * Secure version used by ESP-IDF anti-rollback feature. */ #define EFUSE_SECURE_VERSION 0x0000FFFFU #define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) #define EFUSE_SECURE_VERSION_V 0x0000FFFFU #define EFUSE_SECURE_VERSION_S 9 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0; - * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is - * enabled. 1: disabled. 0: enabled. + * Represents whether secure boot do fast verification on wake is disabled. 0: enabled + * 1: disabled */ #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(25)) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 25 /** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0; - * Represents whether the hysteresis function of corresponding PAD is enabled. 1: - * enabled. 0:disabled. + * Set bits to enable hysteresis function of PAD0~27 */ #define EFUSE_HYS_EN_PAD (BIT(26)) #define EFUSE_HYS_EN_PAD_M (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S) #define EFUSE_HYS_EN_PAD_V 0x00000001U #define EFUSE_HYS_EN_PAD_S 26 -/** EFUSE_DCDC_VSET : RO; bitpos: [31:27]; default: 0; - * Set the dcdc voltage default. +/** EFUSE_KEY_PURPOSE_0_H : RO; bitpos: [27]; default: 0; + * Purpose of Key0. The 5-th bit. */ -#define EFUSE_DCDC_VSET 0x0000001FU -#define EFUSE_DCDC_VSET_M (EFUSE_DCDC_VSET_V << EFUSE_DCDC_VSET_S) -#define EFUSE_DCDC_VSET_V 0x0000001FU -#define EFUSE_DCDC_VSET_S 27 +#define EFUSE_KEY_PURPOSE_0_H (BIT(27)) +#define EFUSE_KEY_PURPOSE_0_H_M (EFUSE_KEY_PURPOSE_0_H_V << EFUSE_KEY_PURPOSE_0_H_S) +#define EFUSE_KEY_PURPOSE_0_H_V 0x00000001U +#define EFUSE_KEY_PURPOSE_0_H_S 27 +/** EFUSE_KEY_PURPOSE_1_H : RO; bitpos: [28]; default: 0; + * Purpose of Key1. The 5-th bit. + */ +#define EFUSE_KEY_PURPOSE_1_H (BIT(28)) +#define EFUSE_KEY_PURPOSE_1_H_M (EFUSE_KEY_PURPOSE_1_H_V << EFUSE_KEY_PURPOSE_1_H_S) +#define EFUSE_KEY_PURPOSE_1_H_V 0x00000001U +#define EFUSE_KEY_PURPOSE_1_H_S 28 +/** EFUSE_KEY_PURPOSE_2_H : RO; bitpos: [29]; default: 0; + * Purpose of Key2. The 5-th bit. + */ +#define EFUSE_KEY_PURPOSE_2_H (BIT(29)) +#define EFUSE_KEY_PURPOSE_2_H_M (EFUSE_KEY_PURPOSE_2_H_V << EFUSE_KEY_PURPOSE_2_H_S) +#define EFUSE_KEY_PURPOSE_2_H_V 0x00000001U +#define EFUSE_KEY_PURPOSE_2_H_S 29 +/** EFUSE_KEY_PURPOSE_3_H : RO; bitpos: [30]; default: 0; + * Purpose of Key3. The 5-th bit. + */ +#define EFUSE_KEY_PURPOSE_3_H (BIT(30)) +#define EFUSE_KEY_PURPOSE_3_H_M (EFUSE_KEY_PURPOSE_3_H_V << EFUSE_KEY_PURPOSE_3_H_S) +#define EFUSE_KEY_PURPOSE_3_H_V 0x00000001U +#define EFUSE_KEY_PURPOSE_3_H_S 30 +/** EFUSE_KEY_PURPOSE_4_H : RO; bitpos: [31]; default: 0; + * Purpose of Key4. The 5-th bit. + */ +#define EFUSE_KEY_PURPOSE_4_H (BIT(31)) +#define EFUSE_KEY_PURPOSE_4_H_M (EFUSE_KEY_PURPOSE_4_H_V << EFUSE_KEY_PURPOSE_4_H_S) +#define EFUSE_KEY_PURPOSE_4_H_V 0x00000001U +#define EFUSE_KEY_PURPOSE_4_H_S 31 /** EFUSE_RD_REPEAT_DATA4_REG register - * BLOCK0 data register 5. + * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) /** EFUSE_PXA0_TIEH_SEL_0 : RO; bitpos: [1:0]; default: 0; - * TBD + * Output LDO VO0 tieh source select. 0: 1'b1 1: sdmmc1 2: reg 3:sdmmc0 */ #define EFUSE_PXA0_TIEH_SEL_0 0x00000003U #define EFUSE_PXA0_TIEH_SEL_0_M (EFUSE_PXA0_TIEH_SEL_0_V << EFUSE_PXA0_TIEH_SEL_0_S) #define EFUSE_PXA0_TIEH_SEL_0_V 0x00000003U #define EFUSE_PXA0_TIEH_SEL_0_S 0 -/** EFUSE_PXA0_TIEH_SEL_1 : RO; bitpos: [3:2]; default: 0; - * TBD. +/** EFUSE_PVT_GLITCH_EN : RO; bitpos: [2]; default: 0; + * Represents whether to enable PVT power glitch monitor function.\\1:Enable. + * \\0:Disable */ -#define EFUSE_PXA0_TIEH_SEL_1 0x00000003U -#define EFUSE_PXA0_TIEH_SEL_1_M (EFUSE_PXA0_TIEH_SEL_1_V << EFUSE_PXA0_TIEH_SEL_1_S) -#define EFUSE_PXA0_TIEH_SEL_1_V 0x00000003U -#define EFUSE_PXA0_TIEH_SEL_1_S 2 -/** EFUSE_PXA0_TIEH_SEL_2 : RO; bitpos: [5:4]; default: 0; - * TBD. +#define EFUSE_PVT_GLITCH_EN (BIT(2)) +#define EFUSE_PVT_GLITCH_EN_M (EFUSE_PVT_GLITCH_EN_V << EFUSE_PVT_GLITCH_EN_S) +#define EFUSE_PVT_GLITCH_EN_V 0x00000001U +#define EFUSE_PVT_GLITCH_EN_S 2 +/** EFUSE_RD_RESERVE_0_163 : RW; bitpos: [3]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func */ -#define EFUSE_PXA0_TIEH_SEL_2 0x00000003U -#define EFUSE_PXA0_TIEH_SEL_2_M (EFUSE_PXA0_TIEH_SEL_2_V << EFUSE_PXA0_TIEH_SEL_2_S) -#define EFUSE_PXA0_TIEH_SEL_2_V 0x00000003U -#define EFUSE_PXA0_TIEH_SEL_2_S 4 -/** EFUSE_PXA0_TIEH_SEL_3 : RO; bitpos: [7:6]; default: 0; - * TBD. +#define EFUSE_RD_RESERVE_0_163 (BIT(3)) +#define EFUSE_RD_RESERVE_0_163_M (EFUSE_RD_RESERVE_0_163_V << EFUSE_RD_RESERVE_0_163_S) +#define EFUSE_RD_RESERVE_0_163_V 0x00000001U +#define EFUSE_RD_RESERVE_0_163_S 3 +/** EFUSE_KEY_PURPOSE_5_H : RO; bitpos: [4]; default: 0; + * Purpose of Key5. The 5-th bit. */ -#define EFUSE_PXA0_TIEH_SEL_3 0x00000003U -#define EFUSE_PXA0_TIEH_SEL_3_M (EFUSE_PXA0_TIEH_SEL_3_V << EFUSE_PXA0_TIEH_SEL_3_S) -#define EFUSE_PXA0_TIEH_SEL_3_V 0x00000003U -#define EFUSE_PXA0_TIEH_SEL_3_S 6 +#define EFUSE_KEY_PURPOSE_5_H (BIT(4)) +#define EFUSE_KEY_PURPOSE_5_H_M (EFUSE_KEY_PURPOSE_5_H_V << EFUSE_KEY_PURPOSE_5_H_S) +#define EFUSE_KEY_PURPOSE_5_H_V 0x00000001U +#define EFUSE_KEY_PURPOSE_5_H_S 4 +/** EFUSE_RD_RESERVE_0_165 : RW; bitpos: [6:5]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_165 0x00000003U +#define EFUSE_RD_RESERVE_0_165_M (EFUSE_RD_RESERVE_0_165_V << EFUSE_RD_RESERVE_0_165_S) +#define EFUSE_RD_RESERVE_0_165_V 0x00000003U +#define EFUSE_RD_RESERVE_0_165_S 5 +/** EFUSE_KM_DISABLE_DEPLOY_MODE_H : RO; bitpos: [7]; default: 0; + * EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one + * field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H, EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set + * each bit to control whether corresponding key's deploy mode of new value deployment + * is disabled. 1 is true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, + * bit4:psram + */ +#define EFUSE_KM_DISABLE_DEPLOY_MODE_H (BIT(7)) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_H_M (EFUSE_KM_DISABLE_DEPLOY_MODE_H_V << EFUSE_KM_DISABLE_DEPLOY_MODE_H_S) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_H_V 0x00000001U +#define EFUSE_KM_DISABLE_DEPLOY_MODE_H_S 7 /** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [11:8]; default: 0; - * TBD. + * EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one + * field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H, EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set + * each bit to control whether corresponding key's deploy mode of new value deployment + * is disabled. 1 is true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, + * bit4:psram */ #define EFUSE_KM_DISABLE_DEPLOY_MODE 0x0000000FU #define EFUSE_KM_DISABLE_DEPLOY_MODE_M (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S) #define EFUSE_KM_DISABLE_DEPLOY_MODE_V 0x0000000FU #define EFUSE_KM_DISABLE_DEPLOY_MODE_S 8 -/** EFUSE_USB_DEVICE_DREFL : RO; bitpos: [13:12]; default: 0; - * Represents the usb device single-end input low threshold; 0.8 V to 1.04 V with step - * of 80 mV - */ -#define EFUSE_USB_DEVICE_DREFL 0x00000003U -#define EFUSE_USB_DEVICE_DREFL_M (EFUSE_USB_DEVICE_DREFL_V << EFUSE_USB_DEVICE_DREFL_S) -#define EFUSE_USB_DEVICE_DREFL_V 0x00000003U -#define EFUSE_USB_DEVICE_DREFL_S 12 -/** EFUSE_USB_OTG11_DREFL : RO; bitpos: [15:14]; default: 0; - * Represents the usb otg11 single-end input low threshold; 0.8 V to 1.04 V with step - * of 80 mV - */ -#define EFUSE_USB_OTG11_DREFL 0x00000003U -#define EFUSE_USB_OTG11_DREFL_M (EFUSE_USB_OTG11_DREFL_V << EFUSE_USB_OTG11_DREFL_S) -#define EFUSE_USB_OTG11_DREFL_V 0x00000003U -#define EFUSE_USB_OTG11_DREFL_S 14 -/** EFUSE_RD_RESERVE_0_176 : RW; bitpos: [17:16]; default: 0; +/** EFUSE_RD_RESERVE_0_172 : RW; bitpos: [15:12]; default: 0; * Reserved, it was created by set_missed_fields_in_regs func */ -#define EFUSE_RD_RESERVE_0_176 0x00000003U -#define EFUSE_RD_RESERVE_0_176_M (EFUSE_RD_RESERVE_0_176_V << EFUSE_RD_RESERVE_0_176_S) -#define EFUSE_RD_RESERVE_0_176_V 0x00000003U -#define EFUSE_RD_RESERVE_0_176_S 16 +#define EFUSE_RD_RESERVE_0_172 0x0000000FU +#define EFUSE_RD_RESERVE_0_172_M (EFUSE_RD_RESERVE_0_172_V << EFUSE_RD_RESERVE_0_172_S) +#define EFUSE_RD_RESERVE_0_172_V 0x0000000FU +#define EFUSE_RD_RESERVE_0_172_S 12 +/** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [17:16]; default: 0; + * Sets this bit to control the xts pseudo-round anti-dpa attack function. 0: + * controlled by register. 1-3: the higher the value is, the more pseudo-rounds are + * inserted to the xts-aes calculation + */ +#define EFUSE_XTS_DPA_PSEUDO_LEVEL 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S) +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_V 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_S 16 /** EFUSE_HP_PWR_SRC_SEL : RO; bitpos: [18]; default: 0; - * HP system power source select. 0:LDO. 1: DCDC. + * HP system power source select. 0:LDO 1: DCDC */ #define EFUSE_HP_PWR_SRC_SEL (BIT(18)) #define EFUSE_HP_PWR_SRC_SEL_M (EFUSE_HP_PWR_SRC_SEL_V << EFUSE_HP_PWR_SRC_SEL_S) #define EFUSE_HP_PWR_SRC_SEL_V 0x00000001U #define EFUSE_HP_PWR_SRC_SEL_S 18 -/** EFUSE_DCDC_VSET_EN : RO; bitpos: [19]; default: 0; - * Select dcdc vset use efuse_dcdc_vset. +/** EFUSE_SECURE_BOOT_SHA384_EN : RO; bitpos: [19]; default: 0; + * Represents whether secure boot using SHA-384 is enabled. 0: disable 1: enable */ -#define EFUSE_DCDC_VSET_EN (BIT(19)) -#define EFUSE_DCDC_VSET_EN_M (EFUSE_DCDC_VSET_EN_V << EFUSE_DCDC_VSET_EN_S) -#define EFUSE_DCDC_VSET_EN_V 0x00000001U -#define EFUSE_DCDC_VSET_EN_S 19 +#define EFUSE_SECURE_BOOT_SHA384_EN (BIT(19)) +#define EFUSE_SECURE_BOOT_SHA384_EN_M (EFUSE_SECURE_BOOT_SHA384_EN_V << EFUSE_SECURE_BOOT_SHA384_EN_S) +#define EFUSE_SECURE_BOOT_SHA384_EN_V 0x00000001U +#define EFUSE_SECURE_BOOT_SHA384_EN_S 19 /** EFUSE_DIS_WDT : RO; bitpos: [20]; default: 0; * Set this bit to disable watch dog. */ @@ -700,26 +760,33 @@ extern "C" { #define EFUSE_DIS_WDT_V 0x00000001U #define EFUSE_DIS_WDT_S 20 /** EFUSE_DIS_SWD : RO; bitpos: [21]; default: 0; - * Set this bit to disable super-watchdog. + * Set bit to disable super-watchdog */ #define EFUSE_DIS_SWD (BIT(21)) #define EFUSE_DIS_SWD_M (EFUSE_DIS_SWD_V << EFUSE_DIS_SWD_S) #define EFUSE_DIS_SWD_V 0x00000001U #define EFUSE_DIS_SWD_S 21 -/** EFUSE_RD_RESERVE_0_182 : RW; bitpos: [31:22]; default: 0; +/** EFUSE_PVT_GLITCH_MODE : RO; bitpos: [23:22]; default: 0; + * Use to configure glitch mode + */ +#define EFUSE_PVT_GLITCH_MODE 0x00000003U +#define EFUSE_PVT_GLITCH_MODE_M (EFUSE_PVT_GLITCH_MODE_V << EFUSE_PVT_GLITCH_MODE_S) +#define EFUSE_PVT_GLITCH_MODE_V 0x00000003U +#define EFUSE_PVT_GLITCH_MODE_S 22 +/** EFUSE_RD_RESERVE_0_184 : RW; bitpos: [31:24]; default: 0; * Reserved, it was created by set_missed_fields_in_regs func */ -#define EFUSE_RD_RESERVE_0_182 0x000003FFU -#define EFUSE_RD_RESERVE_0_182_M (EFUSE_RD_RESERVE_0_182_V << EFUSE_RD_RESERVE_0_182_S) -#define EFUSE_RD_RESERVE_0_182_V 0x000003FFU -#define EFUSE_RD_RESERVE_0_182_S 22 +#define EFUSE_RD_RESERVE_0_184 0x000000FFU +#define EFUSE_RD_RESERVE_0_184_M (EFUSE_RD_RESERVE_0_184_V << EFUSE_RD_RESERVE_0_184_S) +#define EFUSE_RD_RESERVE_0_184_V 0x000000FFU +#define EFUSE_RD_RESERVE_0_184_S 24 /** EFUSE_RD_MAC_SYS_0_REG register - * BLOCK1 data register $n. + * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) /** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; - * Stores the low 32 bits of MAC address. + * Represents MAC address. Low 32-bit. */ #define EFUSE_MAC_0 0xFFFFFFFFU #define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) @@ -727,26 +794,26 @@ extern "C" { #define EFUSE_MAC_0_S 0 /** EFUSE_RD_MAC_SYS_1_REG register - * BLOCK1 data register $n. + * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) /** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; - * Stores the high 16 bits of MAC address. + * Represents MAC address. High 16-bit. */ #define EFUSE_MAC_1 0x0000FFFFU #define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) #define EFUSE_MAC_1_V 0x0000FFFFU #define EFUSE_MAC_1_S 0 -/** EFUSE_RESERVED_1_16 : RO; bitpos: [31:16]; default: 0; - * Stores the extended bits of MAC address. +/** EFUSE_RD_RESERVE_1_48 : RW; bitpos: [31:16]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func */ -#define EFUSE_RESERVED_1_16 0x0000FFFFU -#define EFUSE_RESERVED_1_16_M (EFUSE_RESERVED_1_16_V << EFUSE_RESERVED_1_16_S) -#define EFUSE_RESERVED_1_16_V 0x0000FFFFU -#define EFUSE_RESERVED_1_16_S 16 +#define EFUSE_RD_RESERVE_1_48 0x0000FFFFU +#define EFUSE_RD_RESERVE_1_48_M (EFUSE_RD_RESERVE_1_48_V << EFUSE_RD_RESERVE_1_48_S) +#define EFUSE_RD_RESERVE_1_48_V 0x0000FFFFU +#define EFUSE_RD_RESERVE_1_48_S 16 /** EFUSE_RD_MAC_SYS_2_REG register - * BLOCK1 data register $n. + * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) /** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0; @@ -826,157 +893,59 @@ extern "C" { #define EFUSE_WAFER_VERSION_MAJOR_HI_M (EFUSE_WAFER_VERSION_MAJOR_HI_V << EFUSE_WAFER_VERSION_MAJOR_HI_S) #define EFUSE_WAFER_VERSION_MAJOR_HI_V 0x00000001U #define EFUSE_WAFER_VERSION_MAJOR_HI_S 23 -/** EFUSE_LDO_VO1_DREF : R; bitpos: [27:24]; default: 0; - * Output VO1 parameter +/** EFUSE_RESERVED_1_88 : R; bitpos: [31:24]; default: 0; + * reserved */ -#define EFUSE_LDO_VO1_DREF 0x0000000FU -#define EFUSE_LDO_VO1_DREF_M (EFUSE_LDO_VO1_DREF_V << EFUSE_LDO_VO1_DREF_S) -#define EFUSE_LDO_VO1_DREF_V 0x0000000FU -#define EFUSE_LDO_VO1_DREF_S 24 -/** EFUSE_LDO_VO2_DREF : R; bitpos: [31:28]; default: 0; - * Output VO2 parameter - */ -#define EFUSE_LDO_VO2_DREF 0x0000000FU -#define EFUSE_LDO_VO2_DREF_M (EFUSE_LDO_VO2_DREF_V << EFUSE_LDO_VO2_DREF_S) -#define EFUSE_LDO_VO2_DREF_V 0x0000000FU -#define EFUSE_LDO_VO2_DREF_S 28 +#define EFUSE_RESERVED_1_88 0x000000FFU +#define EFUSE_RESERVED_1_88_M (EFUSE_RESERVED_1_88_V << EFUSE_RESERVED_1_88_S) +#define EFUSE_RESERVED_1_88_V 0x000000FFU +#define EFUSE_RESERVED_1_88_S 24 /** EFUSE_RD_MAC_SYS_3_REG register - * BLOCK1 data register $n. + * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) -/** EFUSE_LDO_VO1_MUL : R; bitpos: [2:0]; default: 0; - * Output VO1 parameter +/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. */ -#define EFUSE_LDO_VO1_MUL 0x00000007U -#define EFUSE_LDO_VO1_MUL_M (EFUSE_LDO_VO1_MUL_V << EFUSE_LDO_VO1_MUL_S) -#define EFUSE_LDO_VO1_MUL_V 0x00000007U -#define EFUSE_LDO_VO1_MUL_S 0 -/** EFUSE_LDO_VO2_MUL : R; bitpos: [5:3]; default: 0; - * Output VO2 parameter +#define EFUSE_MAC_RESERVED_2 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) +#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU +#define EFUSE_MAC_RESERVED_2_S 0 +/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; + * Represents the first 14-bit of zeroth part of system data. */ -#define EFUSE_LDO_VO2_MUL 0x00000007U -#define EFUSE_LDO_VO2_MUL_M (EFUSE_LDO_VO2_MUL_V << EFUSE_LDO_VO2_MUL_S) -#define EFUSE_LDO_VO2_MUL_V 0x00000007U -#define EFUSE_LDO_VO2_MUL_S 3 -/** EFUSE_LDO_VO3_K : R; bitpos: [13:6]; default: 0; - * Output VO3 calibration parameter - */ -#define EFUSE_LDO_VO3_K 0x000000FFU -#define EFUSE_LDO_VO3_K_M (EFUSE_LDO_VO3_K_V << EFUSE_LDO_VO3_K_S) -#define EFUSE_LDO_VO3_K_V 0x000000FFU -#define EFUSE_LDO_VO3_K_S 6 -/** EFUSE_LDO_VO3_VOS : R; bitpos: [19:14]; default: 0; - * Output VO3 calibration parameter - */ -#define EFUSE_LDO_VO3_VOS 0x0000003FU -#define EFUSE_LDO_VO3_VOS_M (EFUSE_LDO_VO3_VOS_V << EFUSE_LDO_VO3_VOS_S) -#define EFUSE_LDO_VO3_VOS_V 0x0000003FU -#define EFUSE_LDO_VO3_VOS_S 14 -/** EFUSE_LDO_VO3_C : R; bitpos: [25:20]; default: 0; - * Output VO3 calibration parameter - */ -#define EFUSE_LDO_VO3_C 0x0000003FU -#define EFUSE_LDO_VO3_C_M (EFUSE_LDO_VO3_C_V << EFUSE_LDO_VO3_C_S) -#define EFUSE_LDO_VO3_C_V 0x0000003FU -#define EFUSE_LDO_VO3_C_S 20 -/** EFUSE_LDO_VO4_K : R; bitpos: [31:26]; default: 0; - * Output VO4 calibration parameter - */ -#define EFUSE_LDO_VO4_K 0x0000003FU -#define EFUSE_LDO_VO4_K_M (EFUSE_LDO_VO4_K_V << EFUSE_LDO_VO4_K_S) -#define EFUSE_LDO_VO4_K_V 0x0000003FU -#define EFUSE_LDO_VO4_K_S 26 +#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) +#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU +#define EFUSE_SYS_DATA_PART0_0_S 18 /** EFUSE_RD_MAC_SYS_4_REG register - * BLOCK1 data register $n. + * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) -/** EFUSE_LDO_VO4_K_1 : R; bitpos: [1:0]; default: 0; - * Output VO4 calibration parameter +/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; + * Represents the second 32-bit of zeroth part of system data. */ -#define EFUSE_LDO_VO4_K_1 0x00000003U -#define EFUSE_LDO_VO4_K_1_M (EFUSE_LDO_VO4_K_1_V << EFUSE_LDO_VO4_K_1_S) -#define EFUSE_LDO_VO4_K_1_V 0x00000003U -#define EFUSE_LDO_VO4_K_1_S 0 -/** EFUSE_LDO_VO4_VOS : R; bitpos: [7:2]; default: 0; - * Output VO4 calibration parameter - */ -#define EFUSE_LDO_VO4_VOS 0x0000003FU -#define EFUSE_LDO_VO4_VOS_M (EFUSE_LDO_VO4_VOS_V << EFUSE_LDO_VO4_VOS_S) -#define EFUSE_LDO_VO4_VOS_V 0x0000003FU -#define EFUSE_LDO_VO4_VOS_S 2 -/** EFUSE_LDO_VO4_C : R; bitpos: [13:8]; default: 0; - * Output VO4 calibration parameter - */ -#define EFUSE_LDO_VO4_C 0x0000003FU -#define EFUSE_LDO_VO4_C_M (EFUSE_LDO_VO4_C_V << EFUSE_LDO_VO4_C_S) -#define EFUSE_LDO_VO4_C_V 0x0000003FU -#define EFUSE_LDO_VO4_C_S 8 -/** EFUSE_RESERVED_1_142 : R; bitpos: [15:14]; default: 0; - * reserved - */ -#define EFUSE_RESERVED_1_142 0x00000003U -#define EFUSE_RESERVED_1_142_M (EFUSE_RESERVED_1_142_V << EFUSE_RESERVED_1_142_S) -#define EFUSE_RESERVED_1_142_V 0x00000003U -#define EFUSE_RESERVED_1_142_S 14 -/** EFUSE_ACTIVE_HP_DBIAS : R; bitpos: [19:16]; default: 0; - * Active HP DBIAS of fixed voltage - */ -#define EFUSE_ACTIVE_HP_DBIAS 0x0000000FU -#define EFUSE_ACTIVE_HP_DBIAS_M (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S) -#define EFUSE_ACTIVE_HP_DBIAS_V 0x0000000FU -#define EFUSE_ACTIVE_HP_DBIAS_S 16 -/** EFUSE_ACTIVE_LP_DBIAS : R; bitpos: [23:20]; default: 0; - * Active LP DBIAS of fixed voltage - */ -#define EFUSE_ACTIVE_LP_DBIAS 0x0000000FU -#define EFUSE_ACTIVE_LP_DBIAS_M (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S) -#define EFUSE_ACTIVE_LP_DBIAS_V 0x0000000FU -#define EFUSE_ACTIVE_LP_DBIAS_S 20 -/** EFUSE_LSLP_HP_DBIAS : R; bitpos: [27:24]; default: 0; - * LSLP HP DBIAS of fixed voltage - */ -#define EFUSE_LSLP_HP_DBIAS 0x0000000FU -#define EFUSE_LSLP_HP_DBIAS_M (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S) -#define EFUSE_LSLP_HP_DBIAS_V 0x0000000FU -#define EFUSE_LSLP_HP_DBIAS_S 24 -/** EFUSE_DSLP_DBG : R; bitpos: [31:28]; default: 0; - * DSLP BDG of fixed voltage - */ -#define EFUSE_DSLP_DBG 0x0000000FU -#define EFUSE_DSLP_DBG_M (EFUSE_DSLP_DBG_V << EFUSE_DSLP_DBG_S) -#define EFUSE_DSLP_DBG_V 0x0000000FU -#define EFUSE_DSLP_DBG_S 28 +#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) +#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_1_S 0 /** EFUSE_RD_MAC_SYS_5_REG register - * BLOCK1 data register $n. + * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) -/** EFUSE_DSLP_LP_DBIAS : R; bitpos: [4:0]; default: 0; - * DSLP LP DBIAS of fixed voltage +/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; + * Represents the third 32-bit of zeroth part of system data. */ -#define EFUSE_DSLP_LP_DBIAS 0x0000001FU -#define EFUSE_DSLP_LP_DBIAS_M (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S) -#define EFUSE_DSLP_LP_DBIAS_V 0x0000001FU -#define EFUSE_DSLP_LP_DBIAS_S 0 -/** EFUSE_LP_DCDC_DBIAS_VOL_GAP : R; bitpos: [9:5]; default: 0; - * DBIAS gap between LP and DCDC - */ -#define EFUSE_LP_DCDC_DBIAS_VOL_GAP 0x0000001FU -#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_M (EFUSE_LP_DCDC_DBIAS_VOL_GAP_V << EFUSE_LP_DCDC_DBIAS_VOL_GAP_S) -#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_V 0x0000001FU -#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_S 5 -/** EFUSE_RESERVED_1_170 : R; bitpos: [31:10]; default: 0; - * reserved - */ -#define EFUSE_RESERVED_1_170 0x003FFFFFU -#define EFUSE_RESERVED_1_170_M (EFUSE_RESERVED_1_170_V << EFUSE_RESERVED_1_170_S) -#define EFUSE_RESERVED_1_170_V 0x003FFFFFU -#define EFUSE_RESERVED_1_170_S 10 +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) +#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART0_2_S 0 /** EFUSE_RD_SYS_PART1_DATA0_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data0 */ #define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) /** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; @@ -988,7 +957,7 @@ extern "C" { #define EFUSE_OPTIONAL_UNIQUE_ID_S 0 /** EFUSE_RD_SYS_PART1_DATA1_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data1 */ #define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) /** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; @@ -1000,7 +969,7 @@ extern "C" { #define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 /** EFUSE_RD_SYS_PART1_DATA2_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data2 */ #define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) /** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; @@ -1012,7 +981,7 @@ extern "C" { #define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 /** EFUSE_RD_SYS_PART1_DATA3_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data3 */ #define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) /** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; @@ -1024,143 +993,59 @@ extern "C" { #define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 /** EFUSE_RD_SYS_PART1_DATA4_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data4 */ #define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) -/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [9:0]; default: 0; - * Average initcode of ADC1 atten0 +/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_ADC1_AVE_INITCODE_ATTEN0 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S) -#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S 0 -/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [19:10]; default: 0; - * Average initcode of ADC1 atten1 - */ -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S) -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S 10 -/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [29:20]; default: 0; - * Average initcode of ADC1 atten2 - */ -#define EFUSE_ADC1_AVE_INITCODE_ATTEN2 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S) -#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V 0x000003FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S 20 -/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [31:30]; default: 0; - * Average initcode of ADC1 atten3 - */ -#define EFUSE_ADC1_AVE_INITCODE_ATTEN3 0x00000003U -#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S) -#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V 0x00000003U -#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S 30 +#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) +#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_4_S 0 /** EFUSE_RD_SYS_PART1_DATA5_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data5 */ #define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) -/** EFUSE_ADC1_AVE_INITCODE_ATTEN3_1 : R; bitpos: [7:0]; default: 0; - * Average initcode of ADC1 atten3 +/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1 0x000000FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_S) -#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_V 0x000000FFU -#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_S 0 -/** EFUSE_ADC2_AVE_INITCODE_ATTEN0 : R; bitpos: [17:8]; default: 0; - * Average initcode of ADC2 atten0 - */ -#define EFUSE_ADC2_AVE_INITCODE_ATTEN0 0x000003FFU -#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_M (EFUSE_ADC2_AVE_INITCODE_ATTEN0_V << EFUSE_ADC2_AVE_INITCODE_ATTEN0_S) -#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_V 0x000003FFU -#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_S 8 -/** EFUSE_ADC2_AVE_INITCODE_ATTEN1 : R; bitpos: [27:18]; default: 0; - * Average initcode of ADC2 atten1 - */ -#define EFUSE_ADC2_AVE_INITCODE_ATTEN1 0x000003FFU -#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_M (EFUSE_ADC2_AVE_INITCODE_ATTEN1_V << EFUSE_ADC2_AVE_INITCODE_ATTEN1_S) -#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_V 0x000003FFU -#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_S 18 -/** EFUSE_ADC2_AVE_INITCODE_ATTEN2 : R; bitpos: [31:28]; default: 0; - * Average initcode of ADC2 atten2 - */ -#define EFUSE_ADC2_AVE_INITCODE_ATTEN2 0x0000000FU -#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_M (EFUSE_ADC2_AVE_INITCODE_ATTEN2_V << EFUSE_ADC2_AVE_INITCODE_ATTEN2_S) -#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_V 0x0000000FU -#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_S 28 +#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) +#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_5_S 0 /** EFUSE_RD_SYS_PART1_DATA6_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data6 */ #define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) -/** EFUSE_ADC2_AVE_INITCODE_ATTEN2_1 : R; bitpos: [5:0]; default: 0; - * Average initcode of ADC2 atten2 +/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1 0x0000003FU -#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_M (EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_V << EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_S) -#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_V 0x0000003FU -#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_S 0 -/** EFUSE_ADC2_AVE_INITCODE_ATTEN3 : R; bitpos: [15:6]; default: 0; - * Average initcode of ADC2 atten3 - */ -#define EFUSE_ADC2_AVE_INITCODE_ATTEN3 0x000003FFU -#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_M (EFUSE_ADC2_AVE_INITCODE_ATTEN3_V << EFUSE_ADC2_AVE_INITCODE_ATTEN3_S) -#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_V 0x000003FFU -#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_S 6 -/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [25:16]; default: 0; - * HI_DOUT of ADC1 atten0 - */ -#define EFUSE_ADC1_HI_DOUT_ATTEN0 0x000003FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN0_M (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S) -#define EFUSE_ADC1_HI_DOUT_ATTEN0_V 0x000003FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN0_S 16 -/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [31:26]; default: 0; - * HI_DOUT of ADC1 atten1 - */ -#define EFUSE_ADC1_HI_DOUT_ATTEN1 0x0000003FU -#define EFUSE_ADC1_HI_DOUT_ATTEN1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S) -#define EFUSE_ADC1_HI_DOUT_ATTEN1_V 0x0000003FU -#define EFUSE_ADC1_HI_DOUT_ATTEN1_S 26 +#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) +#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_6_S 0 /** EFUSE_RD_SYS_PART1_DATA7_REG register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data7 */ #define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) -/** EFUSE_ADC1_HI_DOUT_ATTEN1_1 : R; bitpos: [3:0]; default: 0; - * HI_DOUT of ADC1 atten1 +/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ -#define EFUSE_ADC1_HI_DOUT_ATTEN1_1 0x0000000FU -#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_1_S) -#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_V 0x0000000FU -#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_S 0 -/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [13:4]; default: 0; - * HI_DOUT of ADC1 atten2 - */ -#define EFUSE_ADC1_HI_DOUT_ATTEN2 0x000003FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN2_M (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S) -#define EFUSE_ADC1_HI_DOUT_ATTEN2_V 0x000003FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN2_S 4 -/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [23:14]; default: 0; - * HI_DOUT of ADC1 atten3 - */ -#define EFUSE_ADC1_HI_DOUT_ATTEN3 0x000003FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN3_M (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S) -#define EFUSE_ADC1_HI_DOUT_ATTEN3_V 0x000003FFU -#define EFUSE_ADC1_HI_DOUT_ATTEN3_S 14 -/** EFUSE_RESERVED_2_248 : R; bitpos: [31:24]; default: 0; - * reserved - */ -#define EFUSE_RESERVED_2_248 0x000000FFU -#define EFUSE_RESERVED_2_248_M (EFUSE_RESERVED_2_248_V << EFUSE_RESERVED_2_248_S) -#define EFUSE_RESERVED_2_248_V 0x000000FFU -#define EFUSE_RESERVED_2_248_S 24 +#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) +#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART1_7_S 0 /** EFUSE_RD_USR_DATA0_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data0 */ #define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) /** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA0 0xFFFFFFFFU #define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) @@ -1168,11 +1053,11 @@ extern "C" { #define EFUSE_USR_DATA0_S 0 /** EFUSE_RD_USR_DATA1_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data1 */ #define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) /** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA1 0xFFFFFFFFU #define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) @@ -1180,11 +1065,11 @@ extern "C" { #define EFUSE_USR_DATA1_S 0 /** EFUSE_RD_USR_DATA2_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data2 */ #define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) /** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA2 0xFFFFFFFFU #define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) @@ -1192,11 +1077,11 @@ extern "C" { #define EFUSE_USR_DATA2_S 0 /** EFUSE_RD_USR_DATA3_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data3 */ #define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) /** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA3 0xFFFFFFFFU #define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) @@ -1204,11 +1089,11 @@ extern "C" { #define EFUSE_USR_DATA3_S 0 /** EFUSE_RD_USR_DATA4_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data4 */ #define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) /** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA4 0xFFFFFFFFU #define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) @@ -1216,11 +1101,11 @@ extern "C" { #define EFUSE_USR_DATA4_S 0 /** EFUSE_RD_USR_DATA5_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data5 */ #define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) /** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ #define EFUSE_USR_DATA5 0xFFFFFFFFU #define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) @@ -1228,7 +1113,7 @@ extern "C" { #define EFUSE_USR_DATA5_S 0 /** EFUSE_RD_USR_DATA6_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data6 */ #define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) /** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; @@ -1247,7 +1132,7 @@ extern "C" { #define EFUSE_CUSTOM_MAC_S 8 /** EFUSE_RD_USR_DATA7_REG register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data7 */ #define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) /** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; @@ -1266,11 +1151,11 @@ extern "C" { #define EFUSE_RESERVED_3_248_S 24 /** EFUSE_RD_KEY0_DATA0_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data0 */ #define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) /** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA0 0xFFFFFFFFU #define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) @@ -1278,11 +1163,11 @@ extern "C" { #define EFUSE_KEY0_DATA0_S 0 /** EFUSE_RD_KEY0_DATA1_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data1 */ #define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) /** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA1 0xFFFFFFFFU #define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) @@ -1290,11 +1175,11 @@ extern "C" { #define EFUSE_KEY0_DATA1_S 0 /** EFUSE_RD_KEY0_DATA2_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data2 */ #define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) /** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA2 0xFFFFFFFFU #define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) @@ -1302,11 +1187,11 @@ extern "C" { #define EFUSE_KEY0_DATA2_S 0 /** EFUSE_RD_KEY0_DATA3_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data3 */ #define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) /** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA3 0xFFFFFFFFU #define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) @@ -1314,11 +1199,11 @@ extern "C" { #define EFUSE_KEY0_DATA3_S 0 /** EFUSE_RD_KEY0_DATA4_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data4 */ #define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) /** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA4 0xFFFFFFFFU #define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) @@ -1326,11 +1211,11 @@ extern "C" { #define EFUSE_KEY0_DATA4_S 0 /** EFUSE_RD_KEY0_DATA5_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data5 */ #define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) /** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA5 0xFFFFFFFFU #define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) @@ -1338,11 +1223,11 @@ extern "C" { #define EFUSE_KEY0_DATA5_S 0 /** EFUSE_RD_KEY0_DATA6_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data6 */ #define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) /** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA6 0xFFFFFFFFU #define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) @@ -1350,11 +1235,11 @@ extern "C" { #define EFUSE_KEY0_DATA6_S 0 /** EFUSE_RD_KEY0_DATA7_REG register - * Register $n of BLOCK4 (KEY0). + * Represents rd_key0_data7 */ #define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) /** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY0. + * Represents the zeroth 32-bit of key0. */ #define EFUSE_KEY0_DATA7 0xFFFFFFFFU #define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) @@ -1362,11 +1247,11 @@ extern "C" { #define EFUSE_KEY0_DATA7_S 0 /** EFUSE_RD_KEY1_DATA0_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data0 */ #define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) /** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA0 0xFFFFFFFFU #define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) @@ -1374,11 +1259,11 @@ extern "C" { #define EFUSE_KEY1_DATA0_S 0 /** EFUSE_RD_KEY1_DATA1_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data1 */ #define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) /** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA1 0xFFFFFFFFU #define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) @@ -1386,11 +1271,11 @@ extern "C" { #define EFUSE_KEY1_DATA1_S 0 /** EFUSE_RD_KEY1_DATA2_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data2 */ #define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) /** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA2 0xFFFFFFFFU #define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) @@ -1398,11 +1283,11 @@ extern "C" { #define EFUSE_KEY1_DATA2_S 0 /** EFUSE_RD_KEY1_DATA3_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data3 */ #define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) /** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA3 0xFFFFFFFFU #define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) @@ -1410,11 +1295,11 @@ extern "C" { #define EFUSE_KEY1_DATA3_S 0 /** EFUSE_RD_KEY1_DATA4_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data4 */ #define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) /** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA4 0xFFFFFFFFU #define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) @@ -1422,11 +1307,11 @@ extern "C" { #define EFUSE_KEY1_DATA4_S 0 /** EFUSE_RD_KEY1_DATA5_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data5 */ #define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) /** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA5 0xFFFFFFFFU #define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) @@ -1434,11 +1319,11 @@ extern "C" { #define EFUSE_KEY1_DATA5_S 0 /** EFUSE_RD_KEY1_DATA6_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data6 */ #define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) /** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA6 0xFFFFFFFFU #define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) @@ -1446,11 +1331,11 @@ extern "C" { #define EFUSE_KEY1_DATA6_S 0 /** EFUSE_RD_KEY1_DATA7_REG register - * Register $n of BLOCK5 (KEY1). + * Represents rd_key1_data7 */ #define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) /** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY1. + * Represents the zeroth 32-bit of key1. */ #define EFUSE_KEY1_DATA7 0xFFFFFFFFU #define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) @@ -1458,11 +1343,11 @@ extern "C" { #define EFUSE_KEY1_DATA7_S 0 /** EFUSE_RD_KEY2_DATA0_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data0 */ #define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) /** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA0 0xFFFFFFFFU #define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) @@ -1470,11 +1355,11 @@ extern "C" { #define EFUSE_KEY2_DATA0_S 0 /** EFUSE_RD_KEY2_DATA1_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data1 */ #define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) /** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA1 0xFFFFFFFFU #define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) @@ -1482,11 +1367,11 @@ extern "C" { #define EFUSE_KEY2_DATA1_S 0 /** EFUSE_RD_KEY2_DATA2_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data2 */ #define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) /** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA2 0xFFFFFFFFU #define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) @@ -1494,11 +1379,11 @@ extern "C" { #define EFUSE_KEY2_DATA2_S 0 /** EFUSE_RD_KEY2_DATA3_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data3 */ #define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) /** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA3 0xFFFFFFFFU #define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) @@ -1506,11 +1391,11 @@ extern "C" { #define EFUSE_KEY2_DATA3_S 0 /** EFUSE_RD_KEY2_DATA4_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data4 */ #define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) /** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA4 0xFFFFFFFFU #define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) @@ -1518,11 +1403,11 @@ extern "C" { #define EFUSE_KEY2_DATA4_S 0 /** EFUSE_RD_KEY2_DATA5_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data5 */ #define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) /** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA5 0xFFFFFFFFU #define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) @@ -1530,11 +1415,11 @@ extern "C" { #define EFUSE_KEY2_DATA5_S 0 /** EFUSE_RD_KEY2_DATA6_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data6 */ #define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) /** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA6 0xFFFFFFFFU #define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) @@ -1542,11 +1427,11 @@ extern "C" { #define EFUSE_KEY2_DATA6_S 0 /** EFUSE_RD_KEY2_DATA7_REG register - * Register $n of BLOCK6 (KEY2). + * Represents rd_key2_data7 */ #define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) /** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY2. + * Represents the zeroth 32-bit of key2. */ #define EFUSE_KEY2_DATA7 0xFFFFFFFFU #define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) @@ -1554,11 +1439,11 @@ extern "C" { #define EFUSE_KEY2_DATA7_S 0 /** EFUSE_RD_KEY3_DATA0_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data0 */ #define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) /** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA0 0xFFFFFFFFU #define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) @@ -1566,11 +1451,11 @@ extern "C" { #define EFUSE_KEY3_DATA0_S 0 /** EFUSE_RD_KEY3_DATA1_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data1 */ #define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) /** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA1 0xFFFFFFFFU #define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) @@ -1578,11 +1463,11 @@ extern "C" { #define EFUSE_KEY3_DATA1_S 0 /** EFUSE_RD_KEY3_DATA2_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data2 */ #define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) /** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA2 0xFFFFFFFFU #define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) @@ -1590,11 +1475,11 @@ extern "C" { #define EFUSE_KEY3_DATA2_S 0 /** EFUSE_RD_KEY3_DATA3_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data3 */ #define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) /** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA3 0xFFFFFFFFU #define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) @@ -1602,11 +1487,11 @@ extern "C" { #define EFUSE_KEY3_DATA3_S 0 /** EFUSE_RD_KEY3_DATA4_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data4 */ #define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) /** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA4 0xFFFFFFFFU #define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) @@ -1614,11 +1499,11 @@ extern "C" { #define EFUSE_KEY3_DATA4_S 0 /** EFUSE_RD_KEY3_DATA5_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data5 */ #define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) /** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA5 0xFFFFFFFFU #define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) @@ -1626,11 +1511,11 @@ extern "C" { #define EFUSE_KEY3_DATA5_S 0 /** EFUSE_RD_KEY3_DATA6_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data6 */ #define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) /** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA6 0xFFFFFFFFU #define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) @@ -1638,11 +1523,11 @@ extern "C" { #define EFUSE_KEY3_DATA6_S 0 /** EFUSE_RD_KEY3_DATA7_REG register - * Register $n of BLOCK7 (KEY3). + * Represents rd_key3_data7 */ #define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) /** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY3. + * Represents the zeroth 32-bit of key3. */ #define EFUSE_KEY3_DATA7 0xFFFFFFFFU #define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) @@ -1650,11 +1535,11 @@ extern "C" { #define EFUSE_KEY3_DATA7_S 0 /** EFUSE_RD_KEY4_DATA0_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data0 */ #define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) /** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA0 0xFFFFFFFFU #define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) @@ -1662,11 +1547,11 @@ extern "C" { #define EFUSE_KEY4_DATA0_S 0 /** EFUSE_RD_KEY4_DATA1_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data1 */ #define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) /** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA1 0xFFFFFFFFU #define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) @@ -1674,11 +1559,11 @@ extern "C" { #define EFUSE_KEY4_DATA1_S 0 /** EFUSE_RD_KEY4_DATA2_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data2 */ #define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) /** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA2 0xFFFFFFFFU #define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) @@ -1686,11 +1571,11 @@ extern "C" { #define EFUSE_KEY4_DATA2_S 0 /** EFUSE_RD_KEY4_DATA3_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data3 */ #define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) /** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA3 0xFFFFFFFFU #define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) @@ -1698,11 +1583,11 @@ extern "C" { #define EFUSE_KEY4_DATA3_S 0 /** EFUSE_RD_KEY4_DATA4_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data4 */ #define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) /** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA4 0xFFFFFFFFU #define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) @@ -1710,11 +1595,11 @@ extern "C" { #define EFUSE_KEY4_DATA4_S 0 /** EFUSE_RD_KEY4_DATA5_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data5 */ #define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) /** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA5 0xFFFFFFFFU #define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) @@ -1722,11 +1607,11 @@ extern "C" { #define EFUSE_KEY4_DATA5_S 0 /** EFUSE_RD_KEY4_DATA6_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data6 */ #define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) /** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA6 0xFFFFFFFFU #define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) @@ -1734,11 +1619,11 @@ extern "C" { #define EFUSE_KEY4_DATA6_S 0 /** EFUSE_RD_KEY4_DATA7_REG register - * Register $n of BLOCK8 (KEY4). + * Represents rd_key4_data7 */ #define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) /** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY4. + * Represents the zeroth 32-bit of key4. */ #define EFUSE_KEY4_DATA7 0xFFFFFFFFU #define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) @@ -1746,11 +1631,11 @@ extern "C" { #define EFUSE_KEY4_DATA7_S 0 /** EFUSE_RD_KEY5_DATA0_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data0 */ #define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) /** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA0 0xFFFFFFFFU #define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) @@ -1758,11 +1643,11 @@ extern "C" { #define EFUSE_KEY5_DATA0_S 0 /** EFUSE_RD_KEY5_DATA1_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data1 */ #define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) /** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA1 0xFFFFFFFFU #define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) @@ -1770,11 +1655,11 @@ extern "C" { #define EFUSE_KEY5_DATA1_S 0 /** EFUSE_RD_KEY5_DATA2_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data2 */ #define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) /** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA2 0xFFFFFFFFU #define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) @@ -1782,11 +1667,11 @@ extern "C" { #define EFUSE_KEY5_DATA2_S 0 /** EFUSE_RD_KEY5_DATA3_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data3 */ #define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) /** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA3 0xFFFFFFFFU #define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) @@ -1794,11 +1679,11 @@ extern "C" { #define EFUSE_KEY5_DATA3_S 0 /** EFUSE_RD_KEY5_DATA4_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data4 */ #define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) /** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA4 0xFFFFFFFFU #define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) @@ -1806,11 +1691,11 @@ extern "C" { #define EFUSE_KEY5_DATA4_S 0 /** EFUSE_RD_KEY5_DATA5_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data5 */ #define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) /** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA5 0xFFFFFFFFU #define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) @@ -1818,11 +1703,11 @@ extern "C" { #define EFUSE_KEY5_DATA5_S 0 /** EFUSE_RD_KEY5_DATA6_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data6 */ #define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) /** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA6 0xFFFFFFFFU #define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) @@ -1830,11 +1715,11 @@ extern "C" { #define EFUSE_KEY5_DATA6_S 0 /** EFUSE_RD_KEY5_DATA7_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_key5_data7 */ #define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) /** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY5. + * Represents the zeroth 32-bit of key5. */ #define EFUSE_KEY5_DATA7 0xFFFFFFFFU #define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) @@ -1842,178 +1727,59 @@ extern "C" { #define EFUSE_KEY5_DATA7_S 0 /** EFUSE_RD_SYS_PART2_DATA0_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data */ #define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) -/** EFUSE_ADC2_HI_DOUT_ATTEN0 : R; bitpos: [9:0]; default: 0; - * HI_DOUT of ADC2 atten0 +/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Represents the first 32-bit of second part of system data. */ -#define EFUSE_ADC2_HI_DOUT_ATTEN0 0x000003FFU -#define EFUSE_ADC2_HI_DOUT_ATTEN0_M (EFUSE_ADC2_HI_DOUT_ATTEN0_V << EFUSE_ADC2_HI_DOUT_ATTEN0_S) -#define EFUSE_ADC2_HI_DOUT_ATTEN0_V 0x000003FFU -#define EFUSE_ADC2_HI_DOUT_ATTEN0_S 0 -/** EFUSE_ADC2_HI_DOUT_ATTEN1 : R; bitpos: [19:10]; default: 0; - * HI_DOUT of ADC2 atten1 - */ -#define EFUSE_ADC2_HI_DOUT_ATTEN1 0x000003FFU -#define EFUSE_ADC2_HI_DOUT_ATTEN1_M (EFUSE_ADC2_HI_DOUT_ATTEN1_V << EFUSE_ADC2_HI_DOUT_ATTEN1_S) -#define EFUSE_ADC2_HI_DOUT_ATTEN1_V 0x000003FFU -#define EFUSE_ADC2_HI_DOUT_ATTEN1_S 10 -/** EFUSE_ADC2_HI_DOUT_ATTEN2 : R; bitpos: [29:20]; default: 0; - * HI_DOUT of ADC2 atten2 - */ -#define EFUSE_ADC2_HI_DOUT_ATTEN2 0x000003FFU -#define EFUSE_ADC2_HI_DOUT_ATTEN2_M (EFUSE_ADC2_HI_DOUT_ATTEN2_V << EFUSE_ADC2_HI_DOUT_ATTEN2_S) -#define EFUSE_ADC2_HI_DOUT_ATTEN2_V 0x000003FFU -#define EFUSE_ADC2_HI_DOUT_ATTEN2_S 20 -/** EFUSE_ADC2_HI_DOUT_ATTEN3 : R; bitpos: [31:30]; default: 0; - * HI_DOUT of ADC2 atten3 - */ -#define EFUSE_ADC2_HI_DOUT_ATTEN3 0x00000003U -#define EFUSE_ADC2_HI_DOUT_ATTEN3_M (EFUSE_ADC2_HI_DOUT_ATTEN3_V << EFUSE_ADC2_HI_DOUT_ATTEN3_S) -#define EFUSE_ADC2_HI_DOUT_ATTEN3_V 0x00000003U -#define EFUSE_ADC2_HI_DOUT_ATTEN3_S 30 +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_0_S 0 /** EFUSE_RD_SYS_PART2_DATA1_REG register - * Register $n of BLOCK9 (KEY5). + * Represents rd_sys_part2_data */ #define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) -/** EFUSE_ADC2_HI_DOUT_ATTEN3_1 : R; bitpos: [7:0]; default: 0; - * HI_DOUT of ADC2 atten3 +/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Represents the first 32-bit of second part of system data. */ -#define EFUSE_ADC2_HI_DOUT_ATTEN3_1 0x000000FFU -#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_M (EFUSE_ADC2_HI_DOUT_ATTEN3_1_V << EFUSE_ADC2_HI_DOUT_ATTEN3_1_S) -#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_V 0x000000FFU -#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_S 0 -/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [11:8]; default: 0; - * Gap between ADC1_ch0 and average initcode - */ -#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S 8 -/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [15:12]; default: 0; - * Gap between ADC1_ch1 and average initcode - */ -#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S 12 -/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [19:16]; default: 0; - * Gap between ADC1_ch2 and average initcode - */ -#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S 16 -/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [23:20]; default: 0; - * Gap between ADC1_ch3 and average initcode - */ -#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S 20 -/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [27:24]; default: 0; - * Gap between ADC1_ch4 and average initcode - */ -#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S 24 -/** EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [31:28]; default: 0; - * Gap between ADC1_ch5 and average initcode - */ -#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S 28 +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_1_S 0 /** EFUSE_RD_SYS_PART2_DATA2_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data */ #define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) -/** EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF : R; bitpos: [3:0]; default: 0; - * Gap between ADC1_ch6 and average initcode +/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Represents the second 32-bit of second part of system data. */ -#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_S 0 -/** EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF : R; bitpos: [7:4]; default: 0; - * Gap between ADC1_ch7 and average initcode - */ -#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_S 4 -/** EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [11:8]; default: 0; - * Gap between ADC2_ch0 and average initcode - */ -#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_S 8 -/** EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [15:12]; default: 0; - * Gap between ADC2_ch1 and average initcode - */ -#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_S 12 -/** EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [19:16]; default: 0; - * Gap between ADC2_ch2 and average initcode - */ -#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_S 16 -/** EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [23:20]; default: 0; - * Gap between ADC2_ch3 and average initcode - */ -#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_S 20 -/** EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [27:24]; default: 0; - * Gap between ADC2_ch4 and average initcode - */ -#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_S 24 -/** EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [31:28]; default: 0; - * Gap between ADC2_ch5 and average initcode - */ -#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF 0x0000000FU -#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_S) -#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_V 0x0000000FU -#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_S 28 +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_2_S 0 /** EFUSE_RD_SYS_PART2_DATA3_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data */ #define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) -/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [8:0]; default: 0; - * Temperature calibration data +/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Represents the third 32-bit of second part of system data. */ -#define EFUSE_TEMPERATURE_SENSOR 0x000001FFU -#define EFUSE_TEMPERATURE_SENSOR_M (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S) -#define EFUSE_TEMPERATURE_SENSOR_V 0x000001FFU -#define EFUSE_TEMPERATURE_SENSOR_S 0 -/** EFUSE_RESERVED_10_105 : R; bitpos: [31:9]; default: 0; - * reserved - */ -#define EFUSE_RESERVED_10_105 0x007FFFFFU -#define EFUSE_RESERVED_10_105_M (EFUSE_RESERVED_10_105_V << EFUSE_RESERVED_10_105_S) -#define EFUSE_RESERVED_10_105_V 0x007FFFFFU -#define EFUSE_RESERVED_10_105_S 9 +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU +#define EFUSE_SYS_DATA_PART2_3_S 0 /** EFUSE_RD_SYS_PART2_DATA4_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data */ #define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) /** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the fourth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) @@ -2021,11 +1787,11 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_4_S 0 /** EFUSE_RD_SYS_PART2_DATA5_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data */ #define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) /** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the fifth 32-bit of second part of system data. */ #define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) @@ -2033,243 +1799,321 @@ extern "C" { #define EFUSE_SYS_DATA_PART2_5_S 0 /** EFUSE_RD_SYS_PART2_DATA6_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data */ #define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) -/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. +/** EFUSE_PVT_LIMIT : RO; bitpos: [15:0]; default: 0; + * Power glitch monitor threthold. */ -#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) -#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_6_S 0 +#define EFUSE_PVT_LIMIT 0x0000FFFFU +#define EFUSE_PVT_LIMIT_M (EFUSE_PVT_LIMIT_V << EFUSE_PVT_LIMIT_S) +#define EFUSE_PVT_LIMIT_V 0x0000FFFFU +#define EFUSE_PVT_LIMIT_S 0 +/** EFUSE_PVT_PUMP_LIMIT : RO; bitpos: [23:16]; default: 0; + * Use to configure voltage monitor limit for charge pump + */ +#define EFUSE_PVT_PUMP_LIMIT 0x000000FFU +#define EFUSE_PVT_PUMP_LIMIT_M (EFUSE_PVT_PUMP_LIMIT_V << EFUSE_PVT_PUMP_LIMIT_S) +#define EFUSE_PVT_PUMP_LIMIT_V 0x000000FFU +#define EFUSE_PVT_PUMP_LIMIT_S 16 +/** EFUSE_PVT_CELL_SELECT : RO; bitpos: [30:24]; default: 0; + * Power glitch monitor PVT cell select. + */ +#define EFUSE_PVT_CELL_SELECT 0x0000007FU +#define EFUSE_PVT_CELL_SELECT_M (EFUSE_PVT_CELL_SELECT_V << EFUSE_PVT_CELL_SELECT_S) +#define EFUSE_PVT_CELL_SELECT_V 0x0000007FU +#define EFUSE_PVT_CELL_SELECT_S 24 +/** EFUSE_RD_RESERVE_10_223 : RW; bitpos: [31]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_10_223 (BIT(31)) +#define EFUSE_RD_RESERVE_10_223_M (EFUSE_RD_RESERVE_10_223_V << EFUSE_RD_RESERVE_10_223_S) +#define EFUSE_RD_RESERVE_10_223_V 0x00000001U +#define EFUSE_RD_RESERVE_10_223_S 31 /** EFUSE_RD_SYS_PART2_DATA7_REG register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data */ #define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) -/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. +/** EFUSE_PUMP_DRV : RO; bitpos: [3:0]; default: 0; + * Use to configure charge pump voltage gain */ -#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) -#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_7_S 0 +#define EFUSE_PUMP_DRV 0x0000000FU +#define EFUSE_PUMP_DRV_M (EFUSE_PUMP_DRV_V << EFUSE_PUMP_DRV_S) +#define EFUSE_PUMP_DRV_V 0x0000000FU +#define EFUSE_PUMP_DRV_S 0 +/** EFUSE_USB_DEVICE_EXCHG_PINS : RO; bitpos: [4]; default: 0; + * Enable usb device exchange pins of D+ and D-. + */ +#define EFUSE_USB_DEVICE_EXCHG_PINS (BIT(4)) +#define EFUSE_USB_DEVICE_EXCHG_PINS_M (EFUSE_USB_DEVICE_EXCHG_PINS_V << EFUSE_USB_DEVICE_EXCHG_PINS_S) +#define EFUSE_USB_DEVICE_EXCHG_PINS_V 0x00000001U +#define EFUSE_USB_DEVICE_EXCHG_PINS_S 4 +/** EFUSE_USB_OTG11_EXCHG_PINS : RO; bitpos: [5]; default: 0; + * Enable usb otg11 exchange pins of D+ and D-. + */ +#define EFUSE_USB_OTG11_EXCHG_PINS (BIT(5)) +#define EFUSE_USB_OTG11_EXCHG_PINS_M (EFUSE_USB_OTG11_EXCHG_PINS_V << EFUSE_USB_OTG11_EXCHG_PINS_S) +#define EFUSE_USB_OTG11_EXCHG_PINS_V 0x00000001U +#define EFUSE_USB_OTG11_EXCHG_PINS_S 5 +/** EFUSE_USB_DEVICE_DREFH : RO; bitpos: [7:6]; default: 0; + * usb intphy of usb device single-end input high threshold, 1.76V to 2V. step by 80mV. + */ +#define EFUSE_USB_DEVICE_DREFH 0x00000003U +#define EFUSE_USB_DEVICE_DREFH_M (EFUSE_USB_DEVICE_DREFH_V << EFUSE_USB_DEVICE_DREFH_S) +#define EFUSE_USB_DEVICE_DREFH_V 0x00000003U +#define EFUSE_USB_DEVICE_DREFH_S 6 +/** EFUSE_USB_OTG11_DREFH : RO; bitpos: [9:8]; default: 0; + * usb intphy of usb otg11 single-end input high threshold, 1.76V to 2V. step by 80mV. + */ +#define EFUSE_USB_OTG11_DREFH 0x00000003U +#define EFUSE_USB_OTG11_DREFH_M (EFUSE_USB_OTG11_DREFH_V << EFUSE_USB_OTG11_DREFH_S) +#define EFUSE_USB_OTG11_DREFH_V 0x00000003U +#define EFUSE_USB_OTG11_DREFH_S 8 +/** EFUSE_USB_DEVICE_DREFL : RO; bitpos: [11:10]; default: 0; + * usb intphy of usb device single-end input low threshold, 0.8V to 1.04V. step by + * 80mV. + */ +#define EFUSE_USB_DEVICE_DREFL 0x00000003U +#define EFUSE_USB_DEVICE_DREFL_M (EFUSE_USB_DEVICE_DREFL_V << EFUSE_USB_DEVICE_DREFL_S) +#define EFUSE_USB_DEVICE_DREFL_V 0x00000003U +#define EFUSE_USB_DEVICE_DREFL_S 10 +/** EFUSE_USB_OTG11_DREFL : RO; bitpos: [13:12]; default: 0; + * usb intphy of usb otg11 single-end input low threshold, 0.8V to 1.04V. step by 80mV. + */ +#define EFUSE_USB_OTG11_DREFL 0x00000003U +#define EFUSE_USB_OTG11_DREFL_M (EFUSE_USB_OTG11_DREFL_V << EFUSE_USB_OTG11_DREFL_S) +#define EFUSE_USB_OTG11_DREFL_V 0x00000003U +#define EFUSE_USB_OTG11_DREFL_S 12 +/** EFUSE_RD_RESERVE_10_238 : RW; bitpos: [31:14]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_10_238 0x0003FFFFU +#define EFUSE_RD_RESERVE_10_238_M (EFUSE_RD_RESERVE_10_238_V << EFUSE_RD_RESERVE_10_238_S) +#define EFUSE_RD_RESERVE_10_238_V 0x0003FFFFU +#define EFUSE_RD_RESERVE_10_238_S 14 /** EFUSE_RD_REPEAT_ERR0_REG register - * Programming error record register 0 of BLOCK0. + * Represents rd_repeat_data_err */ #define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) /** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; - * Indicates a programming error of RD_DIS. + * Represents the programming error of EFUSE_RD_DIS */ #define EFUSE_RD_DIS_ERR 0x0000007FU #define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) #define EFUSE_RD_DIS_ERR_V 0x0000007FU #define EFUSE_RD_DIS_ERR_S 0 -/** EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR : RO; bitpos: [7]; default: 0; - * Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS. +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_ERR : RO; bitpos: [8:7]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1 */ -#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR (BIT(7)) -#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_M (EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S) -#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V 0x00000001U -#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S 7 -/** EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR : RO; bitpos: [8]; default: 0; - * Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS. - */ -#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR (BIT(8)) -#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_M (EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S) -#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V 0x00000001U -#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S 8 +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_ERR 0x00000003U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_ERR_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_ERR_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_ERR_V 0x00000003U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1_ERR_S 7 /** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0; - * Indicates a programming error of DIS_USB_JTAG. + * Represents the programming error of EFUSE_DIS_USB_JTAG */ #define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) #define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) #define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U #define EFUSE_DIS_USB_JTAG_ERR_S 9 -/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [10]; default: 0; - * Indicates a programming error of POWERGLITCH_EN. +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_ERR : RO; bitpos: [10]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2 */ -#define EFUSE_POWERGLITCH_EN_ERR (BIT(10)) -#define EFUSE_POWERGLITCH_EN_ERR_M (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S) -#define EFUSE_POWERGLITCH_EN_ERR_V 0x00000001U -#define EFUSE_POWERGLITCH_EN_ERR_S 10 +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_ERR (BIT(10)) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_ERR_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_ERR_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_ERR_V 0x00000001U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2_ERR_S 10 /** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0; - * Indicates a programming error of DIS_USB_SERIAL_JTAG. + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG */ #define EFUSE_DIS_USB_SERIAL_JTAG_ERR (BIT(11)) #define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S) #define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S 11 /** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; - * Indicates a programming error of DIS_FORCE_DOWNLOAD. + * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD */ #define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 /** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0; - * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + * Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS */ #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR (BIT(13)) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V 0x00000001U #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S 13 /** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0; - * Indicates a programming error of DIS_TWAI. + * Represents the programming error of EFUSE_DIS_TWAI */ #define EFUSE_DIS_TWAI_ERR (BIT(14)) #define EFUSE_DIS_TWAI_ERR_M (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S) #define EFUSE_DIS_TWAI_ERR_V 0x00000001U #define EFUSE_DIS_TWAI_ERR_S 14 /** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0; - * Indicates a programming error of JTAG_SEL_ENABLE. + * Represents the programming error of EFUSE_JTAG_SEL_ENABLE */ #define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) #define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) #define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U #define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 /** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; - * Indicates a programming error of SOFT_DIS_JTAG. + * Represents the programming error of EFUSE_SOFT_DIS_JTAG */ #define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U #define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) #define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U #define EFUSE_SOFT_DIS_JTAG_ERR_S 16 /** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; - * Indicates a programming error of DIS_PAD_JTAG. + * Represents the programming error of EFUSE_DIS_PAD_JTAG */ #define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) #define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) #define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U #define EFUSE_DIS_PAD_JTAG_ERR_S 19 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; - * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT */ #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 -/** EFUSE_USB_DEVICE_DREFH_ERR : RO; bitpos: [22:21]; default: 0; - * Indicates a programming error of USB_DEVICE_DREFH. +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_ERR : RO; bitpos: [24:21]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6 */ -#define EFUSE_USB_DEVICE_DREFH_ERR 0x00000003U -#define EFUSE_USB_DEVICE_DREFH_ERR_M (EFUSE_USB_DEVICE_DREFH_ERR_V << EFUSE_USB_DEVICE_DREFH_ERR_S) -#define EFUSE_USB_DEVICE_DREFH_ERR_V 0x00000003U -#define EFUSE_USB_DEVICE_DREFH_ERR_S 21 -/** EFUSE_USB_OTG11_DREFH_ERR : RO; bitpos: [24:23]; default: 0; - * Indicates a programming error of USB_OTG11_DREFH. - */ -#define EFUSE_USB_OTG11_DREFH_ERR 0x00000003U -#define EFUSE_USB_OTG11_DREFH_ERR_M (EFUSE_USB_OTG11_DREFH_ERR_V << EFUSE_USB_OTG11_DREFH_ERR_S) -#define EFUSE_USB_OTG11_DREFH_ERR_V 0x00000003U -#define EFUSE_USB_OTG11_DREFH_ERR_S 23 +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_ERR 0x0000000FU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_ERR_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_ERR_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_ERR_V 0x0000000FU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6_ERR_S 21 /** EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0; - * Indicates a programming error of USB_PHY_SEL. + * Represents the programming error of EFUSE_USB_PHY_SEL */ #define EFUSE_USB_PHY_SEL_ERR (BIT(25)) #define EFUSE_USB_PHY_SEL_ERR_M (EFUSE_USB_PHY_SEL_ERR_V << EFUSE_USB_PHY_SEL_ERR_S) #define EFUSE_USB_PHY_SEL_ERR_V 0x00000001U #define EFUSE_USB_PHY_SEL_ERR_S 25 -/** EFUSE_HUK_GEN_STATE_LOW_ERR : RO; bitpos: [31:26]; default: 0; - * Indicates a programming error of HUK_GEN_STATE_LOW. +/** EFUSE_HUK_GEN_STATE_ERR : RO; bitpos: [30:26]; default: 0; + * Represents the programming error of EFUSE_HUK_GEN_STATE */ -#define EFUSE_HUK_GEN_STATE_LOW_ERR 0x0000003FU -#define EFUSE_HUK_GEN_STATE_LOW_ERR_M (EFUSE_HUK_GEN_STATE_LOW_ERR_V << EFUSE_HUK_GEN_STATE_LOW_ERR_S) -#define EFUSE_HUK_GEN_STATE_LOW_ERR_V 0x0000003FU -#define EFUSE_HUK_GEN_STATE_LOW_ERR_S 26 +#define EFUSE_HUK_GEN_STATE_ERR 0x0000001FU +#define EFUSE_HUK_GEN_STATE_ERR_M (EFUSE_HUK_GEN_STATE_ERR_V << EFUSE_HUK_GEN_STATE_ERR_S) +#define EFUSE_HUK_GEN_STATE_ERR_V 0x0000001FU +#define EFUSE_HUK_GEN_STATE_ERR_S 26 +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_ERR : RO; bitpos: [31]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7 + */ +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_ERR (BIT(31)) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_ERR_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_ERR_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_ERR_V 0x00000001U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7_ERR_S 31 /** EFUSE_RD_REPEAT_ERR1_REG register - * Programming error record register 1 of BLOCK0. + * Represents rd_repeat_data_err */ #define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) -/** EFUSE_KM_HUK_GEN_STATE_HIGH_ERR : RO; bitpos: [2:0]; default: 0; - * Indicates a programming error of HUK_GEN_STATE_HIGH. +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_ERR : RO; bitpos: [2:0]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10 */ -#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR 0x00000007U -#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_M (EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V << EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S) -#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V 0x00000007U -#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S 0 -/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [4:3]; default: 0; - * Indicates a programming error of KM_RND_SWITCH_CYCLE. +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_ERR 0x00000007U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_ERR_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_ERR_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_ERR_V 0x00000007U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10_ERR_S 0 +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_ERR : RO; bitpos: [3]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11 */ -#define EFUSE_KM_RND_SWITCH_CYCLE_ERR 0x00000003U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_ERR (BIT(3)) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_ERR_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_ERR_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_ERR_V 0x00000001U +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11_ERR_S 3 +/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [4]; default: 0; + * Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE + */ +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR (BIT(4)) #define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S) -#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V 0x00000003U -#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S 3 +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V 0x00000001U +#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S 4 /** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [8:5]; default: 0; - * Indicates a programming error of KM_DEPLOY_ONLY_ONCE. + * Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE */ #define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR 0x0000000FU #define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S) #define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V 0x0000000FU #define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S 5 /** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [12:9]; default: 0; - * Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY. + * Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY */ #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR 0x0000000FU #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S) #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V 0x0000000FU #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S 9 /** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [13]; default: 0; - * Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY. + * Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY */ #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR (BIT(13)) #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S) #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V 0x00000001U #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S 13 -/** EFUSE_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [14]; default: 0; - * Indicates a programming error of XTS_KEY_LENGTH_256. +/** EFUSE_KM_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [14]; default: 0; + * Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256 */ -#define EFUSE_XTS_KEY_LENGTH_256_ERR (BIT(14)) -#define EFUSE_XTS_KEY_LENGTH_256_ERR_M (EFUSE_XTS_KEY_LENGTH_256_ERR_V << EFUSE_XTS_KEY_LENGTH_256_ERR_S) -#define EFUSE_XTS_KEY_LENGTH_256_ERR_V 0x00000001U -#define EFUSE_XTS_KEY_LENGTH_256_ERR_S 14 -/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; - * Indicates a programming error of WDT_DELAY_SEL. +#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR (BIT(14)) +#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_M (EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V << EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S) +#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V 0x00000001U +#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S 14 +/** EFUSE_ECC_FORCE_CONST_TIME_ERR : RO; bitpos: [15]; default: 0; + * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME */ -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U +#define EFUSE_ECC_FORCE_CONST_TIME_ERR (BIT(15)) +#define EFUSE_ECC_FORCE_CONST_TIME_ERR_M (EFUSE_ECC_FORCE_CONST_TIME_ERR_V << EFUSE_ECC_FORCE_CONST_TIME_ERR_S) +#define EFUSE_ECC_FORCE_CONST_TIME_ERR_V 0x00000001U +#define EFUSE_ECC_FORCE_CONST_TIME_ERR_S 15 +/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17]; default: 0; + * Represents the programming error of EFUSE_WDT_DELAY_SEL + */ +#define EFUSE_WDT_DELAY_SEL_ERR (BIT(17)) #define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) -#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U -#define EFUSE_WDT_DELAY_SEL_ERR_S 16 +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000001U +#define EFUSE_WDT_DELAY_SEL_ERR_S 17 /** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; - * Indicates a programming error of SPI_BOOT_CRYPT_CNT. + * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT */ #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 /** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 */ #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 /** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 */ #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 /** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 */ #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 /** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; - * Indicates a programming error of KEY_PURPOSE_0. + * Represents the programming error of EFUSE_KEY_PURPOSE_0 */ #define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) #define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_0_ERR_S 24 /** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; - * Indicates a programming error of KEY_PURPOSE_1. + * Represents the programming error of EFUSE_KEY_PURPOSE_1 */ #define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) @@ -2277,102 +2121,95 @@ extern "C" { #define EFUSE_KEY_PURPOSE_1_ERR_S 28 /** EFUSE_RD_REPEAT_ERR2_REG register - * Programming error record register 2 of BLOCK0. + * Represents rd_repeat_data_err */ #define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) /** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; - * Indicates a programming error of KEY_PURPOSE_2. + * Represents the programming error of EFUSE_KEY_PURPOSE_2 */ #define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) #define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_2_ERR_S 0 /** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; - * Indicates a programming error of KEY_PURPOSE_3. + * Represents the programming error of EFUSE_KEY_PURPOSE_3 */ #define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) #define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_3_ERR_S 4 /** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; - * Indicates a programming error of KEY_PURPOSE_4. + * Represents the programming error of EFUSE_KEY_PURPOSE_4 */ #define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) #define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_4_ERR_S 8 /** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; - * Indicates a programming error of KEY_PURPOSE_5. + * Represents the programming error of EFUSE_KEY_PURPOSE_5 */ #define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU #define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) #define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU #define EFUSE_KEY_PURPOSE_5_ERR_S 12 /** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0; - * Indicates a programming error of SEC_DPA_LEVEL. + * Represents the programming error of EFUSE_SEC_DPA_LEVEL */ #define EFUSE_SEC_DPA_LEVEL_ERR 0x00000003U #define EFUSE_SEC_DPA_LEVEL_ERR_M (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S) #define EFUSE_SEC_DPA_LEVEL_ERR_V 0x00000003U #define EFUSE_SEC_DPA_LEVEL_ERR_S 16 -/** EFUSE_ECDSA_ENABLE_SOFT_K_ERR : RO; bitpos: [18]; default: 0; - * Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K. +/** EFUSE_XTS_DPA_CLK_ENABLE_ERR : RO; bitpos: [19]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE */ -#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR (BIT(18)) -#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_M (EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V << EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S) -#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V 0x00000001U -#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S 18 -/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0; - * Indicates a programming error of CRYPT_DPA_ENABLE. - */ -#define EFUSE_CRYPT_DPA_ENABLE_ERR (BIT(19)) -#define EFUSE_CRYPT_DPA_ENABLE_ERR_M (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S) -#define EFUSE_CRYPT_DPA_ENABLE_ERR_V 0x00000001U -#define EFUSE_CRYPT_DPA_ENABLE_ERR_S 19 +#define EFUSE_XTS_DPA_CLK_ENABLE_ERR (BIT(19)) +#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_M (EFUSE_XTS_DPA_CLK_ENABLE_ERR_V << EFUSE_XTS_DPA_CLK_ENABLE_ERR_S) +#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_V 0x00000001U +#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_S 19 /** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; - * Indicates a programming error of SECURE_BOOT_EN. + * Represents the programming error of EFUSE_SECURE_BOOT_EN */ #define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) #define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) #define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_EN_ERR_S 20 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; - * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE */ #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 -/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [23]; default: 0; - * Indicates a programming error of FLASH_TYPE. +/** EFUSE_KM_DEPLOY_ONLY_ONCE_H_ERR : RO; bitpos: [22]; default: 0; + * Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE_H */ -#define EFUSE_FLASH_TYPE_ERR (BIT(23)) -#define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S) -#define EFUSE_FLASH_TYPE_ERR_V 0x00000001U -#define EFUSE_FLASH_TYPE_ERR_S 23 -/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [25:24]; default: 0; - * Indicates a programming error of FLASH_PAGE_SIZE. +#define EFUSE_KM_DEPLOY_ONLY_ONCE_H_ERR (BIT(22)) +#define EFUSE_KM_DEPLOY_ONLY_ONCE_H_ERR_M (EFUSE_KM_DEPLOY_ONLY_ONCE_H_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_H_ERR_S) +#define EFUSE_KM_DEPLOY_ONLY_ONCE_H_ERR_V 0x00000001U +#define EFUSE_KM_DEPLOY_ONLY_ONCE_H_ERR_S 22 +/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_ERR : RO; bitpos: [23]; default: 0; + * Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY_H */ -#define EFUSE_FLASH_PAGE_SIZE_ERR 0x00000003U -#define EFUSE_FLASH_PAGE_SIZE_ERR_M (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S) -#define EFUSE_FLASH_PAGE_SIZE_ERR_V 0x00000003U -#define EFUSE_FLASH_PAGE_SIZE_ERR_S 24 +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_ERR (BIT(23)) +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_ERR_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_ERR_S) +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_ERR_V 0x00000001U +#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_H_ERR_S 23 /** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [26]; default: 0; - * Indicates a programming error of FLASH_ECC_EN. + * Represents the programming error of EFUSE_FLASH_ECC_EN */ #define EFUSE_FLASH_ECC_EN_ERR (BIT(26)) #define EFUSE_FLASH_ECC_EN_ERR_M (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S) #define EFUSE_FLASH_ECC_EN_ERR_V 0x00000001U #define EFUSE_FLASH_ECC_EN_ERR_S 26 /** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR : RO; bitpos: [27]; default: 0; - * Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE. + * Represents the programming error of EFUSE_DIS_USB_OTG_DOWNLOAD_MODE */ #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR (BIT(27)) #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S) #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S 27 /** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; - * Indicates a programming error of FLASH_TPUW. + * Represents the programming error of EFUSE_FLASH_TPUW */ #define EFUSE_FLASH_TPUW_ERR 0x0000000FU #define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) @@ -2380,335 +2217,444 @@ extern "C" { #define EFUSE_FLASH_TPUW_ERR_S 28 /** EFUSE_RD_REPEAT_ERR3_REG register - * Programming error record register 3 of BLOCK0. + * Represents rd_repeat_data_err */ #define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) /** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; - * Indicates a programming error of DIS_DOWNLOAD_MODE. + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE */ #define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) #define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 /** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0; - * Indicates a programming error of DIS_DIRECT_BOOT. + * Represents the programming error of EFUSE_DIS_DIRECT_BOOT */ #define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) #define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) #define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0; - * Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR. + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT */ #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR (BIT(2)) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S 2 /** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0; - * TBD + * Represents the programming error of EFUSE_LOCK_KM_KEY */ #define EFUSE_LOCK_KM_KEY_ERR (BIT(3)) #define EFUSE_LOCK_KM_KEY_ERR_M (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S) #define EFUSE_LOCK_KM_KEY_ERR_V 0x00000001U #define EFUSE_LOCK_KM_KEY_ERR_S 3 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; - * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE */ #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 /** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; - * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + * Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD */ #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 /** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; - * Indicates a programming error of UART_PRINT_CONTROL. + * Represents the programming error of EFUSE_UART_PRINT_CONTROL */ #define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U #define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) #define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U #define EFUSE_UART_PRINT_CONTROL_ERR_S 6 /** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0; - * Indicates a programming error of FORCE_SEND_RESUME. + * Represents the programming error of EFUSE_FORCE_SEND_RESUME */ #define EFUSE_FORCE_SEND_RESUME_ERR (BIT(8)) #define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) #define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U #define EFUSE_FORCE_SEND_RESUME_ERR_S 8 /** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0; - * Indicates a programming error of SECURE VERSION. + * Represents the programming error of EFUSE_SECURE_VERSION */ #define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU #define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) #define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU #define EFUSE_SECURE_VERSION_ERR_S 9 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0; - * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE */ #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR (BIT(25)) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V 0x00000001U #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S 25 /** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0; - * Indicates a programming error of HYS_EN_PAD. + * Represents the programming error of EFUSE_HYS_EN_PAD */ #define EFUSE_HYS_EN_PAD_ERR (BIT(26)) #define EFUSE_HYS_EN_PAD_ERR_M (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S) #define EFUSE_HYS_EN_PAD_ERR_V 0x00000001U #define EFUSE_HYS_EN_PAD_ERR_S 26 -/** EFUSE_DCDC_VSET_ERR : RO; bitpos: [31:27]; default: 0; - * Indicates a programming error of DCDC_VSET. +/** EFUSE_KEY_PURPOSE_0_H_ERR : RO; bitpos: [27]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_0_H */ -#define EFUSE_DCDC_VSET_ERR 0x0000001FU -#define EFUSE_DCDC_VSET_ERR_M (EFUSE_DCDC_VSET_ERR_V << EFUSE_DCDC_VSET_ERR_S) -#define EFUSE_DCDC_VSET_ERR_V 0x0000001FU -#define EFUSE_DCDC_VSET_ERR_S 27 +#define EFUSE_KEY_PURPOSE_0_H_ERR (BIT(27)) +#define EFUSE_KEY_PURPOSE_0_H_ERR_M (EFUSE_KEY_PURPOSE_0_H_ERR_V << EFUSE_KEY_PURPOSE_0_H_ERR_S) +#define EFUSE_KEY_PURPOSE_0_H_ERR_V 0x00000001U +#define EFUSE_KEY_PURPOSE_0_H_ERR_S 27 +/** EFUSE_KEY_PURPOSE_1_H_ERR : RO; bitpos: [28]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_1_H + */ +#define EFUSE_KEY_PURPOSE_1_H_ERR (BIT(28)) +#define EFUSE_KEY_PURPOSE_1_H_ERR_M (EFUSE_KEY_PURPOSE_1_H_ERR_V << EFUSE_KEY_PURPOSE_1_H_ERR_S) +#define EFUSE_KEY_PURPOSE_1_H_ERR_V 0x00000001U +#define EFUSE_KEY_PURPOSE_1_H_ERR_S 28 +/** EFUSE_KEY_PURPOSE_2_H_ERR : RO; bitpos: [29]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_2_H + */ +#define EFUSE_KEY_PURPOSE_2_H_ERR (BIT(29)) +#define EFUSE_KEY_PURPOSE_2_H_ERR_M (EFUSE_KEY_PURPOSE_2_H_ERR_V << EFUSE_KEY_PURPOSE_2_H_ERR_S) +#define EFUSE_KEY_PURPOSE_2_H_ERR_V 0x00000001U +#define EFUSE_KEY_PURPOSE_2_H_ERR_S 29 +/** EFUSE_KEY_PURPOSE_3_H_ERR : RO; bitpos: [30]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_3_H + */ +#define EFUSE_KEY_PURPOSE_3_H_ERR (BIT(30)) +#define EFUSE_KEY_PURPOSE_3_H_ERR_M (EFUSE_KEY_PURPOSE_3_H_ERR_V << EFUSE_KEY_PURPOSE_3_H_ERR_S) +#define EFUSE_KEY_PURPOSE_3_H_ERR_V 0x00000001U +#define EFUSE_KEY_PURPOSE_3_H_ERR_S 30 +/** EFUSE_KEY_PURPOSE_4_H_ERR : RO; bitpos: [31]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_4_H + */ +#define EFUSE_KEY_PURPOSE_4_H_ERR (BIT(31)) +#define EFUSE_KEY_PURPOSE_4_H_ERR_M (EFUSE_KEY_PURPOSE_4_H_ERR_V << EFUSE_KEY_PURPOSE_4_H_ERR_S) +#define EFUSE_KEY_PURPOSE_4_H_ERR_V 0x00000001U +#define EFUSE_KEY_PURPOSE_4_H_ERR_S 31 /** EFUSE_RD_REPEAT_ERR4_REG register - * Programming error record register 4 of BLOCK0. + * Represents rd_repeat_data_err */ #define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) /** EFUSE_PXA0_TIEH_SEL_0_ERR : RO; bitpos: [1:0]; default: 0; - * Indicates a programming error of 0PXA_TIEH_SEL_0. + * Represents the programming error of EFUSE_0PXA_TIEH_SEL_0 */ #define EFUSE_PXA0_TIEH_SEL_0_ERR 0x00000003U #define EFUSE_PXA0_TIEH_SEL_0_ERR_M (EFUSE_PXA0_TIEH_SEL_0_ERR_V << EFUSE_PXA0_TIEH_SEL_0_ERR_S) #define EFUSE_PXA0_TIEH_SEL_0_ERR_V 0x00000003U #define EFUSE_PXA0_TIEH_SEL_0_ERR_S 0 -/** EFUSE_PXA0_TIEH_SEL_1_ERR : RO; bitpos: [3:2]; default: 0; - * Indicates a programming error of 0PXA_TIEH_SEL_1. +/** EFUSE_PVT_GLITCH_EN_ERR : RO; bitpos: [2]; default: 0; + * Represents the programming error of EFUSE_PVT_GLITCH_EN */ -#define EFUSE_PXA0_TIEH_SEL_1_ERR 0x00000003U -#define EFUSE_PXA0_TIEH_SEL_1_ERR_M (EFUSE_PXA0_TIEH_SEL_1_ERR_V << EFUSE_PXA0_TIEH_SEL_1_ERR_S) -#define EFUSE_PXA0_TIEH_SEL_1_ERR_V 0x00000003U -#define EFUSE_PXA0_TIEH_SEL_1_ERR_S 2 -/** EFUSE_PXA0_TIEH_SEL_2_ERR : RO; bitpos: [5:4]; default: 0; - * Indicates a programming error of 0PXA_TIEH_SEL_2. +#define EFUSE_PVT_GLITCH_EN_ERR (BIT(2)) +#define EFUSE_PVT_GLITCH_EN_ERR_M (EFUSE_PVT_GLITCH_EN_ERR_V << EFUSE_PVT_GLITCH_EN_ERR_S) +#define EFUSE_PVT_GLITCH_EN_ERR_V 0x00000001U +#define EFUSE_PVT_GLITCH_EN_ERR_S 2 +/** EFUSE_KEY_PURPOSE_5_H_ERR : RO; bitpos: [4]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_5_H */ -#define EFUSE_PXA0_TIEH_SEL_2_ERR 0x00000003U -#define EFUSE_PXA0_TIEH_SEL_2_ERR_M (EFUSE_PXA0_TIEH_SEL_2_ERR_V << EFUSE_PXA0_TIEH_SEL_2_ERR_S) -#define EFUSE_PXA0_TIEH_SEL_2_ERR_V 0x00000003U -#define EFUSE_PXA0_TIEH_SEL_2_ERR_S 4 -/** EFUSE_PXA0_TIEH_SEL_3_ERR : RO; bitpos: [7:6]; default: 0; - * Indicates a programming error of 0PXA_TIEH_SEL_3. +#define EFUSE_KEY_PURPOSE_5_H_ERR (BIT(4)) +#define EFUSE_KEY_PURPOSE_5_H_ERR_M (EFUSE_KEY_PURPOSE_5_H_ERR_V << EFUSE_KEY_PURPOSE_5_H_ERR_S) +#define EFUSE_KEY_PURPOSE_5_H_ERR_V 0x00000001U +#define EFUSE_KEY_PURPOSE_5_H_ERR_S 4 +/** EFUSE_KM_DISABLE_DEPLOY_MODE_H_ERR : RO; bitpos: [7]; default: 0; + * Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE_H */ -#define EFUSE_PXA0_TIEH_SEL_3_ERR 0x00000003U -#define EFUSE_PXA0_TIEH_SEL_3_ERR_M (EFUSE_PXA0_TIEH_SEL_3_ERR_V << EFUSE_PXA0_TIEH_SEL_3_ERR_S) -#define EFUSE_PXA0_TIEH_SEL_3_ERR_V 0x00000003U -#define EFUSE_PXA0_TIEH_SEL_3_ERR_S 6 +#define EFUSE_KM_DISABLE_DEPLOY_MODE_H_ERR (BIT(7)) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_H_ERR_M (EFUSE_KM_DISABLE_DEPLOY_MODE_H_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_H_ERR_S) +#define EFUSE_KM_DISABLE_DEPLOY_MODE_H_ERR_V 0x00000001U +#define EFUSE_KM_DISABLE_DEPLOY_MODE_H_ERR_S 7 /** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [11:8]; default: 0; - * TBD. + * Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE */ #define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR 0x0000000FU #define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S) #define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V 0x0000000FU #define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S 8 -/** EFUSE_USB_DEVICE_DREFL_ERR : RO; bitpos: [13:12]; default: 0; - * Indicates a programming error of USB_DEVICE_DREFL. +/** EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR : RO; bitpos: [17:16]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL */ -#define EFUSE_USB_DEVICE_DREFL_ERR 0x00000003U -#define EFUSE_USB_DEVICE_DREFL_ERR_M (EFUSE_USB_DEVICE_DREFL_ERR_V << EFUSE_USB_DEVICE_DREFL_ERR_S) -#define EFUSE_USB_DEVICE_DREFL_ERR_V 0x00000003U -#define EFUSE_USB_DEVICE_DREFL_ERR_S 12 -/** EFUSE_USB_OTG11_DREFL_ERR : RO; bitpos: [15:14]; default: 0; - * Indicates a programming error of USB_OTG11_DREFL. - */ -#define EFUSE_USB_OTG11_DREFL_ERR 0x00000003U -#define EFUSE_USB_OTG11_DREFL_ERR_M (EFUSE_USB_OTG11_DREFL_ERR_V << EFUSE_USB_OTG11_DREFL_ERR_S) -#define EFUSE_USB_OTG11_DREFL_ERR_V 0x00000003U -#define EFUSE_USB_OTG11_DREFL_ERR_S 14 +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S) +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V 0x00000003U +#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S 16 /** EFUSE_HP_PWR_SRC_SEL_ERR : RO; bitpos: [18]; default: 0; - * Indicates a programming error of HP_PWR_SRC_SEL. + * Represents the programming error of EFUSE_HP_PWR_SRC_SEL */ #define EFUSE_HP_PWR_SRC_SEL_ERR (BIT(18)) #define EFUSE_HP_PWR_SRC_SEL_ERR_M (EFUSE_HP_PWR_SRC_SEL_ERR_V << EFUSE_HP_PWR_SRC_SEL_ERR_S) #define EFUSE_HP_PWR_SRC_SEL_ERR_V 0x00000001U #define EFUSE_HP_PWR_SRC_SEL_ERR_S 18 -/** EFUSE_DCDC_VSET_EN_ERR : RO; bitpos: [19]; default: 0; - * Indicates a programming error of DCDC_VSET_EN. +/** EFUSE_SECURE_BOOT_SHA384_EN_ERR : RO; bitpos: [19]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_SHA384_EN */ -#define EFUSE_DCDC_VSET_EN_ERR (BIT(19)) -#define EFUSE_DCDC_VSET_EN_ERR_M (EFUSE_DCDC_VSET_EN_ERR_V << EFUSE_DCDC_VSET_EN_ERR_S) -#define EFUSE_DCDC_VSET_EN_ERR_V 0x00000001U -#define EFUSE_DCDC_VSET_EN_ERR_S 19 +#define EFUSE_SECURE_BOOT_SHA384_EN_ERR (BIT(19)) +#define EFUSE_SECURE_BOOT_SHA384_EN_ERR_M (EFUSE_SECURE_BOOT_SHA384_EN_ERR_V << EFUSE_SECURE_BOOT_SHA384_EN_ERR_S) +#define EFUSE_SECURE_BOOT_SHA384_EN_ERR_V 0x00000001U +#define EFUSE_SECURE_BOOT_SHA384_EN_ERR_S 19 /** EFUSE_DIS_WDT_ERR : RO; bitpos: [20]; default: 0; - * Indicates a programming error of DIS_WDT. + * Represents the programming error of EFUSE_DIS_WDT */ #define EFUSE_DIS_WDT_ERR (BIT(20)) #define EFUSE_DIS_WDT_ERR_M (EFUSE_DIS_WDT_ERR_V << EFUSE_DIS_WDT_ERR_S) #define EFUSE_DIS_WDT_ERR_V 0x00000001U #define EFUSE_DIS_WDT_ERR_S 20 /** EFUSE_DIS_SWD_ERR : RO; bitpos: [21]; default: 0; - * Indicates a programming error of DIS_SWD. + * Represents the programming error of EFUSE_DIS_SWD */ #define EFUSE_DIS_SWD_ERR (BIT(21)) #define EFUSE_DIS_SWD_ERR_M (EFUSE_DIS_SWD_ERR_V << EFUSE_DIS_SWD_ERR_S) #define EFUSE_DIS_SWD_ERR_V 0x00000001U #define EFUSE_DIS_SWD_ERR_S 21 +/** EFUSE_PVT_GLITCH_MODE_ERR : RO; bitpos: [23:22]; default: 0; + * Represents the programming error of EFUSE_PVT_GLITCH_MODE + */ +#define EFUSE_PVT_GLITCH_MODE_ERR 0x00000003U +#define EFUSE_PVT_GLITCH_MODE_ERR_M (EFUSE_PVT_GLITCH_MODE_ERR_V << EFUSE_PVT_GLITCH_MODE_ERR_S) +#define EFUSE_PVT_GLITCH_MODE_ERR_V 0x00000003U +#define EFUSE_PVT_GLITCH_MODE_ERR_S 22 + +/** EFUSE_ECDSA_REG register + * eFuse status register. + */ +#define EFUSE_ECDSA_REG (DR_REG_EFUSE_BASE + 0x1b0) +/** EFUSE_CFG_ECDSA_P192_BLK : R/W; bitpos: [3:0]; default: 0; + * Configures which block to use for ECDSA P192 key output. + */ +#define EFUSE_CFG_ECDSA_P192_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_P192_BLK_M (EFUSE_CFG_ECDSA_P192_BLK_V << EFUSE_CFG_ECDSA_P192_BLK_S) +#define EFUSE_CFG_ECDSA_P192_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_P192_BLK_S 0 +/** EFUSE_CFG_ECDSA_P256_BLK : R/W; bitpos: [7:4]; default: 0; + * Configures which block to use for ECDSA P256 key output. + */ +#define EFUSE_CFG_ECDSA_P256_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_P256_BLK_M (EFUSE_CFG_ECDSA_P256_BLK_V << EFUSE_CFG_ECDSA_P256_BLK_S) +#define EFUSE_CFG_ECDSA_P256_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_P256_BLK_S 4 +/** EFUSE_CFG_ECDSA_P384_L_BLK : R/W; bitpos: [11:8]; default: 0; + * Configures which block to use for ECDSA P384 key low part output. + */ +#define EFUSE_CFG_ECDSA_P384_L_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_P384_L_BLK_M (EFUSE_CFG_ECDSA_P384_L_BLK_V << EFUSE_CFG_ECDSA_P384_L_BLK_S) +#define EFUSE_CFG_ECDSA_P384_L_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_P384_L_BLK_S 8 +/** EFUSE_CFG_ECDSA_P384_H_BLK : R/W; bitpos: [15:12]; default: 0; + * Configures which block to use for ECDSA P256 key high part output. + */ +#define EFUSE_CFG_ECDSA_P384_H_BLK 0x0000000FU +#define EFUSE_CFG_ECDSA_P384_H_BLK_M (EFUSE_CFG_ECDSA_P384_H_BLK_V << EFUSE_CFG_ECDSA_P384_H_BLK_S) +#define EFUSE_CFG_ECDSA_P384_H_BLK_V 0x0000000FU +#define EFUSE_CFG_ECDSA_P384_H_BLK_S 12 +/** EFUSE_CUR_ECDSA_P192_BLK : RO; bitpos: [19:16]; default: 0; + * Represents which block is used for ECDSA P192 key output. + */ +#define EFUSE_CUR_ECDSA_P192_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_P192_BLK_M (EFUSE_CUR_ECDSA_P192_BLK_V << EFUSE_CUR_ECDSA_P192_BLK_S) +#define EFUSE_CUR_ECDSA_P192_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_P192_BLK_S 16 +/** EFUSE_CUR_ECDSA_P256_BLK : RO; bitpos: [23:20]; default: 0; + * Represents which block is used for ECDSA P256 key output. + */ +#define EFUSE_CUR_ECDSA_P256_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_P256_BLK_M (EFUSE_CUR_ECDSA_P256_BLK_V << EFUSE_CUR_ECDSA_P256_BLK_S) +#define EFUSE_CUR_ECDSA_P256_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_P256_BLK_S 20 +/** EFUSE_CUR_ECDSA_P384_L_BLK : RO; bitpos: [27:24]; default: 0; + * Represents which block is used for ECDSA P384 key low part output. + */ +#define EFUSE_CUR_ECDSA_P384_L_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_P384_L_BLK_M (EFUSE_CUR_ECDSA_P384_L_BLK_V << EFUSE_CUR_ECDSA_P384_L_BLK_S) +#define EFUSE_CUR_ECDSA_P384_L_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_P384_L_BLK_S 24 +/** EFUSE_CUR_ECDSA_P384_H_BLK : RO; bitpos: [31:28]; default: 0; + * Represents which block is used for ECDSA P384 key high part output. + */ +#define EFUSE_CUR_ECDSA_P384_H_BLK 0x0000000FU +#define EFUSE_CUR_ECDSA_P384_H_BLK_M (EFUSE_CUR_ECDSA_P384_H_BLK_V << EFUSE_CUR_ECDSA_P384_H_BLK_S) +#define EFUSE_CUR_ECDSA_P384_H_BLK_V 0x0000000FU +#define EFUSE_CUR_ECDSA_P384_H_BLK_S 28 /** EFUSE_RD_RS_ERR0_REG register - * Programming error record register 0 of BLOCK1-10. + * Represents rd_rs_data_err */ #define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) -/** EFUSE_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. +/** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_mac_sys */ -#define EFUSE_MAC_SYS_ERR_NUM 0x00000007U -#define EFUSE_MAC_SYS_ERR_NUM_M (EFUSE_MAC_SYS_ERR_NUM_V << EFUSE_MAC_SYS_ERR_NUM_S) -#define EFUSE_MAC_SYS_ERR_NUM_V 0x00000007U -#define EFUSE_MAC_SYS_ERR_NUM_S 0 -/** EFUSE_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. +#define EFUSE_RD_MAC_SYS_ERR_NUM 0x00000007U +#define EFUSE_RD_MAC_SYS_ERR_NUM_M (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S) +#define EFUSE_RD_MAC_SYS_ERR_NUM_V 0x00000007U +#define EFUSE_RD_MAC_SYS_ERR_NUM_S 0 +/** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number + * of error bytes is over 6. */ -#define EFUSE_MAC_SYS_FAIL (BIT(3)) -#define EFUSE_MAC_SYS_FAIL_M (EFUSE_MAC_SYS_FAIL_V << EFUSE_MAC_SYS_FAIL_S) -#define EFUSE_MAC_SYS_FAIL_V 0x00000001U -#define EFUSE_MAC_SYS_FAIL_S 3 -/** EFUSE_SYS_PART1_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_MAC_SYS_FAIL (BIT(3)) +#define EFUSE_RD_MAC_SYS_FAIL_M (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S) +#define EFUSE_RD_MAC_SYS_FAIL_V 0x00000001U +#define EFUSE_RD_MAC_SYS_FAIL_S 3 +/** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_sys_part1_data */ -#define EFUSE_SYS_PART1_ERR_NUM 0x00000007U -#define EFUSE_SYS_PART1_ERR_NUM_M (EFUSE_SYS_PART1_ERR_NUM_V << EFUSE_SYS_PART1_ERR_NUM_S) -#define EFUSE_SYS_PART1_ERR_NUM_V 0x00000007U -#define EFUSE_SYS_PART1_ERR_NUM_S 4 -/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part1 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S) +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S 4 +/** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed + * and the number of error bytes is over 6. */ -#define EFUSE_SYS_PART1_FAIL (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) -#define EFUSE_SYS_PART1_FAIL_V 0x00000001U -#define EFUSE_SYS_PART1_FAIL_S 7 -/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_SYS_PART1_DATA_FAIL (BIT(7)) +#define EFUSE_RD_SYS_PART1_DATA_FAIL_M (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S) +#define EFUSE_RD_SYS_PART1_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_SYS_PART1_DATA_FAIL_S 7 +/** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_usr_data */ -#define EFUSE_USR_DATA_ERR_NUM 0x00000007U -#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) -#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U -#define EFUSE_USR_DATA_ERR_NUM_S 8 -/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; - * 0: Means no failure and that the user data is reliable 1: Means that programming - * user data failed and the number of error bytes is over 6. +#define EFUSE_RD_USR_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_USR_DATA_ERR_NUM_M (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S) +#define EFUSE_RD_USR_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_USR_DATA_ERR_NUM_S 8 +/** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the + * number of error bytes is over 6. */ -#define EFUSE_USR_DATA_FAIL (BIT(11)) -#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) -#define EFUSE_USR_DATA_FAIL_V 0x00000001U -#define EFUSE_USR_DATA_FAIL_S 11 -/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_USR_DATA_FAIL (BIT(11)) +#define EFUSE_RD_USR_DATA_FAIL_M (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S) +#define EFUSE_RD_USR_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_USR_DATA_FAIL_S 11 +/** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key0_data */ -#define EFUSE_KEY0_ERR_NUM 0x00000007U -#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) -#define EFUSE_KEY0_ERR_NUM_V 0x00000007U -#define EFUSE_KEY0_ERR_NUM_S 12 -/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; - * 0: Means no failure and that the data of key0 is reliable 1: Means that programming - * key0 failed and the number of error bytes is over 6. +#define EFUSE_RD_KEY0_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY0_DATA_ERR_NUM_M (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY0_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY0_DATA_ERR_NUM_S 12 +/** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the + * number of error bytes is over 6. */ -#define EFUSE_KEY0_FAIL (BIT(15)) -#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) -#define EFUSE_KEY0_FAIL_V 0x00000001U -#define EFUSE_KEY0_FAIL_S 15 -/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_KEY0_DATA_FAIL (BIT(15)) +#define EFUSE_RD_KEY0_DATA_FAIL_M (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S) +#define EFUSE_RD_KEY0_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY0_DATA_FAIL_S 15 +/** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key1_data */ -#define EFUSE_KEY1_ERR_NUM 0x00000007U -#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) -#define EFUSE_KEY1_ERR_NUM_V 0x00000007U -#define EFUSE_KEY1_ERR_NUM_S 16 -/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; - * 0: Means no failure and that the data of key1 is reliable 1: Means that programming - * key1 failed and the number of error bytes is over 6. +#define EFUSE_RD_KEY1_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY1_DATA_ERR_NUM_M (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY1_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY1_DATA_ERR_NUM_S 16 +/** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the + * number of error bytes is over 6. */ -#define EFUSE_KEY1_FAIL (BIT(19)) -#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) -#define EFUSE_KEY1_FAIL_V 0x00000001U -#define EFUSE_KEY1_FAIL_S 19 -/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_KEY1_DATA_FAIL (BIT(19)) +#define EFUSE_RD_KEY1_DATA_FAIL_M (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S) +#define EFUSE_RD_KEY1_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY1_DATA_FAIL_S 19 +/** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key2_data */ -#define EFUSE_KEY2_ERR_NUM 0x00000007U -#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) -#define EFUSE_KEY2_ERR_NUM_V 0x00000007U -#define EFUSE_KEY2_ERR_NUM_S 20 -/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; - * 0: Means no failure and that the data of key2 is reliable 1: Means that programming - * key2 failed and the number of error bytes is over 6. +#define EFUSE_RD_KEY2_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY2_DATA_ERR_NUM_M (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY2_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY2_DATA_ERR_NUM_S 20 +/** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the + * number of error bytes is over 6. */ -#define EFUSE_KEY2_FAIL (BIT(23)) -#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) -#define EFUSE_KEY2_FAIL_V 0x00000001U -#define EFUSE_KEY2_FAIL_S 23 -/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_KEY2_DATA_FAIL (BIT(23)) +#define EFUSE_RD_KEY2_DATA_FAIL_M (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S) +#define EFUSE_RD_KEY2_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY2_DATA_FAIL_S 23 +/** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key3_data */ -#define EFUSE_KEY3_ERR_NUM 0x00000007U -#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) -#define EFUSE_KEY3_ERR_NUM_V 0x00000007U -#define EFUSE_KEY3_ERR_NUM_S 24 -/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; - * 0: Means no failure and that the data of key3 is reliable 1: Means that programming - * key3 failed and the number of error bytes is over 6. +#define EFUSE_RD_KEY3_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY3_DATA_ERR_NUM_M (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY3_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY3_DATA_ERR_NUM_S 24 +/** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the + * number of error bytes is over 6. */ -#define EFUSE_KEY3_FAIL (BIT(27)) -#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) -#define EFUSE_KEY3_FAIL_V 0x00000001U -#define EFUSE_KEY3_FAIL_S 27 -/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_KEY3_DATA_FAIL (BIT(27)) +#define EFUSE_RD_KEY3_DATA_FAIL_M (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S) +#define EFUSE_RD_KEY3_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY3_DATA_FAIL_S 27 +/** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key4_data */ -#define EFUSE_KEY4_ERR_NUM 0x00000007U -#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) -#define EFUSE_KEY4_ERR_NUM_V 0x00000007U -#define EFUSE_KEY4_ERR_NUM_S 28 -/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; - * 0: Means no failure and that the data of key4 is reliable 1: Means that programming - * key4 failed and the number of error bytes is over 6. +#define EFUSE_RD_KEY4_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY4_DATA_ERR_NUM_M (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY4_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY4_DATA_ERR_NUM_S 28 +/** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the + * number of error bytes is over 6. */ -#define EFUSE_KEY4_FAIL (BIT(31)) -#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) -#define EFUSE_KEY4_FAIL_V 0x00000001U -#define EFUSE_KEY4_FAIL_S 31 +#define EFUSE_RD_KEY4_DATA_FAIL (BIT(31)) +#define EFUSE_RD_KEY4_DATA_FAIL_M (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S) +#define EFUSE_RD_KEY4_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY4_DATA_FAIL_S 31 /** EFUSE_RD_RS_ERR1_REG register - * Programming error record register 1 of BLOCK1-10. + * Represents rd_rs_data_err */ #define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) -/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. +/** EFUSE_RD_KEY5_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_key5_data */ -#define EFUSE_KEY5_ERR_NUM 0x00000007U -#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) -#define EFUSE_KEY5_ERR_NUM_V 0x00000007U -#define EFUSE_KEY5_ERR_NUM_S 0 -/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of key5 is reliable 1: Means that programming - * key5 failed and the number of error bytes is over 6. +#define EFUSE_RD_KEY5_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_KEY5_DATA_ERR_NUM_M (EFUSE_RD_KEY5_DATA_ERR_NUM_V << EFUSE_RD_KEY5_DATA_ERR_NUM_S) +#define EFUSE_RD_KEY5_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_KEY5_DATA_ERR_NUM_S 0 +/** EFUSE_RD_KEY5_DATA_FAIL : RO; bitpos: [3]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_key5_data is reliable\\ 1: Means that programming rd_key5_data failed and the + * number of error bytes is over 6. */ -#define EFUSE_KEY5_FAIL (BIT(3)) -#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) -#define EFUSE_KEY5_FAIL_V 0x00000001U -#define EFUSE_KEY5_FAIL_S 3 -/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. +#define EFUSE_RD_KEY5_DATA_FAIL (BIT(3)) +#define EFUSE_RD_KEY5_DATA_FAIL_M (EFUSE_RD_KEY5_DATA_FAIL_V << EFUSE_RD_KEY5_DATA_FAIL_S) +#define EFUSE_RD_KEY5_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_KEY5_DATA_FAIL_S 3 +/** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers.\\The value of this signal means the + * number of error bytes in rd_sys_part2_data */ -#define EFUSE_SYS_PART2_ERR_NUM 0x00000007U -#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) -#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U -#define EFUSE_SYS_PART2_ERR_NUM_S 4 -/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part2 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM 0x00000007U +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S) +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V 0x00000007U +#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S 4 +/** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [7]; default: 0; + * Represents error status of register.\\0: Means no failure and that the data of + * rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed + * and the number of error bytes is over 6. */ -#define EFUSE_SYS_PART2_FAIL (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) -#define EFUSE_SYS_PART2_FAIL_V 0x00000001U -#define EFUSE_SYS_PART2_FAIL_S 7 +#define EFUSE_RD_SYS_PART2_DATA_FAIL (BIT(7)) +#define EFUSE_RD_SYS_PART2_DATA_FAIL_M (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S) +#define EFUSE_RD_SYS_PART2_DATA_FAIL_V 0x00000001U +#define EFUSE_RD_SYS_PART2_DATA_FAIL_S 7 /** EFUSE_CLK_REG register * eFuse clcok configuration register. @@ -2754,13 +2700,6 @@ extern "C" { #define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) #define EFUSE_OP_CODE_V 0x0000FFFFU #define EFUSE_OP_CODE_S 0 -/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0; - * Configures which block to use for ECDSA key output. - */ -#define EFUSE_CFG_ECDSA_BLK 0x0000000FU -#define EFUSE_CFG_ECDSA_BLK_M (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S) -#define EFUSE_CFG_ECDSA_BLK_V 0x0000000FU -#define EFUSE_CFG_ECDSA_BLK_S 16 /** EFUSE_STATUS_REG register * eFuse status register. @@ -2822,13 +2761,6 @@ extern "C" { #define EFUSE_BLK0_VALID_BIT_CNT_M (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S) #define EFUSE_BLK0_VALID_BIT_CNT_V 0x000003FFU #define EFUSE_BLK0_VALID_BIT_CNT_S 10 -/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0; - * Indicates which block is used for ECDSA key output. - */ -#define EFUSE_CUR_ECDSA_BLK 0x0000000FU -#define EFUSE_CUR_ECDSA_BLK_M (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S) -#define EFUSE_CUR_ECDSA_BLK_V 0x0000000FU -#define EFUSE_CUR_ECDSA_BLK_S 20 /** EFUSE_CMD_REG register * eFuse command register. @@ -3082,7 +3014,7 @@ extern "C" { * eFuse version register. */ #define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) -/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 36720720; +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 38805904; * Stores eFuse version. */ #define EFUSE_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32p4/register/hw_ver3/soc/efuse_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/efuse_struct.h index b153ab070f7..090cf135438 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/efuse_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/efuse_struct.h @@ -10,162 +10,46 @@ extern "C" { #endif -// TODO: IDF-13421 - -/** Group: PGM Data Register */ -/** Type of pgm_data0 register - * Register 0 that stores data to be programmed. +/** Group: program_data registers */ +/** Type of pgm_datan register + * Represents pgm_datan */ typedef union { struct { - /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit data to be programmed. + /** pgm_data_n : R/W; bitpos: [31:0]; default: 0; + * Configures the nth 32-bit data to be programmed. */ - uint32_t pgm_data_0:32; + uint32_t pgm_data_n:32; }; uint32_t val; -} efuse_pgm_data0_reg_t; +} efuse_pgm_datan_reg_t; -/** Type of pgm_data1 register - * Register 1 that stores data to be programmed. +/** Type of pgm_check_valuen register + * Represents pgm_check_valuen */ typedef union { struct { - /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1st 32-bit data to be programmed. + /** pgm_rs_data_n : R/W; bitpos: [31:0]; default: 0; + * Configures the nth RS code to be programmed. */ - uint32_t pgm_data_1:32; + uint32_t pgm_rs_data_n:32; }; uint32_t val; -} efuse_pgm_data1_reg_t; - -/** Type of pgm_data2 register - * Register 2 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2nd 32-bit data to be programmed. - */ - uint32_t pgm_data_2:32; - }; - uint32_t val; -} efuse_pgm_data2_reg_t; - -/** Type of pgm_data3 register - * Register 3 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0; - * Configures the 3rd 32-bit data to be programmed. - */ - uint32_t pgm_data_3:32; - }; - uint32_t val; -} efuse_pgm_data3_reg_t; - -/** Type of pgm_data4 register - * Register 4 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0; - * Configures the 4th 32-bit data to be programmed. - */ - uint32_t pgm_data_4:32; - }; - uint32_t val; -} efuse_pgm_data4_reg_t; - -/** Type of pgm_data5 register - * Register 5 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0; - * Configures the 5th 32-bit data to be programmed. - */ - uint32_t pgm_data_5:32; - }; - uint32_t val; -} efuse_pgm_data5_reg_t; - -/** Type of pgm_data6 register - * Register 6 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0; - * Configures the 6th 32-bit data to be programmed. - */ - uint32_t pgm_data_6:32; - }; - uint32_t val; -} efuse_pgm_data6_reg_t; - -/** Type of pgm_data7 register - * Register 7 that stores data to be programmed. - */ -typedef union { - struct { - /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0; - * Configures the 7th 32-bit data to be programmed. - */ - uint32_t pgm_data_7:32; - }; - uint32_t val; -} efuse_pgm_data7_reg_t; - -/** Type of pgm_check_value0 register - * Register 0 that stores the RS code to be programmed. - */ -typedef union { - struct { - /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the 0th 32-bit RS code to be programmed. - */ - uint32_t pgm_rs_data_0:32; - }; - uint32_t val; -} efuse_pgm_check_value0_reg_t; - -/** Type of pgm_check_value1 register - * Register 1 that stores the RS code to be programmed. - */ -typedef union { - struct { - /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0; - * Configures the 1st 32-bit RS code to be programmed. - */ - uint32_t pgm_rs_data_1:32; - }; - uint32_t val; -} efuse_pgm_check_value1_reg_t; - -/** Type of pgm_check_value2 register - * Register 2 that stores the RS code to be programmed. - */ -typedef union { - struct { - /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0; - * Configures the 2nd 32-bit RS code to be programmed. - */ - uint32_t pgm_rs_data_2:32; - }; - uint32_t val; -} efuse_pgm_check_value2_reg_t; +} efuse_pgm_check_valuen_reg_t; -/** Group: ******** Registers */ +/** Group: block0 registers */ /** Type of rd_wr_dis register - * BLOCK0 data register 0. + * Represents rd_wr_dis */ typedef union { struct { /** wr_dis : RO; bitpos: [31:0]; default: 0; - * Represents whether programming of individual eFuse memory bit is disabled or - * enabled. 1: Disabled. 0 Enabled. + * Represents whether programming of individual eFuse memory bit is disabled. For + * mapping between the bits of this field and the eFuse memory bits, please refer to + * Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}. + * 1: Disabled + * 0: Enabled */ uint32_t wr_dis:32; }; @@ -173,39 +57,39 @@ typedef union { } efuse_rd_wr_dis_reg_t; /** Type of rd_repeat_data0 register - * BLOCK0 data register 1. + * Represents rd_repeat_data */ typedef union { struct { /** rd_dis : RO; bitpos: [6:0]; default: 0; * Represents whether reading of individual eFuse block(block4~block10) is disabled or - * enabled. 1: disabled. 0: enabled. + * enabled. + * 1: disabled + * 0: enabled */ uint32_t rd_dis:7; - /** usb_device_exchg_pins : RO; bitpos: [7]; default: 0; - * Enable usb device exchange pins of D+ and D-. + /** recovery_bootloader_flash_sector_0_1 : RO; bitpos: [8:7]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. */ - uint32_t usb_device_exchg_pins:1; - /** usb_otg11_exchg_pins : RO; bitpos: [8]; default: 0; - * Enable usb otg11 exchange pins of D+ and D-. - */ - uint32_t usb_otg11_exchg_pins:1; + uint32_t recovery_bootloader_flash_sector_0_1:2; /** dis_usb_jtag : RO; bitpos: [9]; default: 0; - * Represents whether the function of usb switch to jtag is disabled or enabled. 1: - * disabled. 0: enabled. + * Set this bit to disable function of usb switch to jtag in module of usb device. */ uint32_t dis_usb_jtag:1; - /** powerglitch_en : RO; bitpos: [10]; default: 0; - * Represents whether power glitch function is enabled. 1: enabled. 0: disabled. + /** recovery_bootloader_flash_sector_2_2 : RO; bitpos: [10]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. */ - uint32_t powerglitch_en:1; + uint32_t recovery_bootloader_flash_sector_2_2:1; /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; - * Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. + * Set this bit to disable USB-Serial-JTAG. */ uint32_t dis_usb_serial_jtag:1; /** dis_force_download : RO; bitpos: [12]; default: 0; - * Represents whether the function that forces chip into download mode is disabled or - * enabled. 1: disabled. 0: enabled. + * Set this bit to disable the function that forces chip into download mode. */ uint32_t dis_force_download:1; /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; @@ -214,119 +98,135 @@ typedef union { */ uint32_t spi_download_mspi_dis:1; /** dis_twai : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. + * Set this bit to disable TWAI function. */ uint32_t dis_twai:1; /** jtag_sel_enable : RO; bitpos: [15]; default: 0; - * Represents whether the selection between usb_to_jtag and pad_to_jtag through - * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 - * is enabled or disabled. 1: enabled. 0: disabled. + * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through + * strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0. */ uint32_t jtag_sel_enable:1; /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; - * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: - * enabled. + * Set odd bits to disable JTAG in the soft way. JTAG can be enabled in HMAC module. */ uint32_t soft_dis_jtag:3; /** dis_pad_jtag : RO; bitpos: [19]; default: 0; - * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: - * enabled. + * Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. */ uint32_t dis_pad_jtag:1; /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; - * Represents whether flash encrypt function is disabled or enabled(except in SPI boot - * mode). 1: disabled. 0: enabled. + * Set this bit to disable flash manual encrypt function (except in SPI boot mode). */ uint32_t dis_download_manual_encrypt:1; - /** usb_device_drefh : RO; bitpos: [22:21]; default: 0; - * USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV + /** recovery_bootloader_flash_sector_3_6 : RO; bitpos: [24:21]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. */ - uint32_t usb_device_drefh:2; - /** usb_otg11_drefh : RO; bitpos: [24:23]; default: 0; - * USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV - */ - uint32_t usb_otg11_drefh:2; + uint32_t recovery_bootloader_flash_sector_3_6:4; /** usb_phy_sel : RO; bitpos: [25]; default: 0; - * TBD + * 0: intphy(gpio24/25) <---> usb_device + * 1: intphy(26/27) <---> usb_otg11.1: intphy(gpio26/27) <---> usb_device + * 1: intphy(24/25) <---> usb_otg11. */ uint32_t usb_phy_sel:1; - /** km_huk_gen_state_low : RO; bitpos: [31:26]; default: 0; - * Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even + /** huk_gen_state : RO; bitpos: [30:26]; default: 0; + * Set the bits to control validation of HUK generate mode. Odd of 1 is invalid, even * of 1 is valid. */ - uint32_t km_huk_gen_state_low:6; + uint32_t huk_gen_state:5; + /** recovery_bootloader_flash_sector_7_7 : RO; bitpos: [31]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. + */ + uint32_t recovery_bootloader_flash_sector_7_7:1; }; uint32_t val; } efuse_rd_repeat_data0_reg_t; /** Type of rd_repeat_data1 register - * BLOCK0 data register 2. + * Represents rd_repeat_data */ typedef union { struct { - /** km_huk_gen_state_high : RO; bitpos: [2:0]; default: 0; - * Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even - * of 1 is valid. + /** recovery_bootloader_flash_sector_8_10 : RO; bitpos: [2:0]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. */ - uint32_t km_huk_gen_state_high:3; - /** km_rnd_switch_cycle : RO; bitpos: [4:3]; default: 0; - * Set bits to control key manager random number switch cycle. 0: control by register. - * 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles. + uint32_t recovery_bootloader_flash_sector_8_10:3; + /** recovery_bootloader_flash_sector_11_11 : RO; bitpos: [3]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. */ - uint32_t km_rnd_switch_cycle:2; + uint32_t recovery_bootloader_flash_sector_11_11:1; + /** km_rnd_switch_cycle : RO; bitpos: [4]; default: 0; + * Set the bits to control key manager random number switch cycle. 0: control by + * register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles + */ + uint32_t km_rnd_switch_cycle:1; /** km_deploy_only_once : RO; bitpos: [8:5]; default: 0; - * Set each bit to control whether corresponding key can only be deployed once. 1 is - * true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. + * EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: + * {EFUSE_KM_DEPLOY_ONLY_ONCE_H, EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to + * control whether corresponding key can only be deployed once. 1 is true, 0 is false. + * bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, bit4:psram */ uint32_t km_deploy_only_once:4; /** force_use_key_manager_key : RO; bitpos: [12:9]; default: 0; - * Set each bit to control whether corresponding key must come from key manager.. 1 is - * true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds. + * EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form + * one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H, + * EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether + * corresponding key must come from key manager. 1 is true, 0 is false. bit 0: ecsda, + * bit 1: xts, bit2: hmac, bit3: ds, bit4:psram */ uint32_t force_use_key_manager_key:4; /** force_disable_sw_init_key : RO; bitpos: [13]; default: 0; * Set this bit to disable software written init key, and force use efuse_init_key. */ uint32_t force_disable_sw_init_key:1; - /** xts_key_length_256 : RO; bitpos: [14]; default: 0; - * Set this bit to configure flash encryption use xts-128 key, else use xts-256 key. + /** km_xts_key_length_256 : RO; bitpos: [14]; default: 0; + * Set this bit to config flash encryption xts-512 key, else use xts-256 key when + * using the key manager */ - uint32_t xts_key_length_256:1; - /** rd_reserve_0_79 : RW; bitpos: [15]; default: 0; + uint32_t km_xts_key_length_256:1; + /** ecc_force_const_time : RO; bitpos: [15]; default: 0; + * Set this bit to permanently turn on ECC const-time mode. + */ + uint32_t ecc_force_const_time:1; + /** rd_reserve_0_80 : RW; bitpos: [16]; default: 0; * Reserved, it was created by set_missed_fields_in_regs func */ - uint32_t rd_reserve_0_79:1; - /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; - * Represents whether RTC watchdog timeout threshold is selected at startup. 1: - * selected. 0: not selected. + uint32_t rd_reserve_0_80:1; + /** wdt_delay_sel : RO; bitpos: [17]; default: 0; + * Select lp wdt timeout threshold at startup = initial timeout value * (2 ^ + * (EFUSE_WDT_DELAY_SEL + 1)) */ - uint32_t wdt_delay_sel:2; + uint32_t wdt_delay_sel:1; /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; - * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of - * 1: enabled. Even number of 1: disabled. + * Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even + * number of 1: disable. */ uint32_t spi_boot_crypt_cnt:3; /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; - * Represents whether revoking first secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. + * Set this bit to enable revoking first secure boot key. */ uint32_t secure_boot_key_revoke0:1; /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; - * Represents whether revoking second secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. + * Set this bit to enable revoking second secure boot key. */ uint32_t secure_boot_key_revoke1:1; /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; - * Represents whether revoking third secure boot key is enabled or disabled. 1: - * enabled. 0: disabled. + * Set this bit to enable revoking third secure boot key. */ uint32_t secure_boot_key_revoke2:1; /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; - * Represents the purpose of Key0. + * Purpose of Key0. */ uint32_t key_purpose_0:4; /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; - * Represents the purpose of Key1. + * Purpose of Key1. */ uint32_t key_purpose_1:4; }; @@ -334,62 +234,67 @@ typedef union { } efuse_rd_repeat_data1_reg_t; /** Type of rd_repeat_data2 register - * BLOCK0 data register 3. + * Represents rd_repeat_data */ typedef union { struct { /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; - * Represents the purpose of Key2. + * Purpose of Key2. */ uint32_t key_purpose_2:4; /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; - * Represents the purpose of Key3. + * Purpose of Key3. */ uint32_t key_purpose_3:4; /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; - * Represents the purpose of Key4. + * Purpose of Key4. */ uint32_t key_purpose_4:4; /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; - * Represents the purpose of Key5. + * Purpose of Key5. */ uint32_t key_purpose_5:4; /** sec_dpa_level : RO; bitpos: [17:16]; default: 0; - * Represents the spa secure level by configuring the clock random divide mode. + * Configures the clock random divide mode to determine the dpa secure level */ uint32_t sec_dpa_level:2; - /** ecdsa_enable_soft_k : RO; bitpos: [18]; default: 0; - * Represents whether hardware random number k is forced used in ESDCA. 1: force used. - * 0: not force used. + /** rd_reserve_0_114 : RW; bitpos: [18]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func */ - uint32_t ecdsa_enable_soft_k:1; - /** crypt_dpa_enable : RO; bitpos: [19]; default: 1; - * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. + uint32_t rd_reserve_0_114:1; + /** xts_dpa_clk_enable : RO; bitpos: [19]; default: 0; + * Sets this bit to enable xts clock anti-dpa attack function. */ - uint32_t crypt_dpa_enable:1; + uint32_t xts_dpa_clk_enable:1; /** secure_boot_en : RO; bitpos: [20]; default: 0; - * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. + * Set this bit to enable secure boot. */ uint32_t secure_boot_en:1; /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; - * Represents whether revoking aggressive secure boot is enabled or disabled. 1: - * enabled. 0: disabled. + * Set this bit to enable revoking aggressive secure boot. */ uint32_t secure_boot_aggressive_revoke:1; - /** rd_reserve_0_118 : RW; bitpos: [22]; default: 0; + /** km_deploy_only_once_h : RO; bitpos: [22]; default: 0; + * EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field: + * {EFUSE_KM_DEPLOY_ONLY_ONCE_H, EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to + * control whether corresponding key can only be deployed once. 1 is true, 0 is false. + * bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, bit4:psram + */ + uint32_t km_deploy_only_once_h:1; + /** force_use_key_manager_key_h : RO; bitpos: [23]; default: 0; + * EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form + * one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H, + * EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether + * corresponding key must come from key manager. 1 is true, 0 is false. bit 0: ecsda, + * bit 1: xts, bit2: hmac, bit3: ds, bit4:psram + */ + uint32_t force_use_key_manager_key_h:1; + /** rd_reserve_0_120 : RW; bitpos: [25:24]; default: 0; * Reserved, it was created by set_missed_fields_in_regs func */ - uint32_t rd_reserve_0_118:1; - /** flash_type : RO; bitpos: [23]; default: 0; - * The type of interfaced flash. 0: four data lines, 1: eight data lines. - */ - uint32_t flash_type:1; - /** flash_page_size : RO; bitpos: [25:24]; default: 0; - * Set flash page size. - */ - uint32_t flash_page_size:2; + uint32_t rd_reserve_0_120:2; /** flash_ecc_en : RO; bitpos: [26]; default: 0; - * Set this bit to enable ecc for flash boot. + * Set this bit to enable ECC for flash boot. */ uint32_t flash_ecc_en:1; /** dis_usb_otg_download_mode : RO; bitpos: [27]; default: 0; @@ -397,9 +302,9 @@ typedef union { */ uint32_t dis_usb_otg_download_mode:1; /** flash_tpuw : RO; bitpos: [31:28]; default: 0; - * Represents the flash waiting time after power-up, in unit of ms. When the value - * less than 15, the waiting time is the programmed value. Otherwise, the waiting time - * is 2 times the programmed value. + * Configures flash waiting time after power-up, in unit of ms. When the value less + * than 15, the waiting time is the configurable value. Otherwise, the waiting time is + * 30. */ uint32_t flash_tpuw:4; }; @@ -407,165 +312,196 @@ typedef union { } efuse_rd_repeat_data2_reg_t; /** Type of rd_repeat_data3 register - * BLOCK0 data register 4. + * Represents rd_repeat_data */ typedef union { struct { /** dis_download_mode : RO; bitpos: [0]; default: 0; - * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. + * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7). */ uint32_t dis_download_mode:1; /** dis_direct_boot : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. + * Set this bit to disable direct boot mode */ uint32_t dis_direct_boot:1; /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. - * 0: enabled. + * Set this bit to disable USB-Serial-JTAG print during rom boot. */ uint32_t dis_usb_serial_jtag_rom_print:1; /** lock_km_key : RO; bitpos: [3]; default: 0; - * TBD + * set this bit to lock the key manager key after deploy */ uint32_t lock_km_key:1; /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: - * disabled. 0: enabled. + * Set this bit to disable the USB-Serial-JTAG download function. */ uint32_t dis_usb_serial_jtag_download_mode:1; /** enable_security_download : RO; bitpos: [5]; default: 0; - * Represents whether security download is enabled or disabled. 1: enabled. 0: - * disabled. + * Set this bit to enable security download mode. */ uint32_t enable_security_download:1; /** uart_print_control : RO; bitpos: [7:6]; default: 0; - * Represents the type of UART printing. 00: force enable printing. 01: enable - * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset - * at high level. 11: force disable printing. + * Set the type of UART printing, 00: force enable printing, 01: enable printing when + * GPIO8 is reset at low level, 10: enable printing when GPIO8 is reset at high level, + * 11: force disable printing */ uint32_t uart_print_control:2; /** force_send_resume : RO; bitpos: [8]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot. 1: - * forced. 0:not forced. + * Set this bit to force ROM code to send a resume command during SPI boot. */ uint32_t force_send_resume:1; /** secure_version : RO; bitpos: [24:9]; default: 0; - * Represents the version used by ESP-IDF anti-rollback feature. + * Secure version used by ESP-IDF anti-rollback feature. */ uint32_t secure_version:16; /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0; - * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is - * enabled. 1: disabled. 0: enabled. + * Represents whether secure boot do fast verification on wake is disabled. 0: enabled + * 1: disabled */ uint32_t secure_boot_disable_fast_wake:1; /** hys_en_pad : RO; bitpos: [26]; default: 0; - * Represents whether the hysteresis function of corresponding PAD is enabled. 1: - * enabled. 0:disabled. + * Set bits to enable hysteresis function of PAD0~27 */ uint32_t hys_en_pad:1; - /** dcdc_vset : RO; bitpos: [31:27]; default: 0; - * Set the dcdc voltage default. + /** key_purpose_0_h : RO; bitpos: [27]; default: 0; + * Purpose of Key0. The 5-th bit. */ - uint32_t dcdc_vset:5; + uint32_t key_purpose_0_h:1; + /** key_purpose_1_h : RO; bitpos: [28]; default: 0; + * Purpose of Key1. The 5-th bit. + */ + uint32_t key_purpose_1_h:1; + /** key_purpose_2_h : RO; bitpos: [29]; default: 0; + * Purpose of Key2. The 5-th bit. + */ + uint32_t key_purpose_2_h:1; + /** key_purpose_3_h : RO; bitpos: [30]; default: 0; + * Purpose of Key3. The 5-th bit. + */ + uint32_t key_purpose_3_h:1; + /** key_purpose_4_h : RO; bitpos: [31]; default: 0; + * Purpose of Key4. The 5-th bit. + */ + uint32_t key_purpose_4_h:1; }; uint32_t val; } efuse_rd_repeat_data3_reg_t; /** Type of rd_repeat_data4 register - * BLOCK0 data register 5. + * Represents rd_repeat_data */ typedef union { struct { /** pxa0_tieh_sel_0 : RO; bitpos: [1:0]; default: 0; - * TBD + * Output LDO VO0 tieh source select. 0: 1'b1 1: sdmmc1 2: reg 3:sdmmc0 */ uint32_t pxa0_tieh_sel_0:2; - /** pxa0_tieh_sel_1 : RO; bitpos: [3:2]; default: 0; - * TBD. + /** pvt_glitch_en : RO; bitpos: [2]; default: 0; + * Represents whether to enable PVT power glitch monitor function. + * 1:Enable. + * 0:Disable */ - uint32_t pxa0_tieh_sel_1:2; - /** pxa0_tieh_sel_2 : RO; bitpos: [5:4]; default: 0; - * TBD. - */ - uint32_t pxa0_tieh_sel_2:2; - /** pxa0_tieh_sel_3 : RO; bitpos: [7:6]; default: 0; - * TBD. - */ - uint32_t pxa0_tieh_sel_3:2; - /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0; - * TBD. - */ - uint32_t km_disable_deploy_mode:4; - /** usb_device_drefl : RO; bitpos: [13:12]; default: 0; - * Represents the usb device single-end input low threshold, 0.8 V to 1.04 V with step - * of 80 mV. - */ - uint32_t usb_device_drefl:2; - /** usb_otg11_drefl : RO; bitpos: [15:14]; default: 0; - * Represents the usb otg11 single-end input low threshold, 0.8 V to 1.04 V with step - * of 80 mV. - */ - uint32_t usb_otg11_drefl:2; - /** rd_reserve_0_176 : RW; bitpos: [17:16]; default: 0; + uint32_t pvt_glitch_en:1; + /** rd_reserve_0_163 : RW; bitpos: [3]; default: 0; * Reserved, it was created by set_missed_fields_in_regs func */ - uint32_t rd_reserve_0_176:2; + uint32_t rd_reserve_0_163:1; + /** key_purpose_5_h : RO; bitpos: [4]; default: 0; + * Purpose of Key5. The 5-th bit. + */ + uint32_t key_purpose_5_h:1; + /** rd_reserve_0_165 : RW; bitpos: [6:5]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_165:2; + /** km_disable_deploy_mode_h : RO; bitpos: [7]; default: 0; + * EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one + * field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H, EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set + * each bit to control whether corresponding key's deploy mode of new value deployment + * is disabled. 1 is true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, + * bit4:psram + */ + uint32_t km_disable_deploy_mode_h:1; + /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0; + * EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one + * field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H, EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set + * each bit to control whether corresponding key's deploy mode of new value deployment + * is disabled. 1 is true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, + * bit4:psram + */ + uint32_t km_disable_deploy_mode:4; + /** rd_reserve_0_172 : RW; bitpos: [15:12]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_172:4; + /** xts_dpa_pseudo_level : RO; bitpos: [17:16]; default: 0; + * Sets this bit to control the xts pseudo-round anti-dpa attack function. 0: + * controlled by register. 1-3: the higher the value is, the more pseudo-rounds are + * inserted to the xts-aes calculation + */ + uint32_t xts_dpa_pseudo_level:2; /** hp_pwr_src_sel : RO; bitpos: [18]; default: 0; - * HP system power source select. 0:LDO. 1: DCDC. + * HP system power source select. 0:LDO 1: DCDC */ uint32_t hp_pwr_src_sel:1; - /** dcdc_vset_en : RO; bitpos: [19]; default: 0; - * Select dcdc vset use efuse_dcdc_vset. + /** secure_boot_sha384_en : RO; bitpos: [19]; default: 0; + * Represents whether secure boot using SHA-384 is enabled. 0: disable 1: enable */ - uint32_t dcdc_vset_en:1; + uint32_t secure_boot_sha384_en:1; /** dis_wdt : RO; bitpos: [20]; default: 0; * Set this bit to disable watch dog. */ uint32_t dis_wdt:1; /** dis_swd : RO; bitpos: [21]; default: 0; - * Set this bit to disable super-watchdog. + * Set bit to disable super-watchdog */ uint32_t dis_swd:1; - /** rd_reserve_0_182 : RW; bitpos: [31:22]; default: 0; + /** pvt_glitch_mode : RO; bitpos: [23:22]; default: 0; + * Use to configure glitch mode + */ + uint32_t pvt_glitch_mode:2; + /** rd_reserve_0_184 : RW; bitpos: [31:24]; default: 0; * Reserved, it was created by set_missed_fields_in_regs func */ - uint32_t rd_reserve_0_182:10; + uint32_t rd_reserve_0_184:8; }; uint32_t val; } efuse_rd_repeat_data4_reg_t; -/** Type of rd_mac_sys_0 register - * BLOCK1 data register $n. + +/** Group: block1 registers */ +/** Type of rd_mac_sys0 register + * Represents rd_mac_sys */ typedef union { struct { /** mac_0 : RO; bitpos: [31:0]; default: 0; - * Stores the low 32 bits of MAC address. + * Represents MAC address. Low 32-bit. */ uint32_t mac_0:32; }; uint32_t val; -} efuse_rd_mac_sys_0_reg_t; +} efuse_rd_mac_sys0_reg_t; -/** Type of rd_mac_sys_1 register - * BLOCK1 data register $n. +/** Type of rd_mac_sys1 register + * Represents rd_mac_sys */ typedef union { struct { /** mac_1 : RO; bitpos: [15:0]; default: 0; - * Stores the high 16 bits of MAC address. + * Represents MAC address. High 16-bit. */ uint32_t mac_1:16; - /** reserved_1_16 : RO; bitpos: [31:16]; default: 0; - * Stores the extended bits of MAC address. + /** rd_reserve_1_48 : RW; bitpos: [31:16]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func */ - uint32_t reserved_1_16:16; + uint32_t rd_reserve_1_48:16; }; uint32_t val; -} efuse_rd_mac_sys_1_reg_t; +} efuse_rd_mac_sys1_reg_t; -/** Type of rd_mac_sys_2 register - * BLOCK1 data register $n. +/** Type of rd_mac_sys2 register + * Represents rd_mac_sys */ typedef union { struct { @@ -613,115 +549,61 @@ typedef union { * Major chip version (MSB) */ uint32_t wafer_version_major_hi:1; - /** ldo_vo1_dref : R; bitpos: [27:24]; default: 0; - * Output VO1 parameter - */ - uint32_t ldo_vo1_dref:4; - /** ldo_vo2_dref : R; bitpos: [31:28]; default: 0; - * Output VO2 parameter - */ - uint32_t ldo_vo2_dref:4; - }; - uint32_t val; -} efuse_rd_mac_sys_2_reg_t; - -/** Type of rd_mac_sys_3 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** ldo_vo1_mul : R; bitpos: [2:0]; default: 0; - * Output VO1 parameter - */ - uint32_t ldo_vo1_mul:3; - /** ldo_vo2_mul : R; bitpos: [5:3]; default: 0; - * Output VO2 parameter - */ - uint32_t ldo_vo2_mul:3; - /** ldo_vo3_k : R; bitpos: [13:6]; default: 0; - * Output VO3 calibration parameter - */ - uint32_t ldo_vo3_k:8; - /** ldo_vo3_vos : R; bitpos: [19:14]; default: 0; - * Output VO3 calibration parameter - */ - uint32_t ldo_vo3_vos:6; - /** ldo_vo3_c : R; bitpos: [25:20]; default: 0; - * Output VO3 calibration parameter - */ - uint32_t ldo_vo3_c:6; - /** ldo_vo4_k : R; bitpos: [31:26]; default: 0; - * Output VO4 calibration parameter - */ - uint32_t ldo_vo4_k:6; - }; - uint32_t val; -} efuse_rd_mac_sys_3_reg_t; - -/** Type of rd_mac_sys_4 register - * BLOCK1 data register $n. - */ -typedef union { - struct { - /** ldo_vo4_k_1 : R; bitpos: [1:0]; default: 0; - * Output VO4 calibration parameter - */ - uint32_t ldo_vo4_k_1:2; - /** ldo_vo4_vos : R; bitpos: [7:2]; default: 0; - * Output VO4 calibration parameter - */ - uint32_t ldo_vo4_vos:6; - /** ldo_vo4_c : R; bitpos: [13:8]; default: 0; - * Output VO4 calibration parameter - */ - uint32_t ldo_vo4_c:6; - /** reserved_1_142 : R; bitpos: [15:14]; default: 0; + /** reserved_1_88 : R; bitpos: [31:24]; default: 0; * reserved */ - uint32_t reserved_1_142:2; - /** active_hp_dbias : R; bitpos: [19:16]; default: 0; - * Active HP DBIAS of fixed voltage - */ - uint32_t active_hp_dbias:4; - /** active_lp_dbias : R; bitpos: [23:20]; default: 0; - * Active LP DBIAS of fixed voltage - */ - uint32_t active_lp_dbias:4; - /** lslp_hp_dbias : R; bitpos: [27:24]; default: 0; - * LSLP HP DBIAS of fixed voltage - */ - uint32_t lslp_hp_dbias:4; - /** dslp_dbg : R; bitpos: [31:28]; default: 0; - * DSLP BDG of fixed voltage - */ - uint32_t dslp_dbg:4; + uint32_t reserved_1_88:8; }; uint32_t val; -} efuse_rd_mac_sys_4_reg_t; +} efuse_rd_mac_sys2_reg_t; -/** Type of rd_mac_sys_5 register - * BLOCK1 data register $n. +/** Type of rd_mac_sys3 register + * Represents rd_mac_sys */ typedef union { struct { - /** dslp_lp_dbias : R; bitpos: [4:0]; default: 0; - * DSLP LP DBIAS of fixed voltage + /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; + * Reserved. */ - uint32_t dslp_lp_dbias:5; - /** lp_dcdc_dbias_vol_gap : R; bitpos: [9:5]; default: 0; - * DBIAS gap between LP and DCDC + uint32_t mac_reserved_2:18; + /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; + * Represents the first 14-bit of zeroth part of system data. */ - uint32_t lp_dcdc_dbias_vol_gap:5; - /** reserved_1_170 : R; bitpos: [31:10]; default: 0; - * reserved - */ - uint32_t reserved_1_170:22; + uint32_t sys_data_part0_0:14; }; uint32_t val; -} efuse_rd_mac_sys_5_reg_t; +} efuse_rd_mac_sys3_reg_t; +/** Type of rd_mac_sys4 register + * Represents rd_mac_sys + */ +typedef union { + struct { + /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0; + * Represents the second 32-bit of zeroth part of system data. + */ + uint32_t sys_data_part0_1:32; + }; + uint32_t val; +} efuse_rd_mac_sys4_reg_t; + +/** Type of rd_mac_sys5 register + * Represents rd_mac_sys + */ +typedef union { + struct { + /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; + * Represents the third 32-bit of zeroth part of system data. + */ + uint32_t sys_data_part0_2:32; + }; + uint32_t val; +} efuse_rd_mac_sys5_reg_t; + + +/** Group: block2 registers */ /** Type of rd_sys_part1_data0 register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data0 */ typedef union { struct { @@ -734,7 +616,7 @@ typedef union { } efuse_rd_sys_part1_data0_reg_t; /** Type of rd_sys_part1_data1 register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data1 */ typedef union { struct { @@ -747,7 +629,7 @@ typedef union { } efuse_rd_sys_part1_data1_reg_t; /** Type of rd_sys_part1_data2 register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data2 */ typedef union { struct { @@ -760,7 +642,7 @@ typedef union { } efuse_rd_sys_part1_data2_reg_t; /** Type of rd_sys_part1_data3 register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data3 */ typedef union { struct { @@ -773,112 +655,66 @@ typedef union { } efuse_rd_sys_part1_data3_reg_t; /** Type of rd_sys_part1_data4 register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data4 */ typedef union { struct { - /** adc1_ave_initcode_atten0 : R; bitpos: [9:0]; default: 0; - * Average initcode of ADC1 atten0 + /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ - uint32_t adc1_ave_initcode_atten0:10; - /** adc1_ave_initcode_atten1 : R; bitpos: [19:10]; default: 0; - * Average initcode of ADC1 atten1 - */ - uint32_t adc1_ave_initcode_atten1:10; - /** adc1_ave_initcode_atten2 : R; bitpos: [29:20]; default: 0; - * Average initcode of ADC1 atten2 - */ - uint32_t adc1_ave_initcode_atten2:10; - /** adc1_ave_initcode_atten3 : R; bitpos: [31:30]; default: 0; - * Average initcode of ADC1 atten3 - */ - uint32_t adc1_ave_initcode_atten3:2; + uint32_t sys_data_part1_4:32; }; uint32_t val; } efuse_rd_sys_part1_data4_reg_t; /** Type of rd_sys_part1_data5 register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data5 */ typedef union { struct { - /** adc1_ave_initcode_atten3_1 : R; bitpos: [7:0]; default: 0; - * Average initcode of ADC1 atten3 + /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ - uint32_t adc1_ave_initcode_atten3_1:8; - /** adc2_ave_initcode_atten0 : R; bitpos: [17:8]; default: 0; - * Average initcode of ADC2 atten0 - */ - uint32_t adc2_ave_initcode_atten0:10; - /** adc2_ave_initcode_atten1 : R; bitpos: [27:18]; default: 0; - * Average initcode of ADC2 atten1 - */ - uint32_t adc2_ave_initcode_atten1:10; - /** adc2_ave_initcode_atten2 : R; bitpos: [31:28]; default: 0; - * Average initcode of ADC2 atten2 - */ - uint32_t adc2_ave_initcode_atten2:4; + uint32_t sys_data_part1_5:32; }; uint32_t val; } efuse_rd_sys_part1_data5_reg_t; /** Type of rd_sys_part1_data6 register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data6 */ typedef union { struct { - /** adc2_ave_initcode_atten2_1 : R; bitpos: [5:0]; default: 0; - * Average initcode of ADC2 atten2 + /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ - uint32_t adc2_ave_initcode_atten2_1:6; - /** adc2_ave_initcode_atten3 : R; bitpos: [15:6]; default: 0; - * Average initcode of ADC2 atten3 - */ - uint32_t adc2_ave_initcode_atten3:10; - /** adc1_hi_dout_atten0 : R; bitpos: [25:16]; default: 0; - * HI_DOUT of ADC1 atten0 - */ - uint32_t adc1_hi_dout_atten0:10; - /** adc1_hi_dout_atten1 : R; bitpos: [31:26]; default: 0; - * HI_DOUT of ADC1 atten1 - */ - uint32_t adc1_hi_dout_atten1:6; + uint32_t sys_data_part1_6:32; }; uint32_t val; } efuse_rd_sys_part1_data6_reg_t; /** Type of rd_sys_part1_data7 register - * Register $n of BLOCK2 (system). + * Represents rd_sys_part1_data7 */ typedef union { struct { - /** adc1_hi_dout_atten1_1 : R; bitpos: [3:0]; default: 0; - * HI_DOUT of ADC1 atten1 + /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of first part of system data. */ - uint32_t adc1_hi_dout_atten1_1:4; - /** adc1_hi_dout_atten2 : R; bitpos: [13:4]; default: 0; - * HI_DOUT of ADC1 atten2 - */ - uint32_t adc1_hi_dout_atten2:10; - /** adc1_hi_dout_atten3 : R; bitpos: [23:14]; default: 0; - * HI_DOUT of ADC1 atten3 - */ - uint32_t adc1_hi_dout_atten3:10; - /** reserved_2_248 : R; bitpos: [31:24]; default: 0; - * reserved - */ - uint32_t reserved_2_248:8; + uint32_t sys_data_part1_7:32; }; uint32_t val; } efuse_rd_sys_part1_data7_reg_t; + +/** Group: block3 registers */ /** Type of rd_usr_data0 register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data0 */ typedef union { struct { /** usr_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ uint32_t usr_data0:32; }; @@ -886,12 +722,12 @@ typedef union { } efuse_rd_usr_data0_reg_t; /** Type of rd_usr_data1 register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data1 */ typedef union { struct { /** usr_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ uint32_t usr_data1:32; }; @@ -899,12 +735,12 @@ typedef union { } efuse_rd_usr_data1_reg_t; /** Type of rd_usr_data2 register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data2 */ typedef union { struct { /** usr_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ uint32_t usr_data2:32; }; @@ -912,12 +748,12 @@ typedef union { } efuse_rd_usr_data2_reg_t; /** Type of rd_usr_data3 register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data3 */ typedef union { struct { /** usr_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ uint32_t usr_data3:32; }; @@ -925,12 +761,12 @@ typedef union { } efuse_rd_usr_data3_reg_t; /** Type of rd_usr_data4 register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data4 */ typedef union { struct { /** usr_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ uint32_t usr_data4:32; }; @@ -938,12 +774,12 @@ typedef union { } efuse_rd_usr_data4_reg_t; /** Type of rd_usr_data5 register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data5 */ typedef union { struct { /** usr_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of BLOCK3 (user). + * Represents the zeroth 32-bit of block3 (user). */ uint32_t usr_data5:32; }; @@ -951,7 +787,7 @@ typedef union { } efuse_rd_usr_data5_reg_t; /** Type of rd_usr_data6 register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data6 */ typedef union { struct { @@ -968,7 +804,7 @@ typedef union { } efuse_rd_usr_data6_reg_t; /** Type of rd_usr_data7 register - * Register $n of BLOCK3 (user). + * Represents rd_usr_data7 */ typedef union { struct { @@ -984,757 +820,157 @@ typedef union { uint32_t val; } efuse_rd_usr_data7_reg_t; -/** Type of rd_key0_data0 register - * Register $n of BLOCK4 (KEY0). + +/** Group: block4 registers */ +/** Type of rd_key0_datan register + * Represents rd_key0_datan */ typedef union { struct { - /** key0_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY0. + /** key0_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key0. */ - uint32_t key0_data0:32; + uint32_t key0_datan:32; }; uint32_t val; -} efuse_rd_key0_data0_reg_t; +} efuse_rd_key0_datan_reg_t; -/** Type of rd_key0_data1 register - * Register $n of BLOCK4 (KEY0). + +/** Group: block5 registers */ +/** Type of rd_key1_datan register + * Represents rd_key1_datan */ typedef union { struct { - /** key0_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY0. + /** key1_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key1. */ - uint32_t key0_data1:32; + uint32_t key1_datan:32; }; uint32_t val; -} efuse_rd_key0_data1_reg_t; +} efuse_rd_key1_datan_reg_t; -/** Type of rd_key0_data2 register - * Register $n of BLOCK4 (KEY0). + +/** Group: block6 registers */ +/** Type of rd_key2_datan register + * Represents rd_key2_datan */ typedef union { struct { - /** key0_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY0. + /** key2_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key2. */ - uint32_t key0_data2:32; + uint32_t key2_datan:32; }; uint32_t val; -} efuse_rd_key0_data2_reg_t; +} efuse_rd_key2_datan_reg_t; -/** Type of rd_key0_data3 register - * Register $n of BLOCK4 (KEY0). + +/** Group: block7 registers */ +/** Type of rd_key3_datan register + * Represents rd_key3_datan */ typedef union { struct { - /** key0_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY0. + /** key3_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key3. */ - uint32_t key0_data3:32; + uint32_t key3_datan:32; }; uint32_t val; -} efuse_rd_key0_data3_reg_t; +} efuse_rd_key3_datan_reg_t; -/** Type of rd_key0_data4 register - * Register $n of BLOCK4 (KEY0). + +/** Group: block8 registers */ +/** Type of rd_key4_datan register + * Represents rd_key4_datan */ typedef union { struct { - /** key0_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY0. + /** key4_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key4. */ - uint32_t key0_data4:32; + uint32_t key4_datan:32; }; uint32_t val; -} efuse_rd_key0_data4_reg_t; +} efuse_rd_key4_datan_reg_t; -/** Type of rd_key0_data5 register - * Register $n of BLOCK4 (KEY0). + +/** Group: block9 registers */ +/** Type of rd_key5_datan register + * Represents rd_key5_datan */ typedef union { struct { - /** key0_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY0. + /** key5_datan : RO; bitpos: [31:0]; default: 0; + * Represents the zeroth 32-bit of key5. */ - uint32_t key0_data5:32; + uint32_t key5_datan:32; }; uint32_t val; -} efuse_rd_key0_data5_reg_t; +} efuse_rd_key5_datan_reg_t; -/** Type of rd_key0_data6 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY0. - */ - uint32_t key0_data6:32; - }; - uint32_t val; -} efuse_rd_key0_data6_reg_t; - -/** Type of rd_key0_data7 register - * Register $n of BLOCK4 (KEY0). - */ -typedef union { - struct { - /** key0_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY0. - */ - uint32_t key0_data7:32; - }; - uint32_t val; -} efuse_rd_key0_data7_reg_t; - -/** Type of rd_key1_data0 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY1. - */ - uint32_t key1_data0:32; - }; - uint32_t val; -} efuse_rd_key1_data0_reg_t; - -/** Type of rd_key1_data1 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY1. - */ - uint32_t key1_data1:32; - }; - uint32_t val; -} efuse_rd_key1_data1_reg_t; - -/** Type of rd_key1_data2 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY1. - */ - uint32_t key1_data2:32; - }; - uint32_t val; -} efuse_rd_key1_data2_reg_t; - -/** Type of rd_key1_data3 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY1. - */ - uint32_t key1_data3:32; - }; - uint32_t val; -} efuse_rd_key1_data3_reg_t; - -/** Type of rd_key1_data4 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY1. - */ - uint32_t key1_data4:32; - }; - uint32_t val; -} efuse_rd_key1_data4_reg_t; - -/** Type of rd_key1_data5 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY1. - */ - uint32_t key1_data5:32; - }; - uint32_t val; -} efuse_rd_key1_data5_reg_t; - -/** Type of rd_key1_data6 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY1. - */ - uint32_t key1_data6:32; - }; - uint32_t val; -} efuse_rd_key1_data6_reg_t; - -/** Type of rd_key1_data7 register - * Register $n of BLOCK5 (KEY1). - */ -typedef union { - struct { - /** key1_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY1. - */ - uint32_t key1_data7:32; - }; - uint32_t val; -} efuse_rd_key1_data7_reg_t; - -/** Type of rd_key2_data0 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY2. - */ - uint32_t key2_data0:32; - }; - uint32_t val; -} efuse_rd_key2_data0_reg_t; - -/** Type of rd_key2_data1 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY2. - */ - uint32_t key2_data1:32; - }; - uint32_t val; -} efuse_rd_key2_data1_reg_t; - -/** Type of rd_key2_data2 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY2. - */ - uint32_t key2_data2:32; - }; - uint32_t val; -} efuse_rd_key2_data2_reg_t; - -/** Type of rd_key2_data3 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY2. - */ - uint32_t key2_data3:32; - }; - uint32_t val; -} efuse_rd_key2_data3_reg_t; - -/** Type of rd_key2_data4 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY2. - */ - uint32_t key2_data4:32; - }; - uint32_t val; -} efuse_rd_key2_data4_reg_t; - -/** Type of rd_key2_data5 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY2. - */ - uint32_t key2_data5:32; - }; - uint32_t val; -} efuse_rd_key2_data5_reg_t; - -/** Type of rd_key2_data6 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY2. - */ - uint32_t key2_data6:32; - }; - uint32_t val; -} efuse_rd_key2_data6_reg_t; - -/** Type of rd_key2_data7 register - * Register $n of BLOCK6 (KEY2). - */ -typedef union { - struct { - /** key2_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY2. - */ - uint32_t key2_data7:32; - }; - uint32_t val; -} efuse_rd_key2_data7_reg_t; - -/** Type of rd_key3_data0 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY3. - */ - uint32_t key3_data0:32; - }; - uint32_t val; -} efuse_rd_key3_data0_reg_t; - -/** Type of rd_key3_data1 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY3. - */ - uint32_t key3_data1:32; - }; - uint32_t val; -} efuse_rd_key3_data1_reg_t; - -/** Type of rd_key3_data2 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY3. - */ - uint32_t key3_data2:32; - }; - uint32_t val; -} efuse_rd_key3_data2_reg_t; - -/** Type of rd_key3_data3 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY3. - */ - uint32_t key3_data3:32; - }; - uint32_t val; -} efuse_rd_key3_data3_reg_t; - -/** Type of rd_key3_data4 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY3. - */ - uint32_t key3_data4:32; - }; - uint32_t val; -} efuse_rd_key3_data4_reg_t; - -/** Type of rd_key3_data5 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY3. - */ - uint32_t key3_data5:32; - }; - uint32_t val; -} efuse_rd_key3_data5_reg_t; - -/** Type of rd_key3_data6 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY3. - */ - uint32_t key3_data6:32; - }; - uint32_t val; -} efuse_rd_key3_data6_reg_t; - -/** Type of rd_key3_data7 register - * Register $n of BLOCK7 (KEY3). - */ -typedef union { - struct { - /** key3_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY3. - */ - uint32_t key3_data7:32; - }; - uint32_t val; -} efuse_rd_key3_data7_reg_t; - -/** Type of rd_key4_data0 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY4. - */ - uint32_t key4_data0:32; - }; - uint32_t val; -} efuse_rd_key4_data0_reg_t; - -/** Type of rd_key4_data1 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY4. - */ - uint32_t key4_data1:32; - }; - uint32_t val; -} efuse_rd_key4_data1_reg_t; - -/** Type of rd_key4_data2 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY4. - */ - uint32_t key4_data2:32; - }; - uint32_t val; -} efuse_rd_key4_data2_reg_t; - -/** Type of rd_key4_data3 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY4. - */ - uint32_t key4_data3:32; - }; - uint32_t val; -} efuse_rd_key4_data3_reg_t; - -/** Type of rd_key4_data4 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY4. - */ - uint32_t key4_data4:32; - }; - uint32_t val; -} efuse_rd_key4_data4_reg_t; - -/** Type of rd_key4_data5 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY4. - */ - uint32_t key4_data5:32; - }; - uint32_t val; -} efuse_rd_key4_data5_reg_t; - -/** Type of rd_key4_data6 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY4. - */ - uint32_t key4_data6:32; - }; - uint32_t val; -} efuse_rd_key4_data6_reg_t; - -/** Type of rd_key4_data7 register - * Register $n of BLOCK8 (KEY4). - */ -typedef union { - struct { - /** key4_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY4. - */ - uint32_t key4_data7:32; - }; - uint32_t val; -} efuse_rd_key4_data7_reg_t; - -/** Type of rd_key5_data0 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY5. - */ - uint32_t key5_data0:32; - }; - uint32_t val; -} efuse_rd_key5_data0_reg_t; - -/** Type of rd_key5_data1 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY5. - */ - uint32_t key5_data1:32; - }; - uint32_t val; -} efuse_rd_key5_data1_reg_t; - -/** Type of rd_key5_data2 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY5. - */ - uint32_t key5_data2:32; - }; - uint32_t val; -} efuse_rd_key5_data2_reg_t; - -/** Type of rd_key5_data3 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY5. - */ - uint32_t key5_data3:32; - }; - uint32_t val; -} efuse_rd_key5_data3_reg_t; - -/** Type of rd_key5_data4 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY5. - */ - uint32_t key5_data4:32; - }; - uint32_t val; -} efuse_rd_key5_data4_reg_t; - -/** Type of rd_key5_data5 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY5. - */ - uint32_t key5_data5:32; - }; - uint32_t val; -} efuse_rd_key5_data5_reg_t; - -/** Type of rd_key5_data6 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY5. - */ - uint32_t key5_data6:32; - }; - uint32_t val; -} efuse_rd_key5_data6_reg_t; - -/** Type of rd_key5_data7 register - * Register $n of BLOCK9 (KEY5). - */ -typedef union { - struct { - /** key5_data7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY5. - */ - uint32_t key5_data7:32; - }; - uint32_t val; -} efuse_rd_key5_data7_reg_t; +/** Group: block10 registers */ /** Type of rd_sys_part2_data0 register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data */ typedef union { struct { - /** adc2_hi_dout_atten0 : R; bitpos: [9:0]; default: 0; - * HI_DOUT of ADC2 atten0 + /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; + * Represents the first 32-bit of second part of system data. */ - uint32_t adc2_hi_dout_atten0:10; - /** adc2_hi_dout_atten1 : R; bitpos: [19:10]; default: 0; - * HI_DOUT of ADC2 atten1 - */ - uint32_t adc2_hi_dout_atten1:10; - /** adc2_hi_dout_atten2 : R; bitpos: [29:20]; default: 0; - * HI_DOUT of ADC2 atten2 - */ - uint32_t adc2_hi_dout_atten2:10; - /** adc2_hi_dout_atten3 : R; bitpos: [31:30]; default: 0; - * HI_DOUT of ADC2 atten3 - */ - uint32_t adc2_hi_dout_atten3:2; + uint32_t sys_data_part2_0:32; }; uint32_t val; } efuse_rd_sys_part2_data0_reg_t; /** Type of rd_sys_part2_data1 register - * Register $n of BLOCK9 (KEY5). + * Represents rd_sys_part2_data */ typedef union { struct { - /** adc2_hi_dout_atten3_1 : R; bitpos: [7:0]; default: 0; - * HI_DOUT of ADC2 atten3 + /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; + * Represents the first 32-bit of second part of system data. */ - uint32_t adc2_hi_dout_atten3_1:8; - /** adc1_ch0_atten0_initcode_diff : R; bitpos: [11:8]; default: 0; - * Gap between ADC1_ch0 and average initcode - */ - uint32_t adc1_ch0_atten0_initcode_diff:4; - /** adc1_ch1_atten0_initcode_diff : R; bitpos: [15:12]; default: 0; - * Gap between ADC1_ch1 and average initcode - */ - uint32_t adc1_ch1_atten0_initcode_diff:4; - /** adc1_ch2_atten0_initcode_diff : R; bitpos: [19:16]; default: 0; - * Gap between ADC1_ch2 and average initcode - */ - uint32_t adc1_ch2_atten0_initcode_diff:4; - /** adc1_ch3_atten0_initcode_diff : R; bitpos: [23:20]; default: 0; - * Gap between ADC1_ch3 and average initcode - */ - uint32_t adc1_ch3_atten0_initcode_diff:4; - /** adc1_ch4_atten0_initcode_diff : R; bitpos: [27:24]; default: 0; - * Gap between ADC1_ch4 and average initcode - */ - uint32_t adc1_ch4_atten0_initcode_diff:4; - /** adc1_ch5_atten0_initcode_diff : R; bitpos: [31:28]; default: 0; - * Gap between ADC1_ch5 and average initcode - */ - uint32_t adc1_ch5_atten0_initcode_diff:4; + uint32_t sys_data_part2_1:32; }; uint32_t val; } efuse_rd_sys_part2_data1_reg_t; /** Type of rd_sys_part2_data2 register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data */ typedef union { struct { - /** adc1_ch6_atten0_initcode_diff : R; bitpos: [3:0]; default: 0; - * Gap between ADC1_ch6 and average initcode + /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; + * Represents the second 32-bit of second part of system data. */ - uint32_t adc1_ch6_atten0_initcode_diff:4; - /** adc1_ch7_atten0_initcode_diff : R; bitpos: [7:4]; default: 0; - * Gap between ADC1_ch7 and average initcode - */ - uint32_t adc1_ch7_atten0_initcode_diff:4; - /** adc2_ch0_atten0_initcode_diff : R; bitpos: [11:8]; default: 0; - * Gap between ADC2_ch0 and average initcode - */ - uint32_t adc2_ch0_atten0_initcode_diff:4; - /** adc2_ch1_atten0_initcode_diff : R; bitpos: [15:12]; default: 0; - * Gap between ADC2_ch1 and average initcode - */ - uint32_t adc2_ch1_atten0_initcode_diff:4; - /** adc2_ch2_atten0_initcode_diff : R; bitpos: [19:16]; default: 0; - * Gap between ADC2_ch2 and average initcode - */ - uint32_t adc2_ch2_atten0_initcode_diff:4; - /** adc2_ch3_atten0_initcode_diff : R; bitpos: [23:20]; default: 0; - * Gap between ADC2_ch3 and average initcode - */ - uint32_t adc2_ch3_atten0_initcode_diff:4; - /** adc2_ch4_atten0_initcode_diff : R; bitpos: [27:24]; default: 0; - * Gap between ADC2_ch4 and average initcode - */ - uint32_t adc2_ch4_atten0_initcode_diff:4; - /** adc2_ch5_atten0_initcode_diff : R; bitpos: [31:28]; default: 0; - * Gap between ADC2_ch5 and average initcode - */ - uint32_t adc2_ch5_atten0_initcode_diff:4; + uint32_t sys_data_part2_2:32; }; uint32_t val; } efuse_rd_sys_part2_data2_reg_t; /** Type of rd_sys_part2_data3 register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data */ typedef union { struct { - /** temperature_sensor : R; bitpos: [8:0]; default: 0; - * Temperature calibration data + /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; + * Represents the third 32-bit of second part of system data. */ - uint32_t temperature_sensor:9; - /** reserved_10_105 : R; bitpos: [31:9]; default: 0; - * reserved - */ - uint32_t reserved_10_105:23; + uint32_t sys_data_part2_3:32; }; uint32_t val; } efuse_rd_sys_part2_data3_reg_t; /** Type of rd_sys_part2_data4 register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data */ typedef union { struct { /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the fourth 32-bit of second part of system data. */ uint32_t sys_data_part2_4:32; }; @@ -1742,12 +978,12 @@ typedef union { } efuse_rd_sys_part2_data4_reg_t; /** Type of rd_sys_part2_data5 register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data */ typedef union { struct { /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + * Represents the fifth 32-bit of second part of system data. */ uint32_t sys_data_part2_5:32; }; @@ -1755,457 +991,595 @@ typedef union { } efuse_rd_sys_part2_data5_reg_t; /** Type of rd_sys_part2_data6 register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data */ typedef union { struct { - /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + /** pvt_limit : RO; bitpos: [15:0]; default: 0; + * Power glitch monitor threthold. */ - uint32_t sys_data_part2_6:32; + uint32_t pvt_limit:16; + /** pvt_pump_limit : RO; bitpos: [23:16]; default: 0; + * Use to configure voltage monitor limit for charge pump + */ + uint32_t pvt_pump_limit:8; + /** pvt_cell_select : RO; bitpos: [30:24]; default: 0; + * Power glitch monitor PVT cell select. + */ + uint32_t pvt_cell_select:7; + /** rd_reserve_10_223 : RW; bitpos: [31]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_10_223:1; }; uint32_t val; } efuse_rd_sys_part2_data6_reg_t; /** Type of rd_sys_part2_data7 register - * Register $n of BLOCK10 (system). + * Represents rd_sys_part2_data */ typedef union { struct { - /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; - * Stores the $nth 32 bits of the 2nd part of system data. + /** pump_drv : RO; bitpos: [3:0]; default: 0; + * Use to configure charge pump voltage gain */ - uint32_t sys_data_part2_7:32; + uint32_t pump_drv:4; + /** usb_device_exchg_pins : RO; bitpos: [4]; default: 0; + * Enable usb device exchange pins of D+ and D-. + */ + uint32_t usb_device_exchg_pins:1; + /** usb_otg11_exchg_pins : RO; bitpos: [5]; default: 0; + * Enable usb otg11 exchange pins of D+ and D-. + */ + uint32_t usb_otg11_exchg_pins:1; + /** usb_device_drefh : RO; bitpos: [7:6]; default: 0; + * usb intphy of usb device single-end input high threshold, 1.76V to 2V. step by 80mV. + */ + uint32_t usb_device_drefh:2; + /** usb_otg11_drefh : RO; bitpos: [9:8]; default: 0; + * usb intphy of usb otg11 single-end input high threshold, 1.76V to 2V. step by 80mV. + */ + uint32_t usb_otg11_drefh:2; + /** usb_device_drefl : RO; bitpos: [11:10]; default: 0; + * usb intphy of usb device single-end input low threshold, 0.8V to 1.04V. step by + * 80mV. + */ + uint32_t usb_device_drefl:2; + /** usb_otg11_drefl : RO; bitpos: [13:12]; default: 0; + * usb intphy of usb otg11 single-end input low threshold, 0.8V to 1.04V. step by 80mV. + */ + uint32_t usb_otg11_drefl:2; + /** rd_reserve_10_238 : RW; bitpos: [31:14]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_10_238:18; }; uint32_t val; } efuse_rd_sys_part2_data7_reg_t; -/** Type of rd_repeat_err0 register - * Programming error record register 0 of BLOCK0. + +/** Group: block0 error report registers */ +/** Type of rd_repeat_data_err0 register + * Represents rd_repeat_data_err */ typedef union { struct { /** rd_dis_err : RO; bitpos: [6:0]; default: 0; - * Indicates a programming error of RD_DIS. + * Represents the programming error of EFUSE_RD_DIS */ uint32_t rd_dis_err:7; - /** dis_usb_device_exchg_pins_err : RO; bitpos: [7]; default: 0; - * Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS. + /** recovery_bootloader_flash_sector_0_1_err : RO; bitpos: [8:7]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1 */ - uint32_t dis_usb_device_exchg_pins_err:1; - /** dis_usb_otg11_exchg_pins_err : RO; bitpos: [8]; default: 0; - * Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS. - */ - uint32_t dis_usb_otg11_exchg_pins_err:1; + uint32_t recovery_bootloader_flash_sector_0_1_err:2; /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0; - * Indicates a programming error of DIS_USB_JTAG. + * Represents the programming error of EFUSE_DIS_USB_JTAG */ uint32_t dis_usb_jtag_err:1; - /** powerglitch_en_err : RO; bitpos: [10]; default: 0; - * Indicates a programming error of POWERGLITCH_EN. + /** recovery_bootloader_flash_sector_2_2_err : RO; bitpos: [10]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2 */ - uint32_t powerglitch_en_err:1; + uint32_t recovery_bootloader_flash_sector_2_2_err:1; /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0; - * Indicates a programming error of DIS_USB_SERIAL_JTAG. + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG */ uint32_t dis_usb_serial_jtag_err:1; /** dis_force_download_err : RO; bitpos: [12]; default: 0; - * Indicates a programming error of DIS_FORCE_DOWNLOAD. + * Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD */ uint32_t dis_force_download_err:1; /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0; - * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + * Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS */ uint32_t spi_download_mspi_dis_err:1; /** dis_twai_err : RO; bitpos: [14]; default: 0; - * Indicates a programming error of DIS_TWAI. + * Represents the programming error of EFUSE_DIS_TWAI */ uint32_t dis_twai_err:1; /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0; - * Indicates a programming error of JTAG_SEL_ENABLE. + * Represents the programming error of EFUSE_JTAG_SEL_ENABLE */ uint32_t jtag_sel_enable_err:1; /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0; - * Indicates a programming error of SOFT_DIS_JTAG. + * Represents the programming error of EFUSE_SOFT_DIS_JTAG */ uint32_t soft_dis_jtag_err:3; /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0; - * Indicates a programming error of DIS_PAD_JTAG. + * Represents the programming error of EFUSE_DIS_PAD_JTAG */ uint32_t dis_pad_jtag_err:1; /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0; - * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT */ uint32_t dis_download_manual_encrypt_err:1; - /** usb_device_drefh_err : RO; bitpos: [22:21]; default: 0; - * Indicates a programming error of USB_DEVICE_DREFH. + /** recovery_bootloader_flash_sector_3_6_err : RO; bitpos: [24:21]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6 */ - uint32_t usb_device_drefh_err:2; - /** usb_otg11_drefh_err : RO; bitpos: [24:23]; default: 0; - * Indicates a programming error of USB_OTG11_DREFH. - */ - uint32_t usb_otg11_drefh_err:2; + uint32_t recovery_bootloader_flash_sector_3_6_err:4; /** usb_phy_sel_err : RO; bitpos: [25]; default: 0; - * Indicates a programming error of USB_PHY_SEL. + * Represents the programming error of EFUSE_USB_PHY_SEL */ uint32_t usb_phy_sel_err:1; - /** huk_gen_state_low_err : RO; bitpos: [31:26]; default: 0; - * Indicates a programming error of HUK_GEN_STATE_LOW. + /** huk_gen_state_err : RO; bitpos: [30:26]; default: 0; + * Represents the programming error of EFUSE_HUK_GEN_STATE */ - uint32_t huk_gen_state_low_err:6; + uint32_t huk_gen_state_err:5; + /** recovery_bootloader_flash_sector_7_7_err : RO; bitpos: [31]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7 + */ + uint32_t recovery_bootloader_flash_sector_7_7_err:1; }; uint32_t val; -} efuse_rd_repeat_err0_reg_t; +} efuse_rd_repeat_data_err0_reg_t; -/** Type of rd_repeat_err1 register - * Programming error record register 1 of BLOCK0. +/** Type of rd_repeat_data_err1 register + * Represents rd_repeat_data_err */ typedef union { struct { - /** km_huk_gen_state_high_err : RO; bitpos: [2:0]; default: 0; - * Indicates a programming error of HUK_GEN_STATE_HIGH. + /** recovery_bootloader_flash_sector_8_10_err : RO; bitpos: [2:0]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10 */ - uint32_t km_huk_gen_state_high_err:3; - /** km_rnd_switch_cycle_err : RO; bitpos: [4:3]; default: 0; - * Indicates a programming error of KM_RND_SWITCH_CYCLE. + uint32_t recovery_bootloader_flash_sector_8_10_err:3; + /** recovery_bootloader_flash_sector_11_11_err : RO; bitpos: [3]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11 */ - uint32_t km_rnd_switch_cycle_err:2; + uint32_t recovery_bootloader_flash_sector_11_11_err:1; + /** km_rnd_switch_cycle_err : RO; bitpos: [4]; default: 0; + * Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE + */ + uint32_t km_rnd_switch_cycle_err:1; /** km_deploy_only_once_err : RO; bitpos: [8:5]; default: 0; - * Indicates a programming error of KM_DEPLOY_ONLY_ONCE. + * Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE */ uint32_t km_deploy_only_once_err:4; /** force_use_key_manager_key_err : RO; bitpos: [12:9]; default: 0; - * Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY. + * Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY */ uint32_t force_use_key_manager_key_err:4; /** force_disable_sw_init_key_err : RO; bitpos: [13]; default: 0; - * Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY. + * Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY */ uint32_t force_disable_sw_init_key_err:1; - /** xts_key_length_256_err : RO; bitpos: [14]; default: 0; - * Indicates a programming error of XTS_KEY_LENGTH_256. + /** km_xts_key_length_256_err : RO; bitpos: [14]; default: 0; + * Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256 */ - uint32_t xts_key_length_256_err:1; - uint32_t reserved_15:1; - /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; - * Indicates a programming error of WDT_DELAY_SEL. + uint32_t km_xts_key_length_256_err:1; + /** ecc_force_const_time_err : RO; bitpos: [15]; default: 0; + * Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME */ - uint32_t wdt_delay_sel_err:2; + uint32_t ecc_force_const_time_err:1; + uint32_t reserved_16:1; + /** wdt_delay_sel_err : RO; bitpos: [17]; default: 0; + * Represents the programming error of EFUSE_WDT_DELAY_SEL + */ + uint32_t wdt_delay_sel_err:1; /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; - * Indicates a programming error of SPI_BOOT_CRYPT_CNT. + * Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT */ uint32_t spi_boot_crypt_cnt_err:3; /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0 */ uint32_t secure_boot_key_revoke0_err:1; /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1 */ uint32_t secure_boot_key_revoke1_err:1; /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; - * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + * Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2 */ uint32_t secure_boot_key_revoke2_err:1; /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; - * Indicates a programming error of KEY_PURPOSE_0. + * Represents the programming error of EFUSE_KEY_PURPOSE_0 */ uint32_t key_purpose_0_err:4; /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; - * Indicates a programming error of KEY_PURPOSE_1. + * Represents the programming error of EFUSE_KEY_PURPOSE_1 */ uint32_t key_purpose_1_err:4; }; uint32_t val; -} efuse_rd_repeat_err1_reg_t; +} efuse_rd_repeat_data_err1_reg_t; -/** Type of rd_repeat_err2 register - * Programming error record register 2 of BLOCK0. +/** Type of rd_repeat_data_err2 register + * Represents rd_repeat_data_err */ typedef union { struct { /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; - * Indicates a programming error of KEY_PURPOSE_2. + * Represents the programming error of EFUSE_KEY_PURPOSE_2 */ uint32_t key_purpose_2_err:4; /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; - * Indicates a programming error of KEY_PURPOSE_3. + * Represents the programming error of EFUSE_KEY_PURPOSE_3 */ uint32_t key_purpose_3_err:4; /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; - * Indicates a programming error of KEY_PURPOSE_4. + * Represents the programming error of EFUSE_KEY_PURPOSE_4 */ uint32_t key_purpose_4_err:4; /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; - * Indicates a programming error of KEY_PURPOSE_5. + * Represents the programming error of EFUSE_KEY_PURPOSE_5 */ uint32_t key_purpose_5_err:4; /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0; - * Indicates a programming error of SEC_DPA_LEVEL. + * Represents the programming error of EFUSE_SEC_DPA_LEVEL */ uint32_t sec_dpa_level_err:2; - /** ecdsa_enable_soft_k_err : RO; bitpos: [18]; default: 0; - * Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K. + uint32_t reserved_18:1; + /** xts_dpa_clk_enable_err : RO; bitpos: [19]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE */ - uint32_t ecdsa_enable_soft_k_err:1; - /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0; - * Indicates a programming error of CRYPT_DPA_ENABLE. - */ - uint32_t crypt_dpa_enable_err:1; + uint32_t xts_dpa_clk_enable_err:1; /** secure_boot_en_err : RO; bitpos: [20]; default: 0; - * Indicates a programming error of SECURE_BOOT_EN. + * Represents the programming error of EFUSE_SECURE_BOOT_EN */ uint32_t secure_boot_en_err:1; /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; - * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + * Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE */ uint32_t secure_boot_aggressive_revoke_err:1; - uint32_t reserved_22:1; - /** flash_type_err : RO; bitpos: [23]; default: 0; - * Indicates a programming error of FLASH_TYPE. + /** km_deploy_only_once_h_err : RO; bitpos: [22]; default: 0; + * Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE_H */ - uint32_t flash_type_err:1; - /** flash_page_size_err : RO; bitpos: [25:24]; default: 0; - * Indicates a programming error of FLASH_PAGE_SIZE. + uint32_t km_deploy_only_once_h_err:1; + /** force_use_key_manager_key_h_err : RO; bitpos: [23]; default: 0; + * Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY_H */ - uint32_t flash_page_size_err:2; + uint32_t force_use_key_manager_key_h_err:1; + uint32_t reserved_24:2; /** flash_ecc_en_err : RO; bitpos: [26]; default: 0; - * Indicates a programming error of FLASH_ECC_EN. + * Represents the programming error of EFUSE_FLASH_ECC_EN */ uint32_t flash_ecc_en_err:1; /** dis_usb_otg_download_mode_err : RO; bitpos: [27]; default: 0; - * Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE. + * Represents the programming error of EFUSE_DIS_USB_OTG_DOWNLOAD_MODE */ uint32_t dis_usb_otg_download_mode_err:1; /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; - * Indicates a programming error of FLASH_TPUW. + * Represents the programming error of EFUSE_FLASH_TPUW */ uint32_t flash_tpuw_err:4; }; uint32_t val; -} efuse_rd_repeat_err2_reg_t; +} efuse_rd_repeat_data_err2_reg_t; -/** Type of rd_repeat_err3 register - * Programming error record register 3 of BLOCK0. +/** Type of rd_repeat_data_err3 register + * Represents rd_repeat_data_err */ typedef union { struct { /** dis_download_mode_err : RO; bitpos: [0]; default: 0; - * Indicates a programming error of DIS_DOWNLOAD_MODE. + * Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE */ uint32_t dis_download_mode_err:1; /** dis_direct_boot_err : RO; bitpos: [1]; default: 0; - * Indicates a programming error of DIS_DIRECT_BOOT. + * Represents the programming error of EFUSE_DIS_DIRECT_BOOT */ uint32_t dis_direct_boot_err:1; /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0; - * Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR. + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT */ uint32_t dis_usb_serial_jtag_rom_print_err:1; /** lock_km_key_err : RO; bitpos: [3]; default: 0; - * TBD + * Represents the programming error of EFUSE_LOCK_KM_KEY */ uint32_t lock_km_key_err:1; /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0; - * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE */ uint32_t dis_usb_serial_jtag_download_mode_err:1; /** enable_security_download_err : RO; bitpos: [5]; default: 0; - * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + * Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD */ uint32_t enable_security_download_err:1; /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; - * Indicates a programming error of UART_PRINT_CONTROL. + * Represents the programming error of EFUSE_UART_PRINT_CONTROL */ uint32_t uart_print_control_err:2; /** force_send_resume_err : RO; bitpos: [8]; default: 0; - * Indicates a programming error of FORCE_SEND_RESUME. + * Represents the programming error of EFUSE_FORCE_SEND_RESUME */ uint32_t force_send_resume_err:1; /** secure_version_err : RO; bitpos: [24:9]; default: 0; - * Indicates a programming error of SECURE VERSION. + * Represents the programming error of EFUSE_SECURE_VERSION */ uint32_t secure_version_err:16; /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0; - * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + * Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE */ uint32_t secure_boot_disable_fast_wake_err:1; /** hys_en_pad_err : RO; bitpos: [26]; default: 0; - * Indicates a programming error of HYS_EN_PAD. + * Represents the programming error of EFUSE_HYS_EN_PAD */ uint32_t hys_en_pad_err:1; - /** dcdc_vset_err : RO; bitpos: [31:27]; default: 0; - * Indicates a programming error of DCDC_VSET. + /** key_purpose_0_h_err : RO; bitpos: [27]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_0_H */ - uint32_t dcdc_vset_err:5; + uint32_t key_purpose_0_h_err:1; + /** key_purpose_1_h_err : RO; bitpos: [28]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_1_H + */ + uint32_t key_purpose_1_h_err:1; + /** key_purpose_2_h_err : RO; bitpos: [29]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_2_H + */ + uint32_t key_purpose_2_h_err:1; + /** key_purpose_3_h_err : RO; bitpos: [30]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_3_H + */ + uint32_t key_purpose_3_h_err:1; + /** key_purpose_4_h_err : RO; bitpos: [31]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_4_H + */ + uint32_t key_purpose_4_h_err:1; }; uint32_t val; -} efuse_rd_repeat_err3_reg_t; +} efuse_rd_repeat_data_err3_reg_t; -/** Type of rd_repeat_err4 register - * Programming error record register 4 of BLOCK0. +/** Type of rd_repeat_data_err4 register + * Represents rd_repeat_data_err */ typedef union { struct { /** pxa0_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0; - * Indicates a programming error of 0PXA_TIEH_SEL_0. + * Represents the programming error of EFUSE_0PXA_TIEH_SEL_0 */ uint32_t pxa0_tieh_sel_0_err:2; - /** pxa0_tieh_sel_1_err : RO; bitpos: [3:2]; default: 0; - * Indicates a programming error of 0PXA_TIEH_SEL_1. + /** pvt_glitch_en_err : RO; bitpos: [2]; default: 0; + * Represents the programming error of EFUSE_PVT_GLITCH_EN */ - uint32_t pxa0_tieh_sel_1_err:2; - /** pxa0_tieh_sel_2_err : RO; bitpos: [5:4]; default: 0; - * Indicates a programming error of 0PXA_TIEH_SEL_2. + uint32_t pvt_glitch_en_err:1; + uint32_t reserved_3:1; + /** key_purpose_5_h_err : RO; bitpos: [4]; default: 0; + * Represents the programming error of EFUSE_KEY_PURPOSE_5_H */ - uint32_t pxa0_tieh_sel_2_err:2; - /** pxa0_tieh_sel_3_err : RO; bitpos: [7:6]; default: 0; - * Indicates a programming error of 0PXA_TIEH_SEL_3. + uint32_t key_purpose_5_h_err:1; + uint32_t reserved_5:2; + /** km_disable_deploy_mode_h_err : RO; bitpos: [7]; default: 0; + * Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE_H */ - uint32_t pxa0_tieh_sel_3_err:2; + uint32_t km_disable_deploy_mode_h_err:1; /** km_disable_deploy_mode_err : RO; bitpos: [11:8]; default: 0; - * TBD. + * Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE */ uint32_t km_disable_deploy_mode_err:4; - /** usb_device_drefl_err : RO; bitpos: [13:12]; default: 0; - * Indicates a programming error of USB_DEVICE_DREFL. + uint32_t reserved_12:4; + /** xts_dpa_pseudo_level_err : RO; bitpos: [17:16]; default: 0; + * Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL */ - uint32_t usb_device_drefl_err:2; - /** usb_otg11_drefl_err : RO; bitpos: [15:14]; default: 0; - * Indicates a programming error of USB_OTG11_DREFL. - */ - uint32_t usb_otg11_drefl_err:2; - uint32_t reserved_16:2; + uint32_t xts_dpa_pseudo_level_err:2; /** hp_pwr_src_sel_err : RO; bitpos: [18]; default: 0; - * Indicates a programming error of HP_PWR_SRC_SEL. + * Represents the programming error of EFUSE_HP_PWR_SRC_SEL */ uint32_t hp_pwr_src_sel_err:1; - /** dcdc_vset_en_err : RO; bitpos: [19]; default: 0; - * Indicates a programming error of DCDC_VSET_EN. + /** secure_boot_sha384_en_err : RO; bitpos: [19]; default: 0; + * Represents the programming error of EFUSE_SECURE_BOOT_SHA384_EN */ - uint32_t dcdc_vset_en_err:1; + uint32_t secure_boot_sha384_en_err:1; /** dis_wdt_err : RO; bitpos: [20]; default: 0; - * Indicates a programming error of DIS_WDT. + * Represents the programming error of EFUSE_DIS_WDT */ uint32_t dis_wdt_err:1; /** dis_swd_err : RO; bitpos: [21]; default: 0; - * Indicates a programming error of DIS_SWD. + * Represents the programming error of EFUSE_DIS_SWD */ uint32_t dis_swd_err:1; - uint32_t reserved_22:10; + /** pvt_glitch_mode_err : RO; bitpos: [23:22]; default: 0; + * Represents the programming error of EFUSE_PVT_GLITCH_MODE + */ + uint32_t pvt_glitch_mode_err:2; + uint32_t reserved_24:8; }; uint32_t val; -} efuse_rd_repeat_err4_reg_t; +} efuse_rd_repeat_data_err4_reg_t; -/** Type of rd_rs_err0 register - * Programming error record register 0 of BLOCK1-10. + +/** Group: EFUSE ECDSA Configure Registers */ +/** Type of ecdsa register + * eFuse status register. */ typedef union { struct { - /** mac_sys_err_num : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. + /** cfg_ecdsa_p192_blk : R/W; bitpos: [3:0]; default: 0; + * Configures which block to use for ECDSA P192 key output. */ - uint32_t mac_sys_err_num:3; - /** mac_sys_fail : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. + uint32_t cfg_ecdsa_p192_blk:4; + /** cfg_ecdsa_p256_blk : R/W; bitpos: [7:4]; default: 0; + * Configures which block to use for ECDSA P256 key output. */ - uint32_t mac_sys_fail:1; - /** sys_part1_err_num : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t cfg_ecdsa_p256_blk:4; + /** cfg_ecdsa_p384_l_blk : R/W; bitpos: [11:8]; default: 0; + * Configures which block to use for ECDSA P384 key low part output. */ - uint32_t sys_part1_err_num:3; - /** sys_part1_fail : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part1 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. + uint32_t cfg_ecdsa_p384_l_blk:4; + /** cfg_ecdsa_p384_h_blk : R/W; bitpos: [15:12]; default: 0; + * Configures which block to use for ECDSA P256 key high part output. */ - uint32_t sys_part1_fail:1; - /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t cfg_ecdsa_p384_h_blk:4; + /** cur_ecdsa_p192_blk : RO; bitpos: [19:16]; default: 0; + * Represents which block is used for ECDSA P192 key output. */ - uint32_t usr_data_err_num:3; - /** usr_data_fail : RO; bitpos: [11]; default: 0; - * 0: Means no failure and that the user data is reliable 1: Means that programming - * user data failed and the number of error bytes is over 6. + uint32_t cur_ecdsa_p192_blk:4; + /** cur_ecdsa_p256_blk : RO; bitpos: [23:20]; default: 0; + * Represents which block is used for ECDSA P256 key output. */ - uint32_t usr_data_fail:1; - /** key0_err_num : RO; bitpos: [14:12]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t cur_ecdsa_p256_blk:4; + /** cur_ecdsa_p384_l_blk : RO; bitpos: [27:24]; default: 0; + * Represents which block is used for ECDSA P384 key low part output. */ - uint32_t key0_err_num:3; - /** key0_fail : RO; bitpos: [15]; default: 0; - * 0: Means no failure and that the data of key0 is reliable 1: Means that programming - * key0 failed and the number of error bytes is over 6. + uint32_t cur_ecdsa_p384_l_blk:4; + /** cur_ecdsa_p384_h_blk : RO; bitpos: [31:28]; default: 0; + * Represents which block is used for ECDSA P384 key high part output. */ - uint32_t key0_fail:1; - /** key1_err_num : RO; bitpos: [18:16]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key1_err_num:3; - /** key1_fail : RO; bitpos: [19]; default: 0; - * 0: Means no failure and that the data of key1 is reliable 1: Means that programming - * key1 failed and the number of error bytes is over 6. - */ - uint32_t key1_fail:1; - /** key2_err_num : RO; bitpos: [22:20]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key2_err_num:3; - /** key2_fail : RO; bitpos: [23]; default: 0; - * 0: Means no failure and that the data of key2 is reliable 1: Means that programming - * key2 failed and the number of error bytes is over 6. - */ - uint32_t key2_fail:1; - /** key3_err_num : RO; bitpos: [26:24]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key3_err_num:3; - /** key3_fail : RO; bitpos: [27]; default: 0; - * 0: Means no failure and that the data of key3 is reliable 1: Means that programming - * key3 failed and the number of error bytes is over 6. - */ - uint32_t key3_fail:1; - /** key4_err_num : RO; bitpos: [30:28]; default: 0; - * The value of this signal means the number of error bytes. - */ - uint32_t key4_err_num:3; - /** key4_fail : RO; bitpos: [31]; default: 0; - * 0: Means no failure and that the data of key4 is reliable 1: Means that programming - * key4 failed and the number of error bytes is over 6. - */ - uint32_t key4_fail:1; + uint32_t cur_ecdsa_p384_h_blk:4; }; uint32_t val; -} efuse_rd_rs_err0_reg_t; +} efuse_ecdsa_reg_t; -/** Type of rd_rs_err1 register - * Programming error record register 1 of BLOCK1-10. + +/** Group: RS block error report registers */ +/** Type of rd_rs_data_err0 register + * Represents rd_rs_data_err */ typedef union { struct { - /** key5_err_num : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. + /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_mac_sys */ - uint32_t key5_err_num:3; - /** key5_fail : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of key5 is reliable 1: Means that programming - * key5 failed and the number of error bytes is over 6. + uint32_t rd_mac_sys_err_num:3; + /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_mac_sys is reliable + * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. */ - uint32_t key5_fail:1; - /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. + uint32_t rd_mac_sys_fail:1; + /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part1_data */ - uint32_t sys_part2_err_num:3; - /** sys_part2_fail : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part2 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. + uint32_t rd_sys_part1_data_err_num:3; + /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part1_data is reliable + * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is + * over 6. */ - uint32_t sys_part2_fail:1; + uint32_t rd_sys_part1_data_fail:1; + /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_usr_data + */ + uint32_t rd_usr_data_err_num:3; + /** rd_usr_data_fail : RO; bitpos: [11]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_usr_data is reliable + * 1: Means that programming rd_usr_data failed and the number of error bytes is over + * 6. + */ + uint32_t rd_usr_data_fail:1; + /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key0_data + */ + uint32_t rd_key0_data_err_num:3; + /** rd_key0_data_fail : RO; bitpos: [15]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key0_data is reliable + * 1: Means that programming rd_key0_data failed and the number of error bytes is over + * 6. + */ + uint32_t rd_key0_data_fail:1; + /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key1_data + */ + uint32_t rd_key1_data_err_num:3; + /** rd_key1_data_fail : RO; bitpos: [19]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key1_data is reliable + * 1: Means that programming rd_key1_data failed and the number of error bytes is over + * 6. + */ + uint32_t rd_key1_data_fail:1; + /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key2_data + */ + uint32_t rd_key2_data_err_num:3; + /** rd_key2_data_fail : RO; bitpos: [23]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key2_data is reliable + * 1: Means that programming rd_key2_data failed and the number of error bytes is over + * 6. + */ + uint32_t rd_key2_data_fail:1; + /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key3_data + */ + uint32_t rd_key3_data_err_num:3; + /** rd_key3_data_fail : RO; bitpos: [27]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key3_data is reliable + * 1: Means that programming rd_key3_data failed and the number of error bytes is over + * 6. + */ + uint32_t rd_key3_data_fail:1; + /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key4_data + */ + uint32_t rd_key4_data_err_num:3; + /** rd_key4_data_fail : RO; bitpos: [31]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key4_data is reliable + * 1: Means that programming rd_key4_data failed and the number of error bytes is over + * 6. + */ + uint32_t rd_key4_data_fail:1; + }; + uint32_t val; +} efuse_rd_rs_data_err0_reg_t; + +/** Type of rd_rs_data_err1 register + * Represents rd_rs_data_err + */ +typedef union { + struct { + /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key5_data + */ + uint32_t rd_key5_data_err_num:3; + /** rd_key5_data_fail : RO; bitpos: [3]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_key5_data is reliable + * 1: Means that programming rd_key5_data failed and the number of error bytes is over + * 6. + */ + uint32_t rd_key5_data_fail:1; + /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0; + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part2_data + */ + uint32_t rd_sys_part2_data_err_num:3; + /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0; + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part2_data is reliable + * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is + * over 6. + */ + uint32_t rd_sys_part2_data_fail:1; uint32_t reserved_8:24; }; uint32_t val; -} efuse_rd_rs_err1_reg_t; +} efuse_rd_rs_data_err1_reg_t; + +/** Group: ******** Registers */ /** Type of clk register * eFuse clcok configuration register. */ @@ -2242,11 +1616,7 @@ typedef union { * 0x5A5A: programming operation command 0x5AA5: read operation command. */ uint32_t op_code:16; - /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0; - * Configures which block to use for ECDSA key output. - */ - uint32_t cfg_ecdsa_blk:4; - uint32_t reserved_20:12; + uint32_t reserved_16:16; }; uint32_t val; } efuse_conf_reg_t; @@ -2288,11 +1658,7 @@ typedef union { * Indicates the number of block valid bit. */ uint32_t blk0_valid_bit_cnt:10; - /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0; - * Indicates which block is used for ECDSA key output. - */ - uint32_t cur_ecdsa_blk:4; - uint32_t reserved_24:8; + uint32_t reserved_20:12; }; uint32_t val; } efuse_status_reg_t; @@ -2515,7 +1881,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36720720; + /** date : R/W; bitpos: [27:0]; default: 38805904; * Stores eFuse version. */ uint32_t date:28; @@ -4475,29 +3841,20 @@ typedef union { typedef struct { - volatile efuse_pgm_data0_reg_t pgm_data0; - volatile efuse_pgm_data1_reg_t pgm_data1; - volatile efuse_pgm_data2_reg_t pgm_data2; - volatile efuse_pgm_data3_reg_t pgm_data3; - volatile efuse_pgm_data4_reg_t pgm_data4; - volatile efuse_pgm_data5_reg_t pgm_data5; - volatile efuse_pgm_data6_reg_t pgm_data6; - volatile efuse_pgm_data7_reg_t pgm_data7; - volatile efuse_pgm_check_value0_reg_t pgm_check_value0; - volatile efuse_pgm_check_value1_reg_t pgm_check_value1; - volatile efuse_pgm_check_value2_reg_t pgm_check_value2; + volatile efuse_pgm_datan_reg_t pgm_datan[8]; + volatile efuse_pgm_check_valuen_reg_t pgm_check_valuen[3]; volatile efuse_rd_wr_dis_reg_t rd_wr_dis; volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; - volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0; - volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1; - volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2; - volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3; - volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4; - volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5; + volatile efuse_rd_mac_sys0_reg_t rd_mac_sys_0; + volatile efuse_rd_mac_sys1_reg_t rd_mac_sys_1; + volatile efuse_rd_mac_sys2_reg_t rd_mac_sys_2; + volatile efuse_rd_mac_sys3_reg_t rd_mac_sys_3; + volatile efuse_rd_mac_sys4_reg_t rd_mac_sys_4; + volatile efuse_rd_mac_sys5_reg_t rd_mac_sys_5; volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; @@ -4514,54 +3871,12 @@ typedef struct { volatile efuse_rd_usr_data5_reg_t rd_usr_data5; volatile efuse_rd_usr_data6_reg_t rd_usr_data6; volatile efuse_rd_usr_data7_reg_t rd_usr_data7; - volatile efuse_rd_key0_data0_reg_t rd_key0_data0; - volatile efuse_rd_key0_data1_reg_t rd_key0_data1; - volatile efuse_rd_key0_data2_reg_t rd_key0_data2; - volatile efuse_rd_key0_data3_reg_t rd_key0_data3; - volatile efuse_rd_key0_data4_reg_t rd_key0_data4; - volatile efuse_rd_key0_data5_reg_t rd_key0_data5; - volatile efuse_rd_key0_data6_reg_t rd_key0_data6; - volatile efuse_rd_key0_data7_reg_t rd_key0_data7; - volatile efuse_rd_key1_data0_reg_t rd_key1_data0; - volatile efuse_rd_key1_data1_reg_t rd_key1_data1; - volatile efuse_rd_key1_data2_reg_t rd_key1_data2; - volatile efuse_rd_key1_data3_reg_t rd_key1_data3; - volatile efuse_rd_key1_data4_reg_t rd_key1_data4; - volatile efuse_rd_key1_data5_reg_t rd_key1_data5; - volatile efuse_rd_key1_data6_reg_t rd_key1_data6; - volatile efuse_rd_key1_data7_reg_t rd_key1_data7; - volatile efuse_rd_key2_data0_reg_t rd_key2_data0; - volatile efuse_rd_key2_data1_reg_t rd_key2_data1; - volatile efuse_rd_key2_data2_reg_t rd_key2_data2; - volatile efuse_rd_key2_data3_reg_t rd_key2_data3; - volatile efuse_rd_key2_data4_reg_t rd_key2_data4; - volatile efuse_rd_key2_data5_reg_t rd_key2_data5; - volatile efuse_rd_key2_data6_reg_t rd_key2_data6; - volatile efuse_rd_key2_data7_reg_t rd_key2_data7; - volatile efuse_rd_key3_data0_reg_t rd_key3_data0; - volatile efuse_rd_key3_data1_reg_t rd_key3_data1; - volatile efuse_rd_key3_data2_reg_t rd_key3_data2; - volatile efuse_rd_key3_data3_reg_t rd_key3_data3; - volatile efuse_rd_key3_data4_reg_t rd_key3_data4; - volatile efuse_rd_key3_data5_reg_t rd_key3_data5; - volatile efuse_rd_key3_data6_reg_t rd_key3_data6; - volatile efuse_rd_key3_data7_reg_t rd_key3_data7; - volatile efuse_rd_key4_data0_reg_t rd_key4_data0; - volatile efuse_rd_key4_data1_reg_t rd_key4_data1; - volatile efuse_rd_key4_data2_reg_t rd_key4_data2; - volatile efuse_rd_key4_data3_reg_t rd_key4_data3; - volatile efuse_rd_key4_data4_reg_t rd_key4_data4; - volatile efuse_rd_key4_data5_reg_t rd_key4_data5; - volatile efuse_rd_key4_data6_reg_t rd_key4_data6; - volatile efuse_rd_key4_data7_reg_t rd_key4_data7; - volatile efuse_rd_key5_data0_reg_t rd_key5_data0; - volatile efuse_rd_key5_data1_reg_t rd_key5_data1; - volatile efuse_rd_key5_data2_reg_t rd_key5_data2; - volatile efuse_rd_key5_data3_reg_t rd_key5_data3; - volatile efuse_rd_key5_data4_reg_t rd_key5_data4; - volatile efuse_rd_key5_data5_reg_t rd_key5_data5; - volatile efuse_rd_key5_data6_reg_t rd_key5_data6; - volatile efuse_rd_key5_data7_reg_t rd_key5_data7; + volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8]; + volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8]; + volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8]; + volatile efuse_rd_key3_datan_reg_t rd_key3_datan[8]; + volatile efuse_rd_key4_datan_reg_t rd_key4_datan[8]; + volatile efuse_rd_key5_datan_reg_t rd_key5_datan[8]; volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; @@ -4570,14 +3885,16 @@ typedef struct { volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; - volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; - volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; - volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; - volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; - volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; - uint32_t reserved_190[12]; - volatile efuse_rd_rs_err0_reg_t rd_rs_err0; - volatile efuse_rd_rs_err1_reg_t rd_rs_err1; + volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0; + volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1; + volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2; + volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3; + volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4; + uint32_t reserved_190[8]; + volatile efuse_ecdsa_reg_t ecdsa; + uint32_t reserved_1b4[3]; + volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0; + volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1; volatile efuse_clk_reg_t clk; volatile efuse_conf_reg_t conf; volatile efuse_status_reg_t status;