refactor(esp32c5): change beta3 path in esp_rom

components/esp_rom/esp32c5/Kconfig.soc_caps.in

@@ -1,80 +1,7 @@
-#####################################################
-# This file is auto-generated from SoC caps
-# using gen_soc_caps_kconfig.py, do not edit manually
-#####################################################
+if IDF_TARGET_ESP32C5_BETA3_VERSION
+    orsource "./beta3/esp32c5/Kconfig.soc_caps.in"
+endif
 
-config ESP_ROM_HAS_CRC_LE
-    bool
-    default y
-
-config ESP_ROM_HAS_CRC_BE
-    bool
-    default y
-
-config ESP_ROM_HAS_JPEG_DECODE
-    bool
-    default y
-
-config ESP_ROM_UART_CLK_IS_XTAL
-    bool
-    default y
-
-config ESP_ROM_USB_SERIAL_DEVICE_NUM
-    int
-    default 3
-
-config ESP_ROM_HAS_RETARGETABLE_LOCKING
-    bool
-    default y
-
-config ESP_ROM_GET_CLK_FREQ
-    bool
-    default y
-
-config ESP_ROM_HAS_RVFPLIB
-    bool
-    default y
-
-config ESP_ROM_HAS_HAL_WDT
-    bool
-    default y
-
-config ESP_ROM_HAS_HAL_SYSTIMER
-    bool
-    default y
-
-config ESP_ROM_HAS_HEAP_TLSF
-    bool
-    default y
-
-config ESP_ROM_TLSF_CHECK_PATCH
-    bool
-    default y
-
-config ESP_ROM_HAS_LAYOUT_TABLE
-    bool
-    default y
-
-config ESP_ROM_HAS_SPI_FLASH
-    bool
-    default y
-
-config ESP_ROM_WITHOUT_REGI2C
-    bool
-    default y
-
-config ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT
-    bool
-    default y
-
-config ESP_ROM_WDT_INIT_PATCH
-    bool
-    default y
-
-config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
-    bool
-    default y
-
-config ESP_ROM_USB_OTG_NUM
-    int
-    default -1
+if IDF_TARGET_ESP32C5_MP_VERSION
+    orsource "./mp/esp32c5/Kconfig.soc_caps.in"
+endif

components/esp_rom/esp32c5/beta3/esp32c5/Kconfig.soc_caps.in

@@ -0,0 +1,80 @@
+#####################################################
+# This file is auto-generated from SoC caps
+# using gen_soc_caps_kconfig.py, do not edit manually
+#####################################################
+
+config ESP_ROM_HAS_CRC_LE
+    bool
+    default y
+
+config ESP_ROM_HAS_CRC_BE
+    bool
+    default y
+
+config ESP_ROM_HAS_JPEG_DECODE
+    bool
+    default y
+
+config ESP_ROM_UART_CLK_IS_XTAL
+    bool
+    default y
+
+config ESP_ROM_USB_SERIAL_DEVICE_NUM
+    int
+    default 3
+
+config ESP_ROM_HAS_RETARGETABLE_LOCKING
+    bool
+    default y
+
+config ESP_ROM_GET_CLK_FREQ
+    bool
+    default y
+
+config ESP_ROM_HAS_RVFPLIB
+    bool
+    default y
+
+config ESP_ROM_HAS_HAL_WDT
+    bool
+    default y
+
+config ESP_ROM_HAS_HAL_SYSTIMER
+    bool
+    default y
+
+config ESP_ROM_HAS_HEAP_TLSF
+    bool
+    default y
+
+config ESP_ROM_TLSF_CHECK_PATCH
+    bool
+    default y
+
+config ESP_ROM_HAS_LAYOUT_TABLE
+    bool
+    default y
+
+config ESP_ROM_HAS_SPI_FLASH
+    bool
+    default y
+
+config ESP_ROM_WITHOUT_REGI2C
+    bool
+    default y
+
+config ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT
+    bool
+    default y
+
+config ESP_ROM_WDT_INIT_PATCH
+    bool
+    default y
+
+config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
+    bool
+    default y
+
+config ESP_ROM_USB_OTG_NUM
+    int
+    default -1

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.heap.ld

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 /* ROM function interface esp32c5.rom.heap.ld for esp32c5
  *
  *

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.ld

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 /* ROM function interface esp32c5.rom.ld for esp32c5
  *
  *
@@ -575,4 +580,3 @@ slc_reattach = 0x40000c64;
 slc_send_to_host_chain = 0x40000c68;
 slc_set_host_io_max_window = 0x40000c6c;
 slc_to_host_chain_recycle = 0x40000c70;
-

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.libgcc.ld

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 /* ROM function interface esp32c5.rom.libgcc.ld for esp32c5
  *
  *
@@ -112,4 +117,3 @@ __umodsi3 = 0x400009d0;
 __unorddf2 = 0x400009d4;
 __extenddftf2 = 0x400009d8;
 __trunctfdf2 = 0x400009dc;
-

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.newlib-normal.ld

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 /* ROM function interface esp32c5.rom.newlib-normal.ld for esp32c5
  *
  *
@@ -34,4 +39,3 @@ vsnprintf = 0x40000614;
 vsniprintf = 0x40000618;
 sscanf = 0x4000061c;
 siscanf = 0x40000620;
-

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.newlib.ld

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 /* ROM function interface esp32c5.rom.newlib.ld for esp32c5
  *
  *
@@ -92,4 +97,3 @@ __swsetup_r = 0x400005cc;
 /* Data (.data, .bss, .rodata) */
 syscall_table_ptr = 0x4087ffd4;
 _global_impure_ptr = 0x4087ffd0;
-

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.rvfp.ld

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 /* ROM function interface esp32c5.rom.rvfp.ld for esp32c5
  *
  *

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.spiflash.ld

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 /* ROM function interface esp32c5.rom.spiflash.ld for esp32c5
  *
  *
@@ -158,4 +163,3 @@ spi_flash_encryption_hal_prepare = 0x40000380;
 spi_flash_encryption_hal_done = 0x40000384;
 spi_flash_encryption_hal_destroy = 0x40000388;
 spi_flash_encryption_hal_check = 0x4000038c;
-

components/esp_rom/esp32c5/beta3/esp32c5/ld/esp32c5.rom.version.ld

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 /* ROM version variables for esp32c5
  *
  * These addresses should be compatible with any ROM version for this chip.