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Merge branch 'feat/dynamic_usb_hal_backport_v5.3' into 'release/v5.3'

Browse Source 
feat(hal/usb): Make USB-DWC HAL&LL configuration independent backport v5.3

See merge request espressif/esp-idf!34811
This commit is contained in:
morris
2024-12-07 23:19:56 +08:00
parent cd3d85ae4b 177679b74e
commit 3946fbb142
28 changed files with 2687 additions and 320 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/CMakeLists.txt
+1 -4
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@@ -138,10 +138,7 @@ if(CONFIG_SOC_IEEE802154_SUPPORTED)
endif()
if(CONFIG_SOC_USB_OTG_SUPPORTED)
if(NOT ${target} STREQUAL "esp32p4")
list(APPEND srcs "${target_folder}/usb_periph.c"
"${target_folder}/usb_dwc_periph.c")
endif()
list(APPEND srcs "${target_folder}/usb_dwc_periph.c")
endif()
if(CONFIG_SOC_DAC_SUPPORTED)
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+8
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@@ -1087,6 +1087,14 @@ config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
bool
default y
config SOC_USB_OTG_PERIPH_NUM
int
default 2
config SOC_USB_UTMI_PHY_NUM
int
default 1
config SOC_PARLIO_GROUPS
int
default 1
components/soc/esp32p4/include/soc/soc_caps.h
+8 -1
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@@ -411,9 +411,16 @@
#define SOC_MCPWM_SUPPORT_EVENT_COMPARATOR (1) ///< Support event comparator (based on ETM)
#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
/*-------------------------- USB CAPS ----------------------------------------*/
// USB Serial JTAG Caps
// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
// USB OTG Caps
#define SOC_USB_OTG_PERIPH_NUM (2U)
// USB PHY Caps
#define SOC_USB_UTMI_PHY_NUM (1U)
/*-------------------------- PARLIO CAPS --------------------------------------*/
#define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */
#define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */
components/soc/esp32p4/include/soc/usb_dwc_cfg.h
+143 -67
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,94 +11,170 @@ extern "C" {
#endif
/*
HS Instance:
Configuration Set ID: 11
*/
/* 3.1 Basic Config Parameters */
#define OTG_MODE 0
#define OTG_ARCHITECTURE 2
#define OTG_SINGLE_POINT 1
#define OTG_ENABLE_LPM 0
#define OTG_EN_DED_TX_FIFO 1
#define OTG_EN_DESC_DMA 1
#define OTG_MULTI_PROC_INTRPT 1
#define OTG20_MODE 0
#define OTG20_ARCHITECTURE 2
#define OTG20_SINGLE_POINT 1
#define OTG20_ENABLE_LPM 0
#define OTG20_EN_DED_TX_FIFO 1
#define OTG20_EN_DESC_DMA 1
#define OTG20_MULTI_PROC_INTRPT 1
/* 3.2 USB Physical Layer Interface Parameters */
#define OTG_HSPHY_INTERFACE 3
#define OTG_HSPHY_DWIDTH 2
#define OTG_FSPHY_INTERFACE 2
#define OTG_ENABLE_IC_USB 0
#define OTG_ENABLE_HSIC 0
#define OTG_I2C_INTERFACE 0
#define OTG_ULPI_CARKIT 1
#define OTG_ADP_SUPPORT 1
#define OTG_BC_SUPPORT 0
#define OTG_VENDOR_CTL_INTERFACE 1
#define OTG20_HSPHY_INTERFACE 3
#define OTG20_HSPHY_DWIDTH 2
#define OTG20_FSPHY_INTERFACE 2
#define OTG20_ENABLE_IC_USB 0
#define OTG20_ENABLE_HSIC 0
#define OTG20_I2C_INTERFACE 0
#define OTG20_ULPI_CARKIT 1
#define OTG20_ADP_SUPPORT 1
#define OTG20_BC_SUPPORT 0
#define OTG20_VENDOR_CTL_INTERFACE 1
/* 3.3 Device Endpoint Configuration Parameters */
#define OTG_NUM_EPS 15
#define OTG_NUM_IN_EPS 8
#define OTG_NUM_CRL_EPS 1
#define OTG20_NUM_EPS 15
#define OTG20_NUM_IN_EPS 8
#define OTG20_NUM_CRL_EPS 1
/* 3.4 Host Endpoint Configuration Parameters */
#define OTG_NUM_HOST_CHAN 16
#define OTG_EN_PERIO_HOST 1
#define OTG20_NUM_HOST_CHAN 16
#define OTG20_EN_PERIO_HOST 1
/* 3.5 Endpoint Channel FIFO Configuration Parameters */
#define OTG_DFIFO_DEPTH 1024
#define OTG_DFIFO_DYNAMIC 1
#define OTG_RX_DFIFO_DEPTH 1024
#define OTG_TX_HNPERIO_DFIFO_DEPTH 1024
#define OTG_TX_HPERIO_DFIFO_DEPTH 1024
#define OTG_NPERIO_TX_QUEUE_DEPTH 4
#define OTG_PERIO_TX_QUEUE_DEPTH 4
#define OTG20_DFIFO_DEPTH 1024
#define OTG20_DFIFO_DYNAMIC 1
#define OTG20_RX_DFIFO_DEPTH 1024
#define OTG20_TX_HNPERIO_DFIFO_DEPTH 1024
#define OTG20_TX_HPERIO_DFIFO_DEPTH 1024
#define OTG20_NPERIO_TX_QUEUE_DEPTH 4
#define OTG20_PERIO_TX_QUEUE_DEPTH 4
/* 3.6 Additional Configuration Options Parameters */
#define OTG_TRANS_COUNT_WIDTH 17
#define OTG_PACKET_COUNT_WIDTH 8
#define OTG_RM_OPT_FEATURES 1
#define OTG_EN_PWROPT 1
#define OTG_SYNC_RESET_TYPE 0
#define OTG_EN_IDDIG_FILTER 1
#define OTG_EN_VBUSVALID_FILTER 1
#define OTG_EN_A_VALID_FILTER 1
#define OTG_EN_B_VALID_FILTER 1
#define OTG_EN_SESSIONEND_FILTER 1
#define OTG_EXCP_CNTL_XFER_FLOW 1
#define OTG_PWR_CLAMP 0
#define OTG_PWR_SWITCH_POLARITY 0
#define OTG20_TRANS_COUNT_WIDTH 17
#define OTG20_PACKET_COUNT_WIDTH 8
#define OTG20_RM_OPT_FEATURES 1
#define OTG20_EN_PWROPT 1
#define OTG20_SYNC_RESET_TYPE 0
#define OTG20_EN_IDDIG_FILTER 1
#define OTG20_EN_VBUSVALID_FILTER 1
#define OTG20_EN_A_VALID_FILTER 1
#define OTG20_EN_B_VALID_FILTER 1
#define OTG20_EN_SESSIONEND_FILTER 1
#define OTG20_EXCP_CNTL_XFER_FLOW 1
#define OTG20_PWR_CLAMP 0
#define OTG20_PWR_SWITCH_POLARITY 0
/* 3.7 Endpoint Direction Parameters */
#define OTG_EP_DIR_1 0
#define OTG_EP_DIR_2 0
#define OTG_EP_DIR_3 0
#define OTG_EP_DIR_4 0
#define OTG_EP_DIR_5 0
#define OTG_EP_DIR_6 0
#define OTG_EP_DIR_7 0
#define OTG_EP_DIR_8 0
#define OTG_EP_DIR_9 0
#define OTG_EP_DIR_10 0
#define OTG_EP_DIR_11 0
#define OTG_EP_DIR_12 0
#define OTG_EP_DIR_13 0
#define OTG_EP_DIR_14 0
#define OTG_EP_DIR_15 0
#define OTG20_EP_DIR_1 0
#define OTG20_EP_DIR_2 0
#define OTG20_EP_DIR_3 0
#define OTG20_EP_DIR_4 0
#define OTG20_EP_DIR_5 0
#define OTG20_EP_DIR_6 0
#define OTG20_EP_DIR_7 0
#define OTG20_EP_DIR_8 0
#define OTG20_EP_DIR_9 0
#define OTG20_EP_DIR_10 0
#define OTG20_EP_DIR_11 0
#define OTG20_EP_DIR_12 0
#define OTG20_EP_DIR_13 0
#define OTG20_EP_DIR_14 0
#define OTG20_EP_DIR_15 0
/* 3.8 Device Periodic FIFO Depth Parameters */
/* 3.9 Device IN Endpoint FIFO Depth Parameters */
#define OTG_TX_DINEP_DFIFO_DEPTH_0 512
#define OTG_TX_DINEP_DFIFO_DEPTH_1 512
#define OTG_TX_DINEP_DFIFO_DEPTH_2 512
#define OTG_TX_DINEP_DFIFO_DEPTH_3 512
#define OTG_TX_DINEP_DFIFO_DEPTH_4 512
#define OTG_TX_DINEP_DFIFO_DEPTH_5 512
#define OTG_TX_DINEP_DFIFO_DEPTH_6 512
#define OTG_TX_DINEP_DFIFO_DEPTH_7 512
#define OTG20_TX_DINEP_DFIFO_DEPTH_0 512
#define OTG20_TX_DINEP_DFIFO_DEPTH_1 512
#define OTG20_TX_DINEP_DFIFO_DEPTH_2 512
#define OTG20_TX_DINEP_DFIFO_DEPTH_3 512
#define OTG20_TX_DINEP_DFIFO_DEPTH_4 512
#define OTG20_TX_DINEP_DFIFO_DEPTH_5 512
#define OTG20_TX_DINEP_DFIFO_DEPTH_6 512
#define OTG20_TX_DINEP_DFIFO_DEPTH_7 512
/* 3.10 UTMI-To-UTMI Bridge Component Parameters */
#define DWC_U2UB_EN 0
#define OTG20_U2UB_EN 0
/*
FS Instance:
Configuration Set ID: 1
*/
/* 3.1 Basic Config Parameters */
#define OTG11_MODE 0
#define OTG11_ARCHITECTURE 2
#define OTG11_SINGLE_POINT 1
#define OTG11_ENABLE_LPM 0
#define OTG11_EN_DED_TX_FIFO 1
#define OTG11_EN_DESC_DMA 1
#define OTG11_MULTI_PROC_INTRPT 0
/* 3.2 USB Physical Layer Interface Parameters */
#define OTG11_HSPHY_INTERFACE 0
#define OTG11_FSPHY_INTERFACE 1
#define OTG11_ENABLE_IC_USB 0
#define OTG11_I2C_INTERFACE 0
#define OTG11_ADP_SUPPORT 0
#define OTG11_BC_SUPPORT 0
/* 3.3 Device Endpoint Configuration Parameters */
#define OTG11_NUM_EPS 6
#define OTG11_NUM_IN_EPS 5
#define OTG11_NUM_CRL_EPS 0
/* 3.4 Host Endpoint Configuration Parameters */
#define OTG11_NUM_HOST_CHAN 8
#define OTG11_EN_PERIO_HOST 1
/* 3.5 Endpoint Channel FIFO Configuration Parameters */
#define OTG11_DFIFO_DEPTH 256
#define OTG11_DFIFO_DYNAMIC 1
#define OTG11_RX_DFIFO_DEPTH 256
#define OTG11_TX_HNPERIO_DFIFO_DEPTH 256
#define OTG11_TX_NPERIO_DFIFO_DEPTH 256
#define OTG11_TX_HPERIO_DFIFO_DEPTH 256
#define OTG11_NPERIO_TX_QUEUE_DEPTH 4
#define OTG11_PERIO_TX_QUEUE_DEPTH 8
/* 3.6 Additional Configuration Options Parameters */
#define OTG11_TRANS_COUNT_WIDTH 16
#define OTG11_PACKET_COUNT_WIDTH 7
#define OTG11_RM_OPT_FEATURES 1
#define OTG11_EN_PWROPT 1
#define OTG11_SYNC_RESET_TYPE 0
#define OTG11_EN_IDDIG_FILTER 1
#define OTG11_EN_VBUSVALID_FILTER 1
#define OTG11_EN_A_VALID_FILTER 1
#define OTG11_EN_B_VALID_FILTER 1
#define OTG11_EN_SESSIONEND_FILTER 1
#define OTG11_EXCP_CNTL_XFER_FLOW 1
#define OTG11_PWR_CLAMP 0
#define OTG11_PWR_SWITCH_POLARITY 0
/* 3.7 Endpoint Direction Parameters */
#define OTG11_EP_DIR_1 0
#define OTG11_EP_DIR_2 0
#define OTG11_EP_DIR_3 0
#define OTG11_EP_DIR_4 0
#define OTG11_EP_DIR_5 0
#define OTG11_EP_DIR_6 0
/* 3.8 Device Periodic FIFO Depth Parameters */
/* 3.9 Device IN Endpoint FIFO Depth Parameters */
#define OTG11_TX_DINEP_DFIFO_DEPTH_1 256
#define OTG11_TX_DINEP_DFIFO_DEPTH_2 256
#define OTG11_TX_DINEP_DFIFO_DEPTH_3 256
#define OTG11_TX_DINEP_DFIFO_DEPTH_4 256
/* 3.10 UTMI-To-UTMI Bridge Component Parameters */
#define OTG11_U2UB_EN 0
#ifdef __cplusplus
}
components/soc/esp32p4/include/soc/usb_dwc_struct.h
+6 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,7 +13,10 @@ extern "C" {
#endif
/*
Registers and fields were generated based on a set of configuration options.
Registers and fields were generated based on a set of USB-DWC configuration options.
ESP32-P4 contains 2 instances of USB-DWC with different configurations, the structure below corresponds to the HS instance.
The FS instance contains a subset of registers from HS instance, the user (HAL) is responsible for accessing only existing fields.
See ESP32-P4 "usb_dwc_cfg.h" for more details.
*/
@@ -1368,6 +1371,7 @@ _Static_assert(sizeof(usb_dwc_dev_t) == 0xe08, "Invalid size of usb_dwc_dev_t st
#endif
extern usb_dwc_dev_t USB_DWC_HS;
extern usb_dwc_dev_t USB_DWC_FS;
#ifdef __cplusplus
}
components/soc/esp32p4/usb_dwc_periph.c
+50
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@@ -0,0 +1,50 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stddef.h>
#include "soc/interrupts.h"
#include "soc/gpio_sig_map.h"
#include "soc/usb_dwc_periph.h"
#include "soc/usb_dwc_struct.h"
/* -------------------------------- Private --------------------------------- */
static const usb_utmi_otg_signal_conn_t dwc_fs_otg_signals = {
// Inputs
.iddig = USB_OTG11_IDDIG_PAD_IN_IDX,
.avalid = USB_OTG11_AVALID_PAD_IN_IDX,
.bvalid = USB_SRP_BVALID_PAD_IN_IDX,
.vbusvalid = USB_OTG11_VBUSVALID_PAD_IN_IDX,
.sessend = USB_SRP_SESSEND_PAD_IN_IDX,
// Outputs
.idpullup = USB_OTG11_IDPULLUP_PAD_OUT_IDX,
.dppulldown = USB_OTG11_DPPULLDOWN_PAD_OUT_IDX,
.dmpulldown = USB_OTG11_DMPULLDOWN_PAD_OUT_IDX,
.drvvbus = USB_OTG11_DRVVBUS_PAD_OUT_IDX,
.chrgvbus = USB_SRP_CHRGVBUS_PAD_OUT_IDX,
.dischrgvbus = USB_SRP_DISCHRGVBUS_PAD_OUT_IDX,
};
/* --------------------------------- Public --------------------------------- */
const usb_dwc_info_t usb_dwc_info = {
.controllers = {
// High-Speed USB-DWC
[0] = {
.fsls_signals = NULL,
.otg_signals = NULL,
.irq = ETS_USB_OTG_INTR_SOURCE,
.irq_2nd_cpu = ETS_USB_OTG_ENDP_MULTI_PROC_INTR_SOURCE,
},
// Full-Speed USB-DWC
[1] = {
.fsls_signals = NULL,
.otg_signals = &dwc_fs_otg_signals,
.irq = ETS_USB_OTG11_CH0_INTR_SOURCE,
.irq_2nd_cpu = -1,
},
},
};
components/soc/esp32s2/include/soc/usb_dwc_struct.h
+2 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -88,7 +88,7 @@ typedef union {
struct {
uint32_t toutcal: 3;
uint32_t phyif: 1;
uint32_t reserved_4: 1;
uint32_t ulpiutmisel: 1;
uint32_t fsintf: 1;
uint32_t physel: 1;
uint32_t reserved_7: 1;
components/soc/esp32s2/usb_dwc_periph.c
+71 -1
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@@ -4,8 +4,78 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/usb_dwc_periph.h"
#include "soc/gpio_sig_map.h"
#include "soc/usb_periph.h"
#include "soc/interrupts.h"
#include "soc/usb_dwc_periph.h"
/* -------------------------------- Private --------------------------------- */
static const usb_fsls_serial_signal_conn_t fsls_signals = {
// Inputs
.rx_dp = USB_EXTPHY_VP_IDX,
.rx_dm = USB_EXTPHY_VM_IDX,
.rx_rcv = USB_EXTPHY_RCV_IDX,
// Outputs
.suspend_n = USB_EXTPHY_SUSPND_IDX,
.tx_enable_n = USB_EXTPHY_OEN_IDX,
.tx_dp = USB_EXTPHY_VPO_IDX,
.tx_dm = USB_EXTPHY_VMO_IDX,
.fs_edge_sel = USB_EXTPHY_SPEED_IDX,
};
static const usb_utmi_otg_signal_conn_t otg_signals = {
// Inputs
.iddig = USB_OTG_IDDIG_IN_IDX,
.avalid = USB_OTG_AVALID_IN_IDX,
.bvalid = USB_SRP_BVALID_IN_IDX,
.vbusvalid = USB_OTG_VBUSVALID_IN_IDX,
.sessend = USB_SRP_SESSEND_IN_IDX,
// Outputs
.idpullup = USB_OTG_IDPULLUP_IDX,
.dppulldown = USB_OTG_DPPULLDOWN_IDX,
.dmpulldown = USB_OTG_DMPULLDOWN_IDX,
.drvvbus = USB_OTG_DRVVBUS_IDX,
.chrgvbus = USB_SRP_CHRGVBUS_IDX,
.dischrgvbus = USB_SRP_DISCHRGVBUS_IDX,
};
/* --------------------------------- Public --------------------------------- */
const usb_dwc_info_t usb_dwc_info = {
.controllers = {
[0] = {
.fsls_signals = &fsls_signals,
.otg_signals = &otg_signals,
.irq = ETS_USB_INTR_SOURCE,
.irq_2nd_cpu = -1,
},
},
};
/* ------------------------------- Deprecated ------------------------------- */
/*
Note: These IO pins are deprecated. When connecting USB OTG to an external FSLS
PHY, the FSLS Serial Interface signals can be routed to any GPIO via the GPIO
matrix. Thus, this mapping of signals to IO pins is meaningless.
Todo: Remove in IDF v6.0 (IDF-9029)
*/
const usb_iopin_dsc_t usb_periph_iopins[] = {
{USBPHY_VP_NUM, USB_EXTPHY_VP_IDX, 0, 1},
{USBPHY_VM_NUM, USB_EXTPHY_VM_IDX, 0, 1},
{USBPHY_RCV_NUM, USB_EXTPHY_RCV_IDX, 0, 1},
{USBPHY_OEN_NUM, USB_EXTPHY_OEN_IDX, 1, 1},
{USBPHY_VPO_NUM, USB_EXTPHY_VPO_IDX, 1, 1},
{USBPHY_VMO_NUM, USB_EXTPHY_VMO_IDX, 1, 1},
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_IDDIG_IN_IDX, 0, 0}, //connected connector is mini-B
//connected connector is mini-B
{GPIO_MATRIX_CONST_ONE_INPUT, USB_SRP_BVALID_IN_IDX, 0, 0}, //HIGH to force USB device mode
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_VBUSVALID_IN_IDX, 0, 0}, //receiving a valid Vbus from host
{GPIO_MATRIX_CONST_ZERO_INPUT, USB_OTG_AVALID_IN_IDX, 0, 0},
{-1, -1, 0, 0}
};
/*
Bunch of constants for USB peripheral: GPIO signals
components/soc/esp32s2/usb_periph.c
-30
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@@ -1,30 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc_caps.h"
#include "soc/usb_periph.h"
/*
Note: These IO pins are deprecated. When connecting USB OTG to an external FSLS
PHY, the FSLS Serial Interface signals can be routed to any GPIO via the GPIO
matrix. Thus, this mapping of signals to IO pins is meaningless.
Todo: Remove in IDF v6.0 (IDF-9029)
*/
const usb_iopin_dsc_t usb_periph_iopins[] = {
{USBPHY_VP_NUM, USB_EXTPHY_VP_IDX, 0, 1},
{USBPHY_VM_NUM, USB_EXTPHY_VM_IDX, 0, 1},
{USBPHY_RCV_NUM, USB_EXTPHY_RCV_IDX, 0, 1},
{USBPHY_OEN_NUM, USB_EXTPHY_OEN_IDX, 1, 1},
{USBPHY_VPO_NUM, USB_EXTPHY_VPO_IDX, 1, 1},
{USBPHY_VMO_NUM, USB_EXTPHY_VMO_IDX, 1, 1},
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_IDDIG_IN_IDX, 0, 0}, //connected connector is mini-B
//connected connector is mini-B
{GPIO_MATRIX_CONST_ONE_INPUT, USB_SRP_BVALID_IN_IDX, 0, 0}, //HIGH to force USB device mode
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_VBUSVALID_IN_IDX, 0, 0}, //receiving a valid Vbus from host
{GPIO_MATRIX_CONST_ZERO_INPUT, USB_OTG_AVALID_IN_IDX, 0, 0},
{-1, -1, 0, 0}
};
components/soc/esp32s3/include/soc/usb_dwc_struct.h
+2 -2
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -88,7 +88,7 @@ typedef union {
struct {
uint32_t toutcal: 3;
uint32_t phyif: 1;
uint32_t reserved_4: 1;
uint32_t ulpiutmisel: 1;
uint32_t fsintf: 1;
uint32_t physel: 1;
uint32_t reserved_7: 1;
components/soc/esp32s3/usb_dwc_periph.c
+72 -1
View File
@@ -4,8 +4,79 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/usb_dwc_periph.h"
#include <stddef.h>
#include "soc/gpio_sig_map.h"
#include "soc/usb_periph.h"
#include "soc/interrupts.h"
#include "soc/usb_dwc_periph.h"
/* -------------------------------- Private --------------------------------- */
static const usb_fsls_serial_signal_conn_t fsls_signals = {
// Inputs
.rx_dp = USB_EXTPHY_VP_IDX,
.rx_dm = USB_EXTPHY_VM_IDX,
.rx_rcv = USB_EXTPHY_RCV_IDX,
// Outputs
.suspend_n = USB_EXTPHY_SUSPND_IDX,
.tx_enable_n = USB_EXTPHY_OEN_IDX,
.tx_dp = USB_EXTPHY_VPO_IDX,
.tx_dm = USB_EXTPHY_VMO_IDX,
.fs_edge_sel = USB_EXTPHY_SPEED_IDX,
};
static const usb_utmi_otg_signal_conn_t otg_signals = {
// Inputs
.iddig = USB_OTG_IDDIG_IN_IDX,
.avalid = USB_OTG_AVALID_IN_IDX,
.bvalid = USB_SRP_BVALID_IN_IDX,
.vbusvalid = USB_OTG_VBUSVALID_IN_IDX,
.sessend = USB_SRP_SESSEND_IN_IDX,
// Outputs
.idpullup = USB_OTG_IDPULLUP_IDX,
.dppulldown = USB_OTG_DPPULLDOWN_IDX,
.dmpulldown = USB_OTG_DMPULLDOWN_IDX,
.drvvbus = USB_OTG_DRVVBUS_IDX,
.chrgvbus = USB_SRP_CHRGVBUS_IDX,
.dischrgvbus = USB_SRP_DISCHRGVBUS_IDX,
};
/* --------------------------------- Public --------------------------------- */
const usb_dwc_info_t usb_dwc_info = {
.controllers = {
[0] = {
.fsls_signals = &fsls_signals,
.otg_signals = &otg_signals,
.irq = ETS_USB_INTR_SOURCE,
.irq_2nd_cpu = -1,
},
},
};
/* ------------------------------- Deprecated ------------------------------- */
/*
Note: These IO pins are deprecated. When connecting USB OTG to an external FSLS
PHY, the FSLS Serial Interface signals can be routed to any GPIO via the GPIO
matrix. Thus, this mapping of signals to IO pins is meaningless.
Todo: Remove in IDF v6.0 (IDF-9029)
*/
const usb_iopin_dsc_t usb_periph_iopins[] = {
{USBPHY_VP_NUM, USB_EXTPHY_VP_IDX, 0, 1},
{USBPHY_VM_NUM, USB_EXTPHY_VM_IDX, 0, 1},
{USBPHY_RCV_NUM, USB_EXTPHY_RCV_IDX, 0, 1},
{USBPHY_OEN_NUM, USB_EXTPHY_OEN_IDX, 1, 1},
{USBPHY_VPO_NUM, USB_EXTPHY_VPO_IDX, 1, 1},
{USBPHY_VMO_NUM, USB_EXTPHY_VMO_IDX, 1, 1},
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_IDDIG_IN_IDX, 0, 0}, //connected connector is mini-B
//connected connector is mini-B
{GPIO_MATRIX_CONST_ONE_INPUT, USB_SRP_BVALID_IN_IDX, 0, 0}, //HIGH to force USB device mode
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_VBUSVALID_IN_IDX, 0, 0}, //receiving a valid Vbus from host
{GPIO_MATRIX_CONST_ZERO_INPUT, USB_OTG_AVALID_IN_IDX, 0, 0},
{-1, -1, 0, 0}
};
/*
Bunch of constants for USB peripheral: GPIO signals
components/soc/esp32s3/usb_periph.c
-30
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@@ -1,30 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc_caps.h"
#include "soc/usb_periph.h"
/*
Note: These IO pins are deprecated. When connecting USB OTG to an external FSLS
PHY, the FSLS Serial Interface signals can be routed to any GPIO via the GPIO
matrix. Thus, this mapping of signals to IO pins is meaningless.
Todo: Remove in IDF v6.0 (IDF-9029)
*/
const usb_iopin_dsc_t usb_periph_iopins[] = {
{USBPHY_VP_NUM, USB_EXTPHY_VP_IDX, 0, 1},
{USBPHY_VM_NUM, USB_EXTPHY_VM_IDX, 0, 1},
{USBPHY_RCV_NUM, USB_EXTPHY_RCV_IDX, 0, 1},
{USBPHY_OEN_NUM, USB_EXTPHY_OEN_IDX, 1, 1},
{USBPHY_VPO_NUM, USB_EXTPHY_VPO_IDX, 1, 1},
{USBPHY_VMO_NUM, USB_EXTPHY_VMO_IDX, 1, 1},
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_IDDIG_IN_IDX, 0, 0}, //connected connector is mini-B
//connected connector is mini-B
{GPIO_MATRIX_CONST_ONE_INPUT, USB_SRP_BVALID_IN_IDX, 0, 0}, //HIGH to force USB device mode
{GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_VBUSVALID_IN_IDX, 0, 0}, //receiving a valid Vbus from host
{GPIO_MATRIX_CONST_ZERO_INPUT, USB_OTG_AVALID_IN_IDX, 0, 0},
{-1, -1, 0, 0}
};
components/soc/include/soc/usb_dwc_periph.h
+78 -1
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@@ -1,18 +1,93 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "soc/soc_pins.h"
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#include "soc/gpio_sig_map.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_USB_OTG_SUPPORTED
/* ---------------------------------- Types --------------------------------- */
/**
* @brief USB PHY FSLS Serial Interface Signals
*
* Structure to store the GPIO matrix signal indexes for a USB PHY FSLS Serial
* interface's signals.
*
* @note Refer to section "2.2.1.13 FsLsSerialMode" of the UTMI+ for more
* details regarding the FSLS Serial Interface.
*/
typedef struct {
// Inputs
int rx_dp;
int rx_dm;
int rx_rcv;
// Outputs
int suspend_n;
int tx_enable_n;
int tx_dp;
int tx_dm;
int fs_edge_sel;
} usb_fsls_serial_signal_conn_t;
/**
* @brief USB PHY UTMI OTG Interface Signal Index Type
*
* Structure to store the GPIO matrix signal indexes for a UTMI PHY interface's
* OTG signals.
*/
typedef struct {
// Inputs
int iddig;
int avalid;
int bvalid;
int vbusvalid;
int sessend;
// Outputs
int idpullup;
int dppulldown;
int dmpulldown;
int drvvbus;
int chrgvbus;
int dischrgvbus;
} usb_utmi_otg_signal_conn_t;
/**
* @brief USB Controller Information
*
* Structure to store information for all USB-DWC instances
*/
typedef struct {
struct {
const usb_fsls_serial_signal_conn_t * const fsls_signals; // Must be set if external PHY is supported by controller
const usb_utmi_otg_signal_conn_t * const otg_signals;
const int irq;
const int irq_2nd_cpu; // The USB-DWC can provide 2nd interrupt so each CPU can have its own interrupt line. Set to -1 if not supported
} controllers [SOC_USB_OTG_PERIPH_NUM];
} usb_dwc_info_t;
extern const usb_dwc_info_t usb_dwc_info;
#endif // SOC_USB_OTG_SUPPORTED
/* ------------------------------- Deprecated ------------------------------- */
/* Todo: Remove in ESP-IDF v6.0 (IDF-9052) */
#if SOC_USB_OTG_SUPPORTED
/*
Stores a bunch of USB-peripheral data.
*/
@@ -41,6 +116,8 @@ typedef struct {
extern const usb_phy_signal_conn_t usb_otg_periph_signal;
#endif // SOC_USB_OTG_SUPPORTED
#ifdef __cplusplus
}
#endif