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refactor(soc): Update the ESP32-P4v3+ PMS header files

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This commit is contained in:
Laukik Hase
2026-05-21 12:15:50 +05:30
parent 4811388910
commit 384eba8a11
16 changed files with 2761 additions and 9308 deletions
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components/soc/esp32p4/register/hw_ver3/soc/dma_pms_eco5_reg.h
-1575
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components/soc/esp32p4/register/hw_ver3/soc/dma_pms_reg.h
+24
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@@ -1584,6 +1584,30 @@ extern "C" {
#define PMS_DMA_SPM_MON_W_PMS_V 0xFFFFFFFFU
#define PMS_DMA_SPM_MON_W_PMS_S 0
/** PMS_DMA_REGDMA_PMS_R_REG register
* REGDMA read permission control registers.
*/
#define PMS_DMA_REGDMA_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1ec)
/** PMS_DMA_REGDMA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
* REGDMA read permission control, each bit corresponds to a region.
*/
#define PMS_DMA_REGDMA_R_PMS 0xFFFFFFFFU
#define PMS_DMA_REGDMA_R_PMS_M (PMS_DMA_REGDMA_R_PMS_V << PMS_DMA_REGDMA_R_PMS_S)
#define PMS_DMA_REGDMA_R_PMS_V 0xFFFFFFFFU
#define PMS_DMA_REGDMA_R_PMS_S 0
/** PMS_DMA_REGDMA_PMS_W_REG register
* REGDMA write permission control registers.
*/
#define PMS_DMA_REGDMA_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1f0)
/** PMS_DMA_REGDMA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
* REGDMA write permission control, each bit corresponds to a region.
*/
#define PMS_DMA_REGDMA_W_PMS 0xFFFFFFFFU
#define PMS_DMA_REGDMA_W_PMS_M (PMS_DMA_REGDMA_W_PMS_V << PMS_DMA_REGDMA_W_PMS_S)
#define PMS_DMA_REGDMA_W_PMS_V 0xFFFFFFFFU
#define PMS_DMA_REGDMA_W_PMS_S 0
/** PMS_DMA_H264_PMS_R_REG register
* H264 DMA read permission control register
*/
components/soc/esp32p4/register/hw_ver3/soc/dma_pms_struct.h
+506 -1310
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components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_eco5_reg.h
-778
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@@ -1,778 +0,0 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TEE_HP2LP_TEE_PMS_DATE_REG register
* NA
*/
#define TEE_HP2LP_TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943;
* NA
*/
#define TEE_TEE_DATE 0xFFFFFFFFU
#define TEE_TEE_DATE_M (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
#define TEE_TEE_DATE_V 0xFFFFFFFFU
#define TEE_TEE_DATE_S 0
/** TEE_PMS_CLK_EN_REG register
* NA
*/
#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_CLK_EN (BIT(0))
#define TEE_REG_CLK_EN_M (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
#define TEE_REG_CLK_EN_V 0x00000001U
#define TEE_REG_CLK_EN_S 0
/** TEE_HP_CORE0_MM_PMS_REG0_REG register
* NA
*/
#define TEE_HP_CORE0_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
/** TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW (BIT(0))
#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_S 0
/** TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW (BIT(1))
#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S 1
/** TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW (BIT(2))
#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_S 2
/** TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW (BIT(3))
#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_S 3
/** TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW (BIT(4))
#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_S 4
/** TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW (BIT(5))
#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_S 5
/** TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW (BIT(6))
#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_S 6
/** TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW (BIT(7))
#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_S 7
/** TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW (BIT(8))
#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S 8
/** TEE_REG_HP_CORE0_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW (BIT(9))
#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_S 9
/** TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW (BIT(10))
#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_S 10
/** TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW (BIT(11))
#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_S 11
/** TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW (BIT(12))
#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_S 12
/** TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW (BIT(13))
#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_S 13
/** TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW (BIT(14))
#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_S 14
/** TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW (BIT(15))
#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_S 15
/** TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW (BIT(16))
#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_S 16
/** TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW (BIT(17))
#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_S 17
/** TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW (BIT(18))
#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_S 18
/** TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW (BIT(19))
#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_S 19
/** TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW (BIT(20))
#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_S 20
/** TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW (BIT(21))
#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_S 21
/** TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW (BIT(22))
#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_S 22
/** TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW (BIT(23))
#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_S 23
/** TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW (BIT(24))
#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_M (TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_S)
#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_S 24
/** TEE_HP_CORE0_UM_PMS_REG0_REG register
* NA
*/
#define TEE_HP_CORE0_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0xc)
/** TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW (BIT(0))
#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_S 0
/** TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW (BIT(1))
#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S 1
/** TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW (BIT(2))
#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_S 2
/** TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW (BIT(3))
#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_S 3
/** TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW (BIT(4))
#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_S 4
/** TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW (BIT(5))
#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_S 5
/** TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW (BIT(6))
#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_S 6
/** TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW (BIT(7))
#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_S 7
/** TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW (BIT(8))
#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S 8
/** TEE_REG_HP_CORE0_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW (BIT(9))
#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_S 9
/** TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW (BIT(10))
#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_S 10
/** TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW (BIT(11))
#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_S 11
/** TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW (BIT(12))
#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_S 12
/** TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW (BIT(13))
#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_S 13
/** TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW (BIT(14))
#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_S 14
/** TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW (BIT(15))
#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_S 15
/** TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW (BIT(16))
#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_S 16
/** TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW (BIT(17))
#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_S 17
/** TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW (BIT(18))
#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_S 18
/** TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW (BIT(19))
#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_S 19
/** TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW (BIT(20))
#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_S 20
/** TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW (BIT(21))
#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_S 21
/** TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW (BIT(22))
#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_S 22
/** TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW (BIT(23))
#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_S 23
/** TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW (BIT(24))
#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_M (TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_S)
#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_S 24
/** TEE_HP_CORE1_MM_PMS_REG0_REG register
* NA
*/
#define TEE_HP_CORE1_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x10)
/** TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW (BIT(0))
#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_S 0
/** TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW (BIT(1))
#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S 1
/** TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW (BIT(2))
#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_S 2
/** TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW (BIT(3))
#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_S 3
/** TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW (BIT(4))
#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_S 4
/** TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW (BIT(5))
#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_S 5
/** TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW (BIT(6))
#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_S 6
/** TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW (BIT(7))
#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_S 7
/** TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW (BIT(8))
#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S 8
/** TEE_REG_HP_CORE1_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW (BIT(9))
#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_S 9
/** TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW (BIT(10))
#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_S 10
/** TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW (BIT(11))
#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_S 11
/** TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW (BIT(12))
#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_S 12
/** TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW (BIT(13))
#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_S 13
/** TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW (BIT(14))
#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_S 14
/** TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW (BIT(15))
#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_S 15
/** TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW (BIT(16))
#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_S 16
/** TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW (BIT(17))
#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_S 17
/** TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW (BIT(18))
#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_S 18
/** TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW (BIT(19))
#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_S 19
/** TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW (BIT(20))
#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_S 20
/** TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW (BIT(21))
#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_S 21
/** TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW (BIT(22))
#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_S 22
/** TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW (BIT(23))
#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_S 23
/** TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW (BIT(24))
#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_M (TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_S)
#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_S 24
/** TEE_HP_CORE1_UM_PMS_REG0_REG register
* NA
*/
#define TEE_HP_CORE1_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x14)
/** TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW (BIT(0))
#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_S 0
/** TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW (BIT(1))
#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S 1
/** TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW (BIT(2))
#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_S 2
/** TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW (BIT(3))
#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_S 3
/** TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW (BIT(4))
#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_S 4
/** TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW (BIT(5))
#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_S 5
/** TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW (BIT(6))
#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_S 6
/** TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW (BIT(7))
#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_S 7
/** TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW (BIT(8))
#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S 8
/** TEE_REG_HP_CORE1_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW (BIT(9))
#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_S 9
/** TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW (BIT(10))
#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_S 10
/** TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW (BIT(11))
#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_S 11
/** TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW (BIT(12))
#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_S 12
/** TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW (BIT(13))
#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_S 13
/** TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW (BIT(14))
#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_S 14
/** TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW (BIT(15))
#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_S 15
/** TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW (BIT(16))
#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_S 16
/** TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW (BIT(17))
#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_S 17
/** TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW (BIT(18))
#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_S 18
/** TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW (BIT(19))
#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_S 19
/** TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW (BIT(20))
#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_M (TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_S 20
/** TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW (BIT(21))
#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_S 21
/** TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW (BIT(22))
#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_S 22
/** TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW (BIT(23))
#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_S 23
/** TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
* NA
*/
#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW (BIT(24))
#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_M (TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_S)
#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_V 0x00000001U
#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_S 24
/** TEE_REGDMA_PERI_PMS_REG register
* NA
*/
#define TEE_REGDMA_PERI_PMS_REG (DR_REG_TEE_BASE + 0x18)
/** TEE_REG_REGDMA_PERI_LP_RAM_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW (BIT(0))
#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_M (TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_V << TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_S)
#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_V 0x00000001U
#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_S 0
/** TEE_REG_REGDMA_PERI_LP_PERI_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW (BIT(1))
#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_M (TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_V << TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_S)
#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_V 0x00000001U
#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_S 1
#ifdef __cplusplus
}
#endif
components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_reg.h
+36 -1
View File
@@ -14,7 +14,7 @@ extern "C" {
* Version control register
*/
#define PMS_HP2LP_PERI_PMS_DATE_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x0)
/** PMS_HP2LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294790;
/** PMS_HP2LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2363943;
* Version control register
*/
#define PMS_HP2LP_PERI_PMS_DATE 0xFFFFFFFFU
@@ -262,6 +262,14 @@ extern "C" {
#define PMS_HP_CORE0_MM_LP_SRAM_ALLOW_M (PMS_HP_CORE0_MM_LP_SRAM_ALLOW_V << PMS_HP_CORE0_MM_LP_SRAM_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_SRAM_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_SRAM_ALLOW_S 23
/** PMS_HP_CORE0_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access RNG.
* 0: Not allowed
* 1: Allowed */
#define PMS_HP_CORE0_MM_LP_TRNG_ALLOW (BIT(24))
#define PMS_HP_CORE0_MM_LP_TRNG_ALLOW_M (PMS_HP_CORE0_MM_LP_TRNG_ALLOW_V << PMS_HP_CORE0_MM_LP_TRNG_ALLOW_S)
#define PMS_HP_CORE0_MM_LP_TRNG_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_MM_LP_TRNG_ALLOW_S 24
/** PMS_HP_CORE0_UM_PMS_REG0_REG register
* Permission control register0 for HP CPU0 in user mode
@@ -487,6 +495,15 @@ extern "C" {
#define PMS_HP_CORE0_UM_LP_SRAM_ALLOW_M (PMS_HP_CORE0_UM_LP_SRAM_ALLOW_V << PMS_HP_CORE0_UM_LP_SRAM_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_SRAM_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_SRAM_ALLOW_S 23
/** PMS_HP_CORE0_UM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access RNG.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE0_UM_LP_TRNG_ALLOW (BIT(24))
#define PMS_HP_CORE0_UM_LP_TRNG_ALLOW_M (PMS_HP_CORE0_UM_LP_TRNG_ALLOW_V << PMS_HP_CORE0_UM_LP_TRNG_ALLOW_S)
#define PMS_HP_CORE0_UM_LP_TRNG_ALLOW_V 0x00000001U
#define PMS_HP_CORE0_UM_LP_TRNG_ALLOW_S 24
/** PMS_HP_CORE1_MM_PMS_REG0_REG register
* Permission control register0 for HP CPU1 in machine mode
@@ -714,6 +731,15 @@ extern "C" {
#define PMS_HP_CORE1_MM_LP_SRAM_ALLOW_M (PMS_HP_CORE1_MM_LP_SRAM_ALLOW_V << PMS_HP_CORE1_MM_LP_SRAM_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_SRAM_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_SRAM_ALLOW_S 23
/** PMS_HP_CORE1_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access RNG.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_MM_LP_TRNG_ALLOW (BIT(24))
#define PMS_HP_CORE1_MM_LP_TRNG_ALLOW_M (PMS_HP_CORE1_MM_LP_TRNG_ALLOW_V << PMS_HP_CORE1_MM_LP_TRNG_ALLOW_S)
#define PMS_HP_CORE1_MM_LP_TRNG_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_MM_LP_TRNG_ALLOW_S 24
/** PMS_HP_CORE1_UM_PMS_REG0_REG register
* Permission control register0 for HP CPU1 in user mode
@@ -939,6 +965,15 @@ extern "C" {
#define PMS_HP_CORE1_UM_LP_SRAM_ALLOW_M (PMS_HP_CORE1_UM_LP_SRAM_ALLOW_V << PMS_HP_CORE1_UM_LP_SRAM_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_SRAM_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_SRAM_ALLOW_S 23
/** PMS_HP_CORE1_UM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access RNG.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_HP_CORE1_UM_LP_TRNG_ALLOW (BIT(24))
#define PMS_HP_CORE1_UM_LP_TRNG_ALLOW_M (PMS_HP_CORE1_UM_LP_TRNG_ALLOW_V << PMS_HP_CORE1_UM_LP_TRNG_ALLOW_S)
#define PMS_HP_CORE1_UM_LP_TRNG_ALLOW_V 0x00000001U
#define PMS_HP_CORE1_UM_LP_TRNG_ALLOW_S 24
/** PMS_REGDMA_LP_PERI_PMS_REG register
* LP Peripheral Permission register for REGDMA
components/soc/esp32p4/register/hw_ver3/soc/hp2lp_peri_pms_struct.h
+307 -417
View File
@@ -10,519 +10,409 @@
extern "C" {
#endif
/** Group: TEE HP2LP TEE PMS DATE REG */
/** Type of hp2lp_tee_pms_date register
* NA
/** Group: Version Control Registers */
/** Type of hp2lp_peri_pms_date register
* Version control register
*/
typedef union {
struct {
/** tee_date : R/W; bitpos: [31:0]; default: 2363943;
* NA
/** hp2lp_peri_pms_date : R/W; bitpos: [31:0]; default: 2363943;
* Version control register
*/
uint32_t tee_date:32;
uint32_t hp2lp_peri_pms_date:32;
};
uint32_t val;
} tee_hp2lp_tee_pms_date_reg_t;
} pms_hp2lp_peri_pms_date_reg_t;
/** Group: TEE PMS CLK EN REG */
/** Type of pms_clk_en register
* NA
/** Group: Clock Gating Registers */
/** Type of hp2lp_peri_pms_clk_en register
* Clock gating register
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 1;
* NA
/** hp2lp_peri_pms_clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: Enable automatic clock gating
* 1: Keep the clock always on
*/
uint32_t reg_clk_en:1;
uint32_t hp2lp_peri_pms_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} tee_pms_clk_en_reg_t;
} pms_hp2lp_peri_pms_clk_en_reg_t;
/** Group: TEE HP CORE0 MM PMS REG0 REG */
/** Type of hp_core0_mm_pms_reg0 register
* NA
/** Group: HP CPU Permission Control Registers */
/** Type of hp_coren_mm_pms_reg0 register
* Permission control register0 for HP CPUn in machine mode
*/
typedef union {
struct {
/** reg_hp_core0_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
/** hp_coren_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP System
* Registers.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_sysreg_allow:1;
/** reg_hp_core0_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
uint32_t hp_coren_mm_lp_sysreg_allow:1;
/** hp_coren_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP_AONCLKRST.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_aonclkrst_allow:1;
/** reg_hp_core0_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
uint32_t hp_coren_mm_lp_aonclkrst_allow:1;
/** hp_coren_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP timer.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_timer_allow:1;
/** reg_hp_core0_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
uint32_t hp_coren_mm_lp_timer_allow:1;
/** hp_coren_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP ANAPERI.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_anaperi_allow:1;
/** reg_hp_core0_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
uint32_t hp_coren_mm_lp_anaperi_allow:1;
/** hp_coren_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP PMU.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_pmu_allow:1;
/** reg_hp_core0_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
uint32_t hp_coren_mm_lp_pmu_allow:1;
/** hp_coren_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP WDT.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_wdt_allow:1;
/** reg_hp_core0_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
uint32_t hp_coren_mm_lp_wdt_allow:1;
/** hp_coren_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP Mailbox
* Controller.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_mailbox_allow:1;
/** reg_hp_core0_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
uint32_t hp_coren_mm_lp_mailbox_allow:1;
/** hp_coren_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP RTC.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core0_mm_lp_rtc_allow:1;
/** reg_hp_core0_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
uint32_t hp_coren_mm_lp_rtc_allow:1;
/** hp_coren_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP PERICLKRST.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_periclkrst_allow:1;
/** reg_hp_core0_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
uint32_t hp_coren_mm_lp_periclkrst_allow:1;
/** hp_coren_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP UART.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_uart_allow:1;
/** reg_hp_core0_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
uint32_t hp_coren_mm_lp_uart_allow:1;
/** hp_coren_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP I2C.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_i2c_allow:1;
/** reg_hp_core0_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
uint32_t hp_coren_mm_lp_i2c_allow:1;
/** hp_coren_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP SPI.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_spi_allow:1;
/** reg_hp_core0_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
uint32_t hp_coren_mm_lp_spi_allow:1;
/** hp_coren_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP I2C master.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_i2cmst_allow:1;
/** reg_hp_core0_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
uint32_t hp_coren_mm_lp_i2cmst_allow:1;
/** hp_coren_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP I2S.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_i2s_allow:1;
/** reg_hp_core0_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
uint32_t hp_coren_mm_lp_i2s_allow:1;
/** hp_coren_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP ADC.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_adc_allow:1;
/** reg_hp_core0_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
uint32_t hp_coren_mm_lp_adc_allow:1;
/** hp_coren_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP touch
* sensor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_touch_allow:1;
/** reg_hp_core0_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
uint32_t hp_coren_mm_lp_touch_allow:1;
/** hp_coren_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP IO MUX.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_iomux_allow:1;
/** reg_hp_core0_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
uint32_t hp_coren_mm_lp_iomux_allow:1;
/** hp_coren_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP INTR.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_intr_allow:1;
/** reg_hp_core0_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
uint32_t hp_coren_mm_lp_intr_allow:1;
/** hp_coren_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP eFuse.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_efuse_allow:1;
/** reg_hp_core0_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
uint32_t hp_coren_mm_lp_efuse_allow:1;
/** hp_coren_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access
* LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_pms_allow:1;
/** reg_hp_core0_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
uint32_t hp_coren_mm_lp_pms_allow:1;
/** hp_coren_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access
* HP2LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_hp2lp_pms_allow:1;
/** reg_hp_core0_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
uint32_t hp_coren_mm_hp2lp_pms_allow:1;
/** hp_coren_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP temperature
* sensor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_tsens_allow:1;
/** reg_hp_core0_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
uint32_t hp_coren_mm_lp_tsens_allow:1;
/** hp_coren_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* Configures whether HP CPUn in machine mode has permission to LP HUK.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_huk_allow:1;
/** reg_hp_core0_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
uint32_t hp_coren_mm_lp_huk_allow:1;
/** hp_coren_mm_lp_sram_allow : R/W; bitpos: [23]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP SRAM.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_tcm_ram_allow:1;
/** reg_hp_core0_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1;
* NA
uint32_t hp_coren_mm_lp_sram_allow:1;
/** hp_coren_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP RNG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_mm_lp_trng_allow:1;
uint32_t hp_coren_mm_lp_trng_allow:1;
uint32_t reserved_25:7;
};
uint32_t val;
} tee_hp_core0_mm_pms_reg0_reg_t;
} pms_hp_coren_mm_pms_reg0_reg_t;
/** Group: TEE HP CORE0 UM PMS REG0 REG */
/** Type of hp_core0_um_pms_reg0 register
* NA
/** Type of hp_coren_um_pms_reg0 register
* Permission control register0 for HP CPUn in user mode
*/
typedef union {
struct {
/** reg_hp_core0_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
/** hp_coren_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP System
* Registers.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_sysreg_allow:1;
/** reg_hp_core0_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
uint32_t hp_coren_um_lp_sysreg_allow:1;
/** hp_coren_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP_AONCLKRST.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_aonclkrst_allow:1;
/** reg_hp_core0_um_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
uint32_t hp_coren_um_lp_aonclkrst_allow:1;
/** hp_coren_um_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP timer.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_timer_allow:1;
/** reg_hp_core0_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
uint32_t hp_coren_um_lp_timer_allow:1;
/** hp_coren_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP ANAPERI.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_anaperi_allow:1;
/** reg_hp_core0_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
uint32_t hp_coren_um_lp_anaperi_allow:1;
/** hp_coren_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP PMU.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_pmu_allow:1;
/** reg_hp_core0_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
uint32_t hp_coren_um_lp_pmu_allow:1;
/** hp_coren_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP WDT.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_wdt_allow:1;
/** reg_hp_core0_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
uint32_t hp_coren_um_lp_wdt_allow:1;
/** hp_coren_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP Mailbox
* Controller.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_mailbox_allow:1;
/** reg_hp_core0_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
uint32_t hp_coren_um_lp_mailbox_allow:1;
/** hp_coren_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP RTC.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core0_um_lp_rtc_allow:1;
/** reg_hp_core0_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
uint32_t hp_coren_um_lp_rtc_allow:1;
/** hp_coren_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP PERICLKRST.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_periclkrst_allow:1;
/** reg_hp_core0_um_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
uint32_t hp_coren_um_lp_periclkrst_allow:1;
/** hp_coren_um_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP UART.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_uart_allow:1;
/** reg_hp_core0_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
uint32_t hp_coren_um_lp_uart_allow:1;
/** hp_coren_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP I2C.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_i2c_allow:1;
/** reg_hp_core0_um_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
uint32_t hp_coren_um_lp_i2c_allow:1;
/** hp_coren_um_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP SPI.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_spi_allow:1;
/** reg_hp_core0_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
uint32_t hp_coren_um_lp_spi_allow:1;
/** hp_coren_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP I2C master.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_i2cmst_allow:1;
/** reg_hp_core0_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
uint32_t hp_coren_um_lp_i2cmst_allow:1;
/** hp_coren_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP I2S.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_i2s_allow:1;
/** reg_hp_core0_um_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
uint32_t hp_coren_um_lp_i2s_allow:1;
/** hp_coren_um_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP ADC.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_adc_allow:1;
/** reg_hp_core0_um_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
uint32_t hp_coren_um_lp_adc_allow:1;
/** hp_coren_um_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP touch sensor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_touch_allow:1;
/** reg_hp_core0_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
uint32_t hp_coren_um_lp_touch_allow:1;
/** hp_coren_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP IO MUX.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_iomux_allow:1;
/** reg_hp_core0_um_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
uint32_t hp_coren_um_lp_iomux_allow:1;
/** hp_coren_um_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP INTR.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_intr_allow:1;
/** reg_hp_core0_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
uint32_t hp_coren_um_lp_intr_allow:1;
/** hp_coren_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP eFuse.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_efuse_allow:1;
/** reg_hp_core0_um_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
uint32_t hp_coren_um_lp_efuse_allow:1;
/** hp_coren_um_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_pms_allow:1;
/** reg_hp_core0_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
uint32_t hp_coren_um_lp_pms_allow:1;
/** hp_coren_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* Configures whether HP CPUn in user mode has permission to access
* HP2LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_hp2lp_pms_allow:1;
/** reg_hp_core0_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
uint32_t hp_coren_um_hp2lp_pms_allow:1;
/** hp_coren_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP temperature
* sensor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_tsens_allow:1;
/** reg_hp_core0_um_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
uint32_t hp_coren_um_lp_tsens_allow:1;
/** hp_coren_um_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* Configures whether HP CPUn in user mode has permission to LP HUK.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_huk_allow:1;
/** reg_hp_core0_um_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
uint32_t hp_coren_um_lp_huk_allow:1;
/** hp_coren_um_lp_sram_allow : R/W; bitpos: [23]; default: 1;
* Configures whether HP CPUn in user mode has permission to access LP SRAM.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_tcm_ram_allow:1;
/** reg_hp_core0_um_lp_trng_allow : R/W; bitpos: [24]; default: 1;
* NA
uint32_t hp_coren_um_lp_sram_allow:1;
/** hp_coren_um_lp_trng_allow : R/W; bitpos: [24]; default: 1;
* Configures whether HP CPUn in machine mode has permission to access LP RNG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_hp_core0_um_lp_trng_allow:1;
uint32_t hp_coren_um_lp_trng_allow:1;
uint32_t reserved_25:7;
};
uint32_t val;
} tee_hp_core0_um_pms_reg0_reg_t;
} pms_hp_coren_um_pms_reg0_reg_t;
/** Group: TEE HP CORE1 MM PMS REG0 REG */
/** Type of hp_core1_mm_pms_reg0 register
* NA
/** Group: TEE Peripheral Permission Control Register */
/** Type of regdma_lp_peri_pms register
* LP Peripheral Permission register for REGDMA
*/
typedef union {
struct {
/** reg_hp_core1_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
/** regdma_peri_lp_sram_allow : R/W; bitpos: [0]; default: 1;
* Configures whether REGDMA has permission to access LP SRAM.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core1_mm_lp_sysreg_allow:1;
/** reg_hp_core1_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
uint32_t regdma_peri_lp_sram_allow:1;
/** regdma_peri_lp_peri_allow : R/W; bitpos: [1]; default: 1;
* Configures whether REGDMA has permission to access all LP peripherals.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core1_mm_lp_aonclkrst_allow:1;
/** reg_hp_core1_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_timer_allow:1;
/** reg_hp_core1_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_anaperi_allow:1;
/** reg_hp_core1_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_pmu_allow:1;
/** reg_hp_core1_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_wdt_allow:1;
/** reg_hp_core1_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_mailbox_allow:1;
/** reg_hp_core1_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_rtc_allow:1;
/** reg_hp_core1_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_periclkrst_allow:1;
/** reg_hp_core1_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_uart_allow:1;
/** reg_hp_core1_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_i2c_allow:1;
/** reg_hp_core1_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_spi_allow:1;
/** reg_hp_core1_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_i2cmst_allow:1;
/** reg_hp_core1_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_i2s_allow:1;
/** reg_hp_core1_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_adc_allow:1;
/** reg_hp_core1_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_touch_allow:1;
/** reg_hp_core1_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_iomux_allow:1;
/** reg_hp_core1_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_intr_allow:1;
/** reg_hp_core1_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_efuse_allow:1;
/** reg_hp_core1_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_pms_allow:1;
/** reg_hp_core1_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_hp2lp_pms_allow:1;
/** reg_hp_core1_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_tsens_allow:1;
/** reg_hp_core1_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_huk_allow:1;
/** reg_hp_core1_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_tcm_ram_allow:1;
/** reg_hp_core1_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1;
* NA
*/
uint32_t reg_hp_core1_mm_lp_trng_allow:1;
uint32_t reserved_25:7;
};
uint32_t val;
} tee_hp_core1_mm_pms_reg0_reg_t;
/** Group: TEE HP CORE1 UM PMS REG0 REG */
/** Type of hp_core1_um_pms_reg0 register
* NA
*/
typedef union {
struct {
/** reg_hp_core1_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_sysreg_allow:1;
/** reg_hp_core1_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_aonclkrst_allow:1;
/** reg_hp_core1_um_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_timer_allow:1;
/** reg_hp_core1_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_anaperi_allow:1;
/** reg_hp_core1_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_pmu_allow:1;
/** reg_hp_core1_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_wdt_allow:1;
/** reg_hp_core1_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_mailbox_allow:1;
/** reg_hp_core1_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_rtc_allow:1;
/** reg_hp_core1_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_periclkrst_allow:1;
/** reg_hp_core1_um_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_uart_allow:1;
/** reg_hp_core1_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_i2c_allow:1;
/** reg_hp_core1_um_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_spi_allow:1;
/** reg_hp_core1_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_i2cmst_allow:1;
/** reg_hp_core1_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_i2s_allow:1;
/** reg_hp_core1_um_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_adc_allow:1;
/** reg_hp_core1_um_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_touch_allow:1;
/** reg_hp_core1_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_iomux_allow:1;
/** reg_hp_core1_um_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_intr_allow:1;
/** reg_hp_core1_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_efuse_allow:1;
/** reg_hp_core1_um_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_pms_allow:1;
/** reg_hp_core1_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_hp2lp_pms_allow:1;
/** reg_hp_core1_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_tsens_allow:1;
/** reg_hp_core1_um_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_huk_allow:1;
/** reg_hp_core1_um_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_tcm_ram_allow:1;
/** reg_hp_core1_um_lp_trng_allow : R/W; bitpos: [24]; default: 1;
* NA
*/
uint32_t reg_hp_core1_um_lp_trng_allow:1;
uint32_t reserved_25:7;
};
uint32_t val;
} tee_hp_core1_um_pms_reg0_reg_t;
/** Group: TEE REGDMA PERI PMS REG */
/** Type of regdma_peri_pms register
* NA
*/
typedef union {
struct {
/** reg_regdma_peri_lp_ram_allow : R/W; bitpos: [0]; default: 1;
* NA
*/
uint32_t reg_regdma_peri_lp_ram_allow:1;
/** reg_regdma_peri_lp_peri_allow : R/W; bitpos: [1]; default: 1;
* NA
*/
uint32_t reg_regdma_peri_lp_peri_allow:1;
uint32_t regdma_peri_lp_peri_allow:1;
uint32_t reserved_2:30;
};
uint32_t val;
} tee_regdma_peri_pms_reg_t;
} pms_regdma_lp_peri_pms_reg_t;
typedef struct {
volatile tee_hp2lp_tee_pms_date_reg_t hp2lp_tee_pms_date;
volatile tee_pms_clk_en_reg_t pms_clk_en;
volatile tee_hp_core0_mm_pms_reg0_reg_t hp_core0_mm_pms_reg0;
volatile tee_hp_core0_um_pms_reg0_reg_t hp_core0_um_pms_reg0;
volatile tee_hp_core1_mm_pms_reg0_reg_t hp_core1_mm_pms_reg0;
volatile tee_hp_core1_um_pms_reg0_reg_t hp_core1_um_pms_reg0;
volatile tee_regdma_peri_pms_reg_t regdma_peri_pms;
} tee_dev_t;
volatile pms_hp2lp_peri_pms_date_reg_t hp2lp_peri_pms_date;
volatile pms_hp2lp_peri_pms_clk_en_reg_t hp2lp_peri_pms_clk_en;
volatile pms_hp_coren_mm_pms_reg0_reg_t hp_core0_mm_pms_reg0;
volatile pms_hp_coren_um_pms_reg0_reg_t hp_core0_um_pms_reg0;
volatile pms_hp_coren_mm_pms_reg0_reg_t hp_core1_mm_pms_reg0;
volatile pms_hp_coren_um_pms_reg0_reg_t hp_core1_um_pms_reg0;
volatile pms_regdma_lp_peri_pms_reg_t regdma_lp_peri_pms;
} hp2lp_peri_pms_dev_t;
extern tee_dev_t HP2LP_PERI_PMS;
extern hp2lp_peri_pms_dev_t HP2LP_PERI_PMS;
#ifndef __cplusplus
_Static_assert(sizeof(tee_dev_t) == 0x1c, "Invalid size of tee_dev_t structure");
_Static_assert(sizeof(hp2lp_peri_pms_dev_t) == 0x1c, "Invalid size of hp2lp_peri_pms_dev_t structure");
#endif
#ifdef __cplusplus
components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_eco5_reg.h
-2231
View File
File diff suppressed because it is too large Load Diff
components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_reg.h
+87 -5
View File
@@ -14,7 +14,7 @@ extern "C" {
* Version control register
*/
#define PMS_HP_PERI_PMS_DATE_REG (DR_REG_HP_PERI_PMS_BASE + 0x0)
/** PMS_HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537;
/** PMS_HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2363943;
* Version control register.
*/
#define PMS_HP_PERI_PMS_DATE 0xFFFFFFFFU
@@ -179,6 +179,15 @@ extern "C" {
#define PMS_CORE0_MM_HP_GDMA_ALLOW_M (PMS_CORE0_MM_HP_GDMA_ALLOW_V << PMS_CORE0_MM_HP_GDMA_ALLOW_S)
#define PMS_CORE0_MM_HP_GDMA_ALLOW_V 0x00000001U
#define PMS_CORE0_MM_HP_GDMA_ALLOW_S 3
/** PMS_CORE0_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access HP REGDMA.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_CORE0_MM_HP_REGDMA_ALLOW (BIT(4))
#define PMS_CORE0_MM_HP_REGDMA_ALLOW_M (PMS_CORE0_MM_HP_REGDMA_ALLOW_V << PMS_CORE0_MM_HP_REGDMA_ALLOW_S)
#define PMS_CORE0_MM_HP_REGDMA_ALLOW_V 0x00000001U
#define PMS_CORE0_MM_HP_REGDMA_ALLOW_S 4
/** PMS_CORE0_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access HP SDMMC.
* 0: Not allowed
@@ -406,6 +415,15 @@ extern "C" {
#define PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_M (PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_V << PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_S)
#define PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_V 0x00000001U
#define PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_S 28
/** PMS_CORE0_MM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1;
* Configures whether HP CPU0 in machine mode has permission to access AXI PERFMON.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_CORE0_MM_AXI_PERF_MON_ALLOW (BIT(29))
#define PMS_CORE0_MM_AXI_PERF_MON_ALLOW_M (PMS_CORE0_MM_AXI_PERF_MON_ALLOW_V << PMS_CORE0_MM_AXI_PERF_MON_ALLOW_S)
#define PMS_CORE0_MM_AXI_PERF_MON_ALLOW_V 0x00000001U
#define PMS_CORE0_MM_AXI_PERF_MON_ALLOW_S 29
/** PMS_CORE0_MM_HP_PERI_PMS_REG2_REG register
* Permission control register2 for HP CPU0 in machine mode
@@ -877,13 +895,20 @@ extern "C" {
* Configures whether HP CPU0 in user mode has permission to access HP DW-GDMA.
* 0: Not allowed
* 1: Allowed
* 0: Not allowed
* 1: Allowed
*/
#define PMS_CORE0_UM_HP_GDMA_ALLOW (BIT(3))
#define PMS_CORE0_UM_HP_GDMA_ALLOW_M (PMS_CORE0_UM_HP_GDMA_ALLOW_V << PMS_CORE0_UM_HP_GDMA_ALLOW_S)
#define PMS_CORE0_UM_HP_GDMA_ALLOW_V 0x00000001U
#define PMS_CORE0_UM_HP_GDMA_ALLOW_S 3
/** PMS_CORE0_UM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access HP REGDMA.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_CORE0_UM_HP_REGDMA_ALLOW (BIT(4))
#define PMS_CORE0_UM_HP_REGDMA_ALLOW_M (PMS_CORE0_UM_HP_REGDMA_ALLOW_V << PMS_CORE0_UM_HP_REGDMA_ALLOW_S)
#define PMS_CORE0_UM_HP_REGDMA_ALLOW_V 0x00000001U
#define PMS_CORE0_UM_HP_REGDMA_ALLOW_S 4
/** PMS_CORE0_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access HP SDMMC.
* 0: Not allowed
@@ -1104,6 +1129,15 @@ extern "C" {
#define PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_M (PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_V << PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_S)
#define PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_V 0x00000001U
#define PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_S 28
/** PMS_CORE0_UM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1;
* Configures whether HP CPU0 in user mode has permission to access AXI PERFMON.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_CORE0_UM_AXI_PERF_MON_ALLOW (BIT(29))
#define PMS_CORE0_UM_AXI_PERF_MON_ALLOW_M (PMS_CORE0_UM_AXI_PERF_MON_ALLOW_V << PMS_CORE0_UM_AXI_PERF_MON_ALLOW_S)
#define PMS_CORE0_UM_AXI_PERF_MON_ALLOW_V 0x00000001U
#define PMS_CORE0_UM_AXI_PERF_MON_ALLOW_S 29
/** PMS_CORE0_UM_HP_PERI_PMS_REG2_REG register
* Permission control register2 for HP CPU0 in user mode
@@ -1578,6 +1612,15 @@ extern "C" {
#define PMS_CORE1_MM_HP_GDMA_ALLOW_M (PMS_CORE1_MM_HP_GDMA_ALLOW_V << PMS_CORE1_MM_HP_GDMA_ALLOW_S)
#define PMS_CORE1_MM_HP_GDMA_ALLOW_V 0x00000001U
#define PMS_CORE1_MM_HP_GDMA_ALLOW_S 3
/** PMS_CORE1_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access HP REGDMA.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_CORE1_MM_HP_REGDMA_ALLOW (BIT(4))
#define PMS_CORE1_MM_HP_REGDMA_ALLOW_M (PMS_CORE1_MM_HP_REGDMA_ALLOW_V << PMS_CORE1_MM_HP_REGDMA_ALLOW_S)
#define PMS_CORE1_MM_HP_REGDMA_ALLOW_V 0x00000001U
#define PMS_CORE1_MM_HP_REGDMA_ALLOW_S 4
/** PMS_CORE1_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access HP SDMMC.
* 0: Not allowed
@@ -1805,6 +1848,15 @@ extern "C" {
#define PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_M (PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_V << PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_S)
#define PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_V 0x00000001U
#define PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_S 28
/** PMS_CORE1_MM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1;
* Configures whether HP CPU1 in machine mode has permission to access AXI PERFMON.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_CORE1_MM_AXI_PERF_MON_ALLOW (BIT(29))
#define PMS_CORE1_MM_AXI_PERF_MON_ALLOW_M (PMS_CORE1_MM_AXI_PERF_MON_ALLOW_V << PMS_CORE1_MM_AXI_PERF_MON_ALLOW_S)
#define PMS_CORE1_MM_AXI_PERF_MON_ALLOW_V 0x00000001U
#define PMS_CORE1_MM_AXI_PERF_MON_ALLOW_S 29
/** PMS_CORE1_MM_HP_PERI_PMS_REG2_REG register
* Permission control register2 for HP CPU1 in machine mode
@@ -2276,13 +2328,20 @@ extern "C" {
* Configures whether HP CPU1 in user mode has permission to access HP DW-GDMA.
* 0: Not allowed
* 1: Allowed
* 0: Not allowed
* 1: Allowed
*/
#define PMS_CORE1_UM_HP_GDMA_ALLOW (BIT(3))
#define PMS_CORE1_UM_HP_GDMA_ALLOW_M (PMS_CORE1_UM_HP_GDMA_ALLOW_V << PMS_CORE1_UM_HP_GDMA_ALLOW_S)
#define PMS_CORE1_UM_HP_GDMA_ALLOW_V 0x00000001U
#define PMS_CORE1_UM_HP_GDMA_ALLOW_S 3
/** PMS_CORE1_UM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access HP REGDMA.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_CORE1_UM_HP_REGDMA_ALLOW (BIT(4))
#define PMS_CORE1_UM_HP_REGDMA_ALLOW_M (PMS_CORE1_UM_HP_REGDMA_ALLOW_V << PMS_CORE1_UM_HP_REGDMA_ALLOW_S)
#define PMS_CORE1_UM_HP_REGDMA_ALLOW_V 0x00000001U
#define PMS_CORE1_UM_HP_REGDMA_ALLOW_S 4
/** PMS_CORE1_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access HP SDMMC.
* 0: Not allowed
@@ -2503,6 +2562,15 @@ extern "C" {
#define PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_M (PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_V << PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_S)
#define PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_V 0x00000001U
#define PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_S 28
/** PMS_CORE1_UM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1;
* Configures whether HP CPU1 in user mode has permission to access AXI PERFMON.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_CORE1_UM_AXI_PERF_MON_ALLOW (BIT(29))
#define PMS_CORE1_UM_AXI_PERF_MON_ALLOW_M (PMS_CORE1_UM_AXI_PERF_MON_ALLOW_V << PMS_CORE1_UM_AXI_PERF_MON_ALLOW_S)
#define PMS_CORE1_UM_AXI_PERF_MON_ALLOW_V 0x00000001U
#define PMS_CORE1_UM_AXI_PERF_MON_ALLOW_S 29
/** PMS_CORE1_UM_HP_PERI_PMS_REG2_REG register
* Permission control register2 for HP CPU1 in user mode
@@ -2834,6 +2902,20 @@ extern "C" {
#define PMS_CORE1_UM_HP_CLKRST_ALLOW_V 0x00000001U
#define PMS_CORE1_UM_HP_CLKRST_ALLOW_S 4
/** PMS_REGDMA_HP_PERI_PMS_REG register
* HP Peripheral Permission register for REGDMA
*/
#define PMS_REGDMA_HP_PERI_PMS_REG (DR_REG_HP_PERI_PMS_BASE + 0x48)
/** PMS_REGDMA_PERI_HP_PERI_ALLOW : R/W; bitpos: [0]; default: 1;
* Configures whether REGDMA has permission to access all HP peripherals.
* 0: Not allowed
* 1: Allow
*/
#define PMS_REGDMA_PERI_HP_PERI_ALLOW (BIT(0))
#define PMS_REGDMA_PERI_HP_PERI_ALLOW_M (PMS_REGDMA_PERI_HP_PERI_ALLOW_V << PMS_REGDMA_PERI_HP_PERI_ALLOW_S)
#define PMS_REGDMA_PERI_HP_PERI_ALLOW_V 0x00000001U
#define PMS_REGDMA_PERI_HP_PERI_ALLOW_S 0
#ifdef __cplusplus
}
#endif
components/soc/esp32p4/register/hw_ver3/soc/hp_peri_pms_struct.h
+859 -1236
View File
File diff suppressed because it is too large Load Diff
components/soc/esp32p4/register/hw_ver3/soc/icm_sys_reg.h
+19 -19
View File
@@ -13,7 +13,7 @@ extern "C" {
/** ICM_VER_DATE_REG register
* NA
*/
#define ICM_VER_DATE_REG (DR_REG_ICM_BASE + 0x0)
#define ICM_VER_DATE_REG (DR_REG_AXI_ICM_BASE + 0x0)
/** ICM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539165204;
* NA
*/
@@ -25,7 +25,7 @@ extern "C" {
/** ICM_CLK_EN_REG register
* NA
*/
#define ICM_CLK_EN_REG (DR_REG_ICM_BASE + 0x4)
#define ICM_CLK_EN_REG (DR_REG_AXI_ICM_BASE + 0x4)
/** ICM_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
* NA
*/
@@ -37,7 +37,7 @@ extern "C" {
/** ICM_DLOCK_STATUS_REG register
* NA
*/
#define ICM_DLOCK_STATUS_REG (DR_REG_ICM_BASE + 0x8)
#define ICM_DLOCK_STATUS_REG (DR_REG_AXI_ICM_BASE + 0x8)
/** ICM_REG_DLOCK_MST : RO; bitpos: [3:0]; default: 0;
* Lowest numbered deadlocked master
*/
@@ -70,7 +70,7 @@ extern "C" {
/** ICM_INT_RAW_REG register
* NA
*/
#define ICM_INT_RAW_REG (DR_REG_ICM_BASE + 0xc)
#define ICM_INT_RAW_REG (DR_REG_AXI_ICM_BASE + 0xc)
/** ICM_REG_DLOCK_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* NA
*/
@@ -96,7 +96,7 @@ extern "C" {
/** ICM_INT_ST_REG register
* NA
*/
#define ICM_INT_ST_REG (DR_REG_ICM_BASE + 0x10)
#define ICM_INT_ST_REG (DR_REG_AXI_ICM_BASE + 0x10)
/** ICM_REG_DLOCK_INT_ST : RO; bitpos: [0]; default: 0;
* NA
*/
@@ -122,7 +122,7 @@ extern "C" {
/** ICM_INT_ENA_REG register
* NA
*/
#define ICM_INT_ENA_REG (DR_REG_ICM_BASE + 0x14)
#define ICM_INT_ENA_REG (DR_REG_AXI_ICM_BASE + 0x14)
/** ICM_REG_DLOCK_INT_ENA : R/W; bitpos: [0]; default: 1;
* NA
*/
@@ -148,7 +148,7 @@ extern "C" {
/** ICM_INT_CLR_REG register
* NA
*/
#define ICM_INT_CLR_REG (DR_REG_ICM_BASE + 0x18)
#define ICM_INT_CLR_REG (DR_REG_AXI_ICM_BASE + 0x18)
/** ICM_REG_DLOCK_INT_CLR : WT; bitpos: [0]; default: 0;
* NA
*/
@@ -174,7 +174,7 @@ extern "C" {
/** ICM_MST_ARB_PRIORITY_REG0_REG register
* NA
*/
#define ICM_MST_ARB_PRIORITY_REG0_REG (DR_REG_ICM_BASE + 0x1c)
#define ICM_MST_ARB_PRIORITY_REG0_REG (DR_REG_AXI_ICM_BASE + 0x1c)
/** ICM_REG_CPU_PRIORITY : R/W; bitpos: [3:0]; default: 0;
* CPU arbitration priority for command channels between masters connected to sys_icm
*/
@@ -240,7 +240,7 @@ extern "C" {
/** ICM_SLV_ARB_PRIORITY_REG register
* NA
*/
#define ICM_SLV_ARB_PRIORITY_REG (DR_REG_ICM_BASE + 0x24)
#define ICM_SLV_ARB_PRIORITY_REG (DR_REG_AXI_ICM_BASE + 0x24)
/** ICM_REG_L2MEM_PRIORITY : R/W; bitpos: [5:3]; default: 0;
* L2MEM arbitration priority for response channels between slaves connected to sys_icm
*/
@@ -284,7 +284,7 @@ extern "C" {
/** ICM_MST_ARQOS_REG0_REG register
* NA
*/
#define ICM_MST_ARQOS_REG0_REG (DR_REG_ICM_BASE + 0x28)
#define ICM_MST_ARQOS_REG0_REG (DR_REG_AXI_ICM_BASE + 0x28)
/** ICM_REG_CPU_ARQOS : R/W; bitpos: [3:0]; default: 0;
* NA
*/
@@ -345,7 +345,7 @@ extern "C" {
/** ICM_MST_AWQOS_REG0_REG register
* NA
*/
#define ICM_MST_AWQOS_REG0_REG (DR_REG_ICM_BASE + 0x30)
#define ICM_MST_AWQOS_REG0_REG (DR_REG_AXI_ICM_BASE + 0x30)
/** ICM_REG_CPU_AWQOS : R/W; bitpos: [3:0]; default: 0;
* NA
*/
@@ -406,7 +406,7 @@ extern "C" {
/** ICM_SYS_ADDRHOLE_ADDR_REG register
* icm sys addr hole address registers
*/
#define ICM_SYS_ADDRHOLE_ADDR_REG (DR_REG_ICM_BASE + 0x38)
#define ICM_SYS_ADDRHOLE_ADDR_REG (DR_REG_AXI_ICM_BASE + 0x38)
/** ICM_REG_ICM_SYS_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
* NA
*/
@@ -418,7 +418,7 @@ extern "C" {
/** ICM_SYS_ADDRHOLE_INFO_REG register
* NA
*/
#define ICM_SYS_ADDRHOLE_INFO_REG (DR_REG_ICM_BASE + 0x3c)
#define ICM_SYS_ADDRHOLE_INFO_REG (DR_REG_AXI_ICM_BASE + 0x3c)
/** ICM_REG_ICM_SYS_ADDRHOLE_ID : RO; bitpos: [7:0]; default: 0;
* master id = 4-bit CID + 4-bit UID(refer to related IP) . CID is used to verify
* master in icm. CID: 4'h1: cache, 4'h5 gdma mst1, 4'h6: gdma mst2, 4'h8: axi pdma,
@@ -447,7 +447,7 @@ extern "C" {
/** ICM_CPU_ADDRHOLE_ADDR_REG register
* icm cpu addr hole address registers
*/
#define ICM_CPU_ADDRHOLE_ADDR_REG (DR_REG_ICM_BASE + 0x40)
#define ICM_CPU_ADDRHOLE_ADDR_REG (DR_REG_AXI_ICM_BASE + 0x40)
/** ICM_REG_ICM_CPU_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
* It is illegall access address if reg_icm_cpu_addrhole_secure is 1. Otherwise, it
* the address without permission to access.
@@ -460,7 +460,7 @@ extern "C" {
/** ICM_CPU_ADDRHOLE_INFO_REG register
* NA
*/
#define ICM_CPU_ADDRHOLE_INFO_REG (DR_REG_ICM_BASE + 0x44)
#define ICM_CPU_ADDRHOLE_INFO_REG (DR_REG_AXI_ICM_BASE + 0x44)
/** ICM_REG_ICM_CPU_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0;
* master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4:
* regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha
@@ -488,7 +488,7 @@ extern "C" {
/** ICM_DLOCK_TIMEOUT_REG register
* NA
*/
#define ICM_DLOCK_TIMEOUT_REG (DR_REG_ICM_BASE + 0x48)
#define ICM_DLOCK_TIMEOUT_REG (DR_REG_AXI_ICM_BASE + 0x48)
/** ICM_REG_DLOCK_TIMEOUT : R/W; bitpos: [12:0]; default: 2048;
* if no response until reg_dlock_timeout bus clock cycle, deadlock will happen
*/
@@ -500,7 +500,7 @@ extern "C" {
/** ICM_RDN_ECO_CS_REG register
* NA
*/
#define ICM_RDN_ECO_CS_REG (DR_REG_ICM_BASE + 0x50)
#define ICM_RDN_ECO_CS_REG (DR_REG_AXI_ICM_BASE + 0x50)
/** ICM_REG_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
* NA
*/
@@ -519,7 +519,7 @@ extern "C" {
/** ICM_RDN_ECO_LOW_REG register
* NA
*/
#define ICM_RDN_ECO_LOW_REG (DR_REG_ICM_BASE + 0x54)
#define ICM_RDN_ECO_LOW_REG (DR_REG_AXI_ICM_BASE + 0x54)
/** ICM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
* NA
*/
@@ -531,7 +531,7 @@ extern "C" {
/** ICM_RDN_ECO_HIGH_REG register
* NA
*/
#define ICM_RDN_ECO_HIGH_REG (DR_REG_ICM_BASE + 0x58)
#define ICM_RDN_ECO_HIGH_REG (DR_REG_AXI_ICM_BASE + 0x58)
/** ICM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
* NA
*/
components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_eco5_reg.h
-584
View File
@@ -1,584 +0,0 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TEE_LP2HP_PMS_DATE_REG register
* NA
*/
#define TEE_LP2HP_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943;
* NA
*/
#define TEE_TEE_DATE 0xFFFFFFFFU
#define TEE_TEE_DATE_M (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
#define TEE_TEE_DATE_V 0xFFFFFFFFU
#define TEE_TEE_DATE_S 0
/** TEE_PMS_CLK_EN_REG register
* NA
*/
#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_CLK_EN (BIT(0))
#define TEE_REG_CLK_EN_M (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
#define TEE_REG_CLK_EN_V 0x00000001U
#define TEE_REG_CLK_EN_S 0
/** TEE_LP_MM_PMS_REG0_REG register
* NA
*/
#define TEE_LP_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
/** TEE_REG_LP_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_PSRAM_ALLOW (BIT(0))
#define TEE_REG_LP_MM_PSRAM_ALLOW_M (TEE_REG_LP_MM_PSRAM_ALLOW_V << TEE_REG_LP_MM_PSRAM_ALLOW_S)
#define TEE_REG_LP_MM_PSRAM_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_PSRAM_ALLOW_S 0
/** TEE_REG_LP_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_FLASH_ALLOW (BIT(1))
#define TEE_REG_LP_MM_FLASH_ALLOW_M (TEE_REG_LP_MM_FLASH_ALLOW_V << TEE_REG_LP_MM_FLASH_ALLOW_S)
#define TEE_REG_LP_MM_FLASH_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_FLASH_ALLOW_S 1
/** TEE_REG_LP_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_L2MEM_ALLOW (BIT(2))
#define TEE_REG_LP_MM_L2MEM_ALLOW_M (TEE_REG_LP_MM_L2MEM_ALLOW_V << TEE_REG_LP_MM_L2MEM_ALLOW_S)
#define TEE_REG_LP_MM_L2MEM_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_L2MEM_ALLOW_S 2
/** TEE_REG_LP_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_L2ROM_ALLOW (BIT(3))
#define TEE_REG_LP_MM_L2ROM_ALLOW_M (TEE_REG_LP_MM_L2ROM_ALLOW_V << TEE_REG_LP_MM_L2ROM_ALLOW_S)
#define TEE_REG_LP_MM_L2ROM_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_L2ROM_ALLOW_S 3
/** TEE_REG_LP_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_TRACE0_ALLOW (BIT(6))
#define TEE_REG_LP_MM_TRACE0_ALLOW_M (TEE_REG_LP_MM_TRACE0_ALLOW_V << TEE_REG_LP_MM_TRACE0_ALLOW_S)
#define TEE_REG_LP_MM_TRACE0_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_TRACE0_ALLOW_S 6
/** TEE_REG_LP_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_TRACE1_ALLOW (BIT(7))
#define TEE_REG_LP_MM_TRACE1_ALLOW_M (TEE_REG_LP_MM_TRACE1_ALLOW_V << TEE_REG_LP_MM_TRACE1_ALLOW_S)
#define TEE_REG_LP_MM_TRACE1_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_TRACE1_ALLOW_S 7
/** TEE_REG_LP_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW (BIT(8))
#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_M (TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_V << TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_S)
#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_CPU_BUS_MON_ALLOW_S 8
/** TEE_REG_LP_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_L2MEM_MON_ALLOW (BIT(9))
#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_M (TEE_REG_LP_MM_L2MEM_MON_ALLOW_V << TEE_REG_LP_MM_L2MEM_MON_ALLOW_S)
#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_L2MEM_MON_ALLOW_S 9
/** TEE_REG_LP_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_TCM_MON_ALLOW (BIT(10))
#define TEE_REG_LP_MM_TCM_MON_ALLOW_M (TEE_REG_LP_MM_TCM_MON_ALLOW_V << TEE_REG_LP_MM_TCM_MON_ALLOW_S)
#define TEE_REG_LP_MM_TCM_MON_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_TCM_MON_ALLOW_S 10
/** TEE_REG_LP_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_CACHE_ALLOW (BIT(11))
#define TEE_REG_LP_MM_CACHE_ALLOW_M (TEE_REG_LP_MM_CACHE_ALLOW_V << TEE_REG_LP_MM_CACHE_ALLOW_S)
#define TEE_REG_LP_MM_CACHE_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_CACHE_ALLOW_S 11
/** TEE_LP_MM_PMS_REG1_REG register
* NA
*/
#define TEE_LP_MM_PMS_REG1_REG (DR_REG_TEE_BASE + 0x30)
/** TEE_REG_LP_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_USBOTG_ALLOW (BIT(0))
#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_M (TEE_REG_LP_MM_HP_USBOTG_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG_ALLOW_S)
#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_USBOTG_ALLOW_S 0
/** TEE_REG_LP_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW (BIT(1))
#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_M (TEE_REG_LP_MM_HP_USBOTG11_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG11_ALLOW_S)
#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_USBOTG11_ALLOW_S 1
/** TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW (BIT(2))
#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_M (TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_S)
#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_USBOTG11_WRAP_ALLOW_S 2
/** TEE_REG_LP_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_GDMA_ALLOW (BIT(3))
#define TEE_REG_LP_MM_HP_GDMA_ALLOW_M (TEE_REG_LP_MM_HP_GDMA_ALLOW_V << TEE_REG_LP_MM_HP_GDMA_ALLOW_S)
#define TEE_REG_LP_MM_HP_GDMA_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_GDMA_ALLOW_S 3
/** TEE_REG_LP_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_REGDMA_ALLOW (BIT(4))
#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_M (TEE_REG_LP_MM_HP_REGDMA_ALLOW_V << TEE_REG_LP_MM_HP_REGDMA_ALLOW_S)
#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_REGDMA_ALLOW_S 4
/** TEE_REG_LP_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_SDMMC_ALLOW (BIT(5))
#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_M (TEE_REG_LP_MM_HP_SDMMC_ALLOW_V << TEE_REG_LP_MM_HP_SDMMC_ALLOW_S)
#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_SDMMC_ALLOW_S 5
/** TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW (BIT(6))
#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_M (TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_V << TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_S)
#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_AHB_PDMA_ALLOW_S 6
/** TEE_REG_LP_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_JPEG_ALLOW (BIT(7))
#define TEE_REG_LP_MM_HP_JPEG_ALLOW_M (TEE_REG_LP_MM_HP_JPEG_ALLOW_V << TEE_REG_LP_MM_HP_JPEG_ALLOW_S)
#define TEE_REG_LP_MM_HP_JPEG_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_JPEG_ALLOW_S 7
/** TEE_REG_LP_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_PPA_ALLOW (BIT(8))
#define TEE_REG_LP_MM_HP_PPA_ALLOW_M (TEE_REG_LP_MM_HP_PPA_ALLOW_V << TEE_REG_LP_MM_HP_PPA_ALLOW_S)
#define TEE_REG_LP_MM_HP_PPA_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_PPA_ALLOW_S 8
/** TEE_REG_LP_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_DMA2D_ALLOW (BIT(9))
#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_M (TEE_REG_LP_MM_HP_DMA2D_ALLOW_V << TEE_REG_LP_MM_HP_DMA2D_ALLOW_S)
#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_DMA2D_ALLOW_S 9
/** TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW (BIT(10))
#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_M (TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_S)
#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_KEY_MANAGER_ALLOW_S 10
/** TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW (BIT(11))
#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_M (TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_V << TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_S)
#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_AXI_PDMA_ALLOW_S 11
/** TEE_REG_LP_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_FLASH_ALLOW (BIT(12))
#define TEE_REG_LP_MM_HP_FLASH_ALLOW_M (TEE_REG_LP_MM_HP_FLASH_ALLOW_V << TEE_REG_LP_MM_HP_FLASH_ALLOW_S)
#define TEE_REG_LP_MM_HP_FLASH_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_FLASH_ALLOW_S 12
/** TEE_REG_LP_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_PSRAM_ALLOW (BIT(13))
#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_M (TEE_REG_LP_MM_HP_PSRAM_ALLOW_V << TEE_REG_LP_MM_HP_PSRAM_ALLOW_S)
#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_PSRAM_ALLOW_S 13
/** TEE_REG_LP_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW (BIT(14))
#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_M (TEE_REG_LP_MM_HP_CRYPTO_ALLOW_V << TEE_REG_LP_MM_HP_CRYPTO_ALLOW_S)
#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_CRYPTO_ALLOW_S 14
/** TEE_REG_LP_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_GMAC_ALLOW (BIT(15))
#define TEE_REG_LP_MM_HP_GMAC_ALLOW_M (TEE_REG_LP_MM_HP_GMAC_ALLOW_V << TEE_REG_LP_MM_HP_GMAC_ALLOW_S)
#define TEE_REG_LP_MM_HP_GMAC_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_GMAC_ALLOW_S 15
/** TEE_REG_LP_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW (BIT(16))
#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_M (TEE_REG_LP_MM_HP_USB_PHY_ALLOW_V << TEE_REG_LP_MM_HP_USB_PHY_ALLOW_S)
#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_USB_PHY_ALLOW_S 16
/** TEE_REG_LP_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_PVT_ALLOW (BIT(17))
#define TEE_REG_LP_MM_HP_PVT_ALLOW_M (TEE_REG_LP_MM_HP_PVT_ALLOW_V << TEE_REG_LP_MM_HP_PVT_ALLOW_S)
#define TEE_REG_LP_MM_HP_PVT_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_PVT_ALLOW_S 17
/** TEE_REG_LP_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW (BIT(18))
#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_M (TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_V << TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_S)
#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_CSI_HOST_ALLOW_S 18
/** TEE_REG_LP_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW (BIT(19))
#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_M (TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_V << TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_S)
#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_DSI_HOST_ALLOW_S 19
/** TEE_REG_LP_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_ISP_ALLOW (BIT(20))
#define TEE_REG_LP_MM_HP_ISP_ALLOW_M (TEE_REG_LP_MM_HP_ISP_ALLOW_V << TEE_REG_LP_MM_HP_ISP_ALLOW_S)
#define TEE_REG_LP_MM_HP_ISP_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_ISP_ALLOW_S 20
/** TEE_REG_LP_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW (BIT(21))
#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_M (TEE_REG_LP_MM_HP_H264_CORE_ALLOW_V << TEE_REG_LP_MM_HP_H264_CORE_ALLOW_S)
#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_H264_CORE_ALLOW_S 21
/** TEE_REG_LP_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_RMT_ALLOW (BIT(22))
#define TEE_REG_LP_MM_HP_RMT_ALLOW_M (TEE_REG_LP_MM_HP_RMT_ALLOW_V << TEE_REG_LP_MM_HP_RMT_ALLOW_S)
#define TEE_REG_LP_MM_HP_RMT_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_RMT_ALLOW_S 22
/** TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW (BIT(23))
#define TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW_M (TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW_V << TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW_S)
#define TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_BITSCRAMBLER_ALLOW_S 23
/** TEE_REG_LP_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW (BIT(24))
#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_M (TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_V << TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_S)
#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_AXI_ICM_ALLOW_S 24
/** TEE_REG_LP_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW (BIT(25))
#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_M (TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_V << TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_S)
#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_PERI_PMS_ALLOW_S 25
/** TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW (BIT(26))
#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_M (TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_S)
#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP2HP_PERI_PMS_ALLOW_S 26
/** TEE_REG_LP_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_DMA_PMS_ALLOW (BIT(27))
#define TEE_REG_LP_MM_DMA_PMS_ALLOW_M (TEE_REG_LP_MM_DMA_PMS_ALLOW_V << TEE_REG_LP_MM_DMA_PMS_ALLOW_S)
#define TEE_REG_LP_MM_DMA_PMS_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_DMA_PMS_ALLOW_S 27
/** TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW (BIT(28))
#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_M (TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_V << TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_S)
#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_H264_DMA2D_ALLOW_S 28
/** TEE_REG_LP_MM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW (BIT(29))
#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_M (TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_V << TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_S)
#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_AXI_PERF_MON_ALLOW_S 29
/** TEE_LP_MM_PMS_REG2_REG register
* NA
*/
#define TEE_LP_MM_PMS_REG2_REG (DR_REG_TEE_BASE + 0xa4)
/** TEE_REG_LP_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW (BIT(0))
#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_M (TEE_REG_LP_MM_HP_MCPWM0_ALLOW_V << TEE_REG_LP_MM_HP_MCPWM0_ALLOW_S)
#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_MCPWM0_ALLOW_S 0
/** TEE_REG_LP_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW (BIT(1))
#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_M (TEE_REG_LP_MM_HP_MCPWM1_ALLOW_V << TEE_REG_LP_MM_HP_MCPWM1_ALLOW_S)
#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_MCPWM1_ALLOW_S 1
/** TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW (BIT(2))
#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_M (TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_S)
#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_TIMER_GROUP0_ALLOW_S 2
/** TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW (BIT(3))
#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_M (TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_S)
#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_TIMER_GROUP1_ALLOW_S 3
/** TEE_REG_LP_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_I2C0_ALLOW (BIT(4))
#define TEE_REG_LP_MM_HP_I2C0_ALLOW_M (TEE_REG_LP_MM_HP_I2C0_ALLOW_V << TEE_REG_LP_MM_HP_I2C0_ALLOW_S)
#define TEE_REG_LP_MM_HP_I2C0_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_I2C0_ALLOW_S 4
/** TEE_REG_LP_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_I2C1_ALLOW (BIT(5))
#define TEE_REG_LP_MM_HP_I2C1_ALLOW_M (TEE_REG_LP_MM_HP_I2C1_ALLOW_V << TEE_REG_LP_MM_HP_I2C1_ALLOW_S)
#define TEE_REG_LP_MM_HP_I2C1_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_I2C1_ALLOW_S 5
/** TEE_REG_LP_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_I2S0_ALLOW (BIT(6))
#define TEE_REG_LP_MM_HP_I2S0_ALLOW_M (TEE_REG_LP_MM_HP_I2S0_ALLOW_V << TEE_REG_LP_MM_HP_I2S0_ALLOW_S)
#define TEE_REG_LP_MM_HP_I2S0_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_I2S0_ALLOW_S 6
/** TEE_REG_LP_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_I2S1_ALLOW (BIT(7))
#define TEE_REG_LP_MM_HP_I2S1_ALLOW_M (TEE_REG_LP_MM_HP_I2S1_ALLOW_V << TEE_REG_LP_MM_HP_I2S1_ALLOW_S)
#define TEE_REG_LP_MM_HP_I2S1_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_I2S1_ALLOW_S 7
/** TEE_REG_LP_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_I2S2_ALLOW (BIT(8))
#define TEE_REG_LP_MM_HP_I2S2_ALLOW_M (TEE_REG_LP_MM_HP_I2S2_ALLOW_V << TEE_REG_LP_MM_HP_I2S2_ALLOW_S)
#define TEE_REG_LP_MM_HP_I2S2_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_I2S2_ALLOW_S 8
/** TEE_REG_LP_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_PCNT_ALLOW (BIT(9))
#define TEE_REG_LP_MM_HP_PCNT_ALLOW_M (TEE_REG_LP_MM_HP_PCNT_ALLOW_V << TEE_REG_LP_MM_HP_PCNT_ALLOW_S)
#define TEE_REG_LP_MM_HP_PCNT_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_PCNT_ALLOW_S 9
/** TEE_REG_LP_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_UART0_ALLOW (BIT(10))
#define TEE_REG_LP_MM_HP_UART0_ALLOW_M (TEE_REG_LP_MM_HP_UART0_ALLOW_V << TEE_REG_LP_MM_HP_UART0_ALLOW_S)
#define TEE_REG_LP_MM_HP_UART0_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_UART0_ALLOW_S 10
/** TEE_REG_LP_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_UART1_ALLOW (BIT(11))
#define TEE_REG_LP_MM_HP_UART1_ALLOW_M (TEE_REG_LP_MM_HP_UART1_ALLOW_V << TEE_REG_LP_MM_HP_UART1_ALLOW_S)
#define TEE_REG_LP_MM_HP_UART1_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_UART1_ALLOW_S 11
/** TEE_REG_LP_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_UART2_ALLOW (BIT(12))
#define TEE_REG_LP_MM_HP_UART2_ALLOW_M (TEE_REG_LP_MM_HP_UART2_ALLOW_V << TEE_REG_LP_MM_HP_UART2_ALLOW_S)
#define TEE_REG_LP_MM_HP_UART2_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_UART2_ALLOW_S 12
/** TEE_REG_LP_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_UART3_ALLOW (BIT(13))
#define TEE_REG_LP_MM_HP_UART3_ALLOW_M (TEE_REG_LP_MM_HP_UART3_ALLOW_V << TEE_REG_LP_MM_HP_UART3_ALLOW_S)
#define TEE_REG_LP_MM_HP_UART3_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_UART3_ALLOW_S 13
/** TEE_REG_LP_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_UART4_ALLOW (BIT(14))
#define TEE_REG_LP_MM_HP_UART4_ALLOW_M (TEE_REG_LP_MM_HP_UART4_ALLOW_V << TEE_REG_LP_MM_HP_UART4_ALLOW_S)
#define TEE_REG_LP_MM_HP_UART4_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_UART4_ALLOW_S 14
/** TEE_REG_LP_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_PARLIO_ALLOW (BIT(15))
#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_M (TEE_REG_LP_MM_HP_PARLIO_ALLOW_V << TEE_REG_LP_MM_HP_PARLIO_ALLOW_S)
#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_PARLIO_ALLOW_S 15
/** TEE_REG_LP_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW (BIT(16))
#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_M (TEE_REG_LP_MM_HP_GPSPI2_ALLOW_V << TEE_REG_LP_MM_HP_GPSPI2_ALLOW_S)
#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_GPSPI2_ALLOW_S 16
/** TEE_REG_LP_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW (BIT(17))
#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_M (TEE_REG_LP_MM_HP_GPSPI3_ALLOW_V << TEE_REG_LP_MM_HP_GPSPI3_ALLOW_S)
#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_GPSPI3_ALLOW_S 17
/** TEE_REG_LP_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW (BIT(18))
#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_M (TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_V << TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_S)
#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_USBDEVICE_ALLOW_S 18
/** TEE_REG_LP_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_LEDC_ALLOW (BIT(19))
#define TEE_REG_LP_MM_HP_LEDC_ALLOW_M (TEE_REG_LP_MM_HP_LEDC_ALLOW_V << TEE_REG_LP_MM_HP_LEDC_ALLOW_S)
#define TEE_REG_LP_MM_HP_LEDC_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_LEDC_ALLOW_S 19
/** TEE_REG_LP_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_ETM_ALLOW (BIT(21))
#define TEE_REG_LP_MM_HP_ETM_ALLOW_M (TEE_REG_LP_MM_HP_ETM_ALLOW_V << TEE_REG_LP_MM_HP_ETM_ALLOW_S)
#define TEE_REG_LP_MM_HP_ETM_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_ETM_ALLOW_S 21
/** TEE_REG_LP_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW (BIT(22))
#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_M (TEE_REG_LP_MM_HP_INTRMTX_ALLOW_V << TEE_REG_LP_MM_HP_INTRMTX_ALLOW_S)
#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_INTRMTX_ALLOW_S 22
/** TEE_REG_LP_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_TWAI0_ALLOW (BIT(23))
#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_M (TEE_REG_LP_MM_HP_TWAI0_ALLOW_V << TEE_REG_LP_MM_HP_TWAI0_ALLOW_S)
#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_TWAI0_ALLOW_S 23
/** TEE_REG_LP_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_TWAI1_ALLOW (BIT(24))
#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_M (TEE_REG_LP_MM_HP_TWAI1_ALLOW_V << TEE_REG_LP_MM_HP_TWAI1_ALLOW_S)
#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_TWAI1_ALLOW_S 24
/** TEE_REG_LP_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_TWAI2_ALLOW (BIT(25))
#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_M (TEE_REG_LP_MM_HP_TWAI2_ALLOW_V << TEE_REG_LP_MM_HP_TWAI2_ALLOW_S)
#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_TWAI2_ALLOW_S 25
/** TEE_REG_LP_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW (BIT(26))
#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_M (TEE_REG_LP_MM_HP_I3C_MST_ALLOW_V << TEE_REG_LP_MM_HP_I3C_MST_ALLOW_S)
#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_I3C_MST_ALLOW_S 26
/** TEE_REG_LP_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW (BIT(27))
#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_M (TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_V << TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_S)
#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_I3C_SLV_ALLOW_S 27
/** TEE_REG_LP_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW (BIT(28))
#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_M (TEE_REG_LP_MM_HP_LCDCAM_ALLOW_V << TEE_REG_LP_MM_HP_LCDCAM_ALLOW_S)
#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_LCDCAM_ALLOW_S 28
/** TEE_REG_LP_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_ADC_ALLOW (BIT(30))
#define TEE_REG_LP_MM_HP_ADC_ALLOW_M (TEE_REG_LP_MM_HP_ADC_ALLOW_V << TEE_REG_LP_MM_HP_ADC_ALLOW_S)
#define TEE_REG_LP_MM_HP_ADC_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_ADC_ALLOW_S 30
/** TEE_REG_LP_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_UHCI_ALLOW (BIT(31))
#define TEE_REG_LP_MM_HP_UHCI_ALLOW_M (TEE_REG_LP_MM_HP_UHCI_ALLOW_V << TEE_REG_LP_MM_HP_UHCI_ALLOW_S)
#define TEE_REG_LP_MM_HP_UHCI_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_UHCI_ALLOW_S 31
/** TEE_LP_MM_PMS_REG3_REG register
* NA
*/
#define TEE_LP_MM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x11c)
/** TEE_REG_LP_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_GPIO_ALLOW (BIT(0))
#define TEE_REG_LP_MM_HP_GPIO_ALLOW_M (TEE_REG_LP_MM_HP_GPIO_ALLOW_V << TEE_REG_LP_MM_HP_GPIO_ALLOW_S)
#define TEE_REG_LP_MM_HP_GPIO_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_GPIO_ALLOW_S 0
/** TEE_REG_LP_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_IOMUX_ALLOW (BIT(1))
#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_M (TEE_REG_LP_MM_HP_IOMUX_ALLOW_V << TEE_REG_LP_MM_HP_IOMUX_ALLOW_S)
#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_IOMUX_ALLOW_S 1
/** TEE_REG_LP_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW (BIT(2))
#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_M (TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_V << TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_S)
#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_SYSTIMER_ALLOW_S 2
/** TEE_REG_LP_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW (BIT(3))
#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_M (TEE_REG_LP_MM_HP_SYS_REG_ALLOW_V << TEE_REG_LP_MM_HP_SYS_REG_ALLOW_S)
#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_SYS_REG_ALLOW_S 3
/** TEE_REG_LP_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP_CLKRST_ALLOW (BIT(4))
#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_M (TEE_REG_LP_MM_HP_CLKRST_ALLOW_V << TEE_REG_LP_MM_HP_CLKRST_ALLOW_S)
#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP_CLKRST_ALLOW_S 4
#ifdef __cplusplus
}
#endif
components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_reg.h
+19 -1
View File
@@ -14,7 +14,7 @@ extern "C" {
* Version control register
*/
#define PMS_LP2HP_PERI_PMS_DATE_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x0)
/** PMS_LP2HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294790;
/** PMS_LP2HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2363943;
* Version control register.
*/
#define PMS_LP2HP_PERI_PMS_DATE 0xFFFFFFFFU
@@ -180,6 +180,15 @@ extern "C" {
#define PMS_LP_MM_HP_GDMA_ALLOW_M (PMS_LP_MM_HP_GDMA_ALLOW_V << PMS_LP_MM_HP_GDMA_ALLOW_S)
#define PMS_LP_MM_HP_GDMA_ALLOW_V 0x00000001U
#define PMS_LP_MM_HP_GDMA_ALLOW_S 3
/** PMS_LP_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP REGDMA.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_LP_MM_HP_REGDMA_ALLOW (BIT(4))
#define PMS_LP_MM_HP_REGDMA_ALLOW_M (PMS_LP_MM_HP_REGDMA_ALLOW_V << PMS_LP_MM_HP_REGDMA_ALLOW_S)
#define PMS_LP_MM_HP_REGDMA_ALLOW_V 0x00000001U
#define PMS_LP_MM_HP_REGDMA_ALLOW_S 4
/** PMS_LP_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP SDMMC.
* 0: Not allowed
@@ -407,6 +416,15 @@ extern "C" {
#define PMS_LP_MM_HP_H264_DMA2D_ALLOW_M (PMS_LP_MM_HP_H264_DMA2D_ALLOW_V << PMS_LP_MM_HP_H264_DMA2D_ALLOW_S)
#define PMS_LP_MM_HP_H264_DMA2D_ALLOW_V 0x00000001U
#define PMS_LP_MM_HP_H264_DMA2D_ALLOW_S 28
/** PMS_LP_MM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access AXI-PERFMON.
* 0: Not allowed
* 1: Allowed
*/
#define PMS_LP_MM_AXI_PERF_MON_ALLOW (BIT(29))
#define PMS_LP_MM_AXI_PERF_MON_ALLOW_M (PMS_LP_MM_AXI_PERF_MON_ALLOW_V << PMS_LP_MM_AXI_PERF_MON_ALLOW_S)
#define PMS_LP_MM_AXI_PERF_MON_ALLOW_V 0x00000001U
#define PMS_LP_MM_AXI_PERF_MON_ALLOW_S 29
/** PMS_LP_MM_PMS_REG2_REG register
* Permission control register2 for the LP CPU in machine mode
components/soc/esp32p4/register/hw_ver3/soc/lp2hp_peri_pms_struct.h
+435 -264
View File
@@ -10,403 +10,574 @@
extern "C" {
#endif
/** Group: TEE LP2HP PMS DATE REG */
/** Type of lp2hp_pms_date register
* NA
/** Group: Version Control Registers */
/** Type of lp2hp_peri_pms_date register
* Version control register
*/
typedef union {
struct {
/** tee_date : R/W; bitpos: [31:0]; default: 2363943;
* NA
/** lp2hp_peri_pms_date : R/W; bitpos: [31:0]; default: 2363943;
* Version control register.
*/
uint32_t tee_date:32;
uint32_t lp2hp_peri_pms_date:32;
};
uint32_t val;
} tee_lp2hp_pms_date_reg_t;
} pms_lp2hp_peri_pms_date_reg_t;
/** Group: TEE PMS CLK EN REG */
/** Type of pms_clk_en register
* NA
/** Group: Clock Gating Registers */
/** Type of lp2hp_peri_pms_clk_en register
* Clock gating register
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 1;
* NA
/** lp2hp_peri_pms_clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: Enable automatic clock gating.
* 1: Keep the clock always on.
*/
uint32_t reg_clk_en:1;
uint32_t lp2hp_peri_pms_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} tee_pms_clk_en_reg_t;
} pms_lp2hp_peri_pms_clk_en_reg_t;
/** Group: TEE LP MM PMS REG0 REG */
/** Group: LP CPU Permission Control Registers */
/** Type of lp_mm_pms_reg0 register
* NA
* Permission control register0 for the LP CPU in machine mode
*/
typedef union {
struct {
/** reg_lp_mm_psram_allow : R/W; bitpos: [0]; default: 1;
* NA
/** lp_mm_psram_allow : R/W; bitpos: [0]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access external RAM
* without going through cache.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_psram_allow:1;
/** reg_lp_mm_flash_allow : R/W; bitpos: [1]; default: 1;
* NA
uint32_t lp_mm_psram_allow:1;
/** lp_mm_flash_allow : R/W; bitpos: [1]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access external
* flash without going through cache.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_flash_allow:1;
/** reg_lp_mm_l2mem_allow : R/W; bitpos: [2]; default: 1;
* NA
uint32_t lp_mm_flash_allow:1;
/** lp_mm_l2mem_allow : R/W; bitpos: [2]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP L2M2M
* without going through cache.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_l2mem_allow:1;
/** reg_lp_mm_l2rom_allow : R/W; bitpos: [3]; default: 1;
* NA
uint32_t lp_mm_l2mem_allow:1;
/** lp_mm_l2rom_allow : R/W; bitpos: [3]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP ROM
* without going through cache.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_l2rom_allow:1;
uint32_t lp_mm_l2rom_allow:1;
uint32_t reserved_4:2;
/** reg_lp_mm_trace0_allow : R/W; bitpos: [6]; default: 1;
* NA
/** lp_mm_trace0_allow : R/W; bitpos: [6]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access TRACE0.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_trace0_allow:1;
/** reg_lp_mm_trace1_allow : R/W; bitpos: [7]; default: 1;
* NA
uint32_t lp_mm_trace0_allow:1;
/** lp_mm_trace1_allow : R/W; bitpos: [7]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access TRACE1.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_trace1_allow:1;
/** reg_lp_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1;
* NA
uint32_t lp_mm_trace1_allow:1;
/** lp_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access CPU bus
* monitor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_cpu_bus_mon_allow:1;
/** reg_lp_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1;
* NA
uint32_t lp_mm_cpu_bus_mon_allow:1;
/** lp_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access L2MEM
* monitor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_l2mem_mon_allow:1;
/** reg_lp_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1;
* NA
uint32_t lp_mm_l2mem_mon_allow:1;
/** lp_mm_spm_mon_allow : R/W; bitpos: [10]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access SPM monitor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_tcm_mon_allow:1;
/** reg_lp_mm_cache_allow : R/W; bitpos: [11]; default: 1;
* NA
uint32_t lp_mm_spm_mon_allow:1;
/** lp_mm_cache_allow : R/W; bitpos: [11]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access cache.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_cache_allow:1;
uint32_t lp_mm_cache_allow:1;
uint32_t reserved_12:20;
};
uint32_t val;
} tee_lp_mm_pms_reg0_reg_t;
} pms_lp_mm_pms_reg0_reg_t;
/** Group: TEE LP MM PMS REG1 REG */
/** Type of lp_mm_pms_reg1 register
* NA
* Permission control register1 for the LP CPU in machine mode
*/
typedef union {
struct {
/** reg_lp_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1;
* NA
/** lp_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP
* high-speed USB 2.0 OTG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_usbotg_allow:1;
/** reg_lp_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1;
* NA
uint32_t lp_mm_hp_usbotg_allow:1;
/** lp_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP
* full-speed USB 2.0 OTG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_usbotg11_allow:1;
/** reg_lp_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1;
* NA
uint32_t lp_mm_hp_usbotg11_allow:1;
/** lp_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP
* full-speed USB 2.0 OTG's wrap.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_usbotg11_wrap_allow:1;
/** reg_lp_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1;
* NA
uint32_t lp_mm_hp_usbotg11_wrap_allow:1;
/** lp_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP DW-GDMA.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_gdma_allow:1;
/** reg_lp_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1;
* NA
uint32_t lp_mm_hp_gdma_allow:1;
uint32_t reserved_4:1;
/** lp_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP SDMMC.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_regdma_allow:1;
/** reg_lp_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
* NA
uint32_t lp_mm_hp_sdmmc_allow:1;
/** lp_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access GDMA-AHB.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_sdmmc_allow:1;
/** reg_lp_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1;
* NA
uint32_t lp_mm_hp_ahb_pdma_allow:1;
/** lp_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP JPEG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_ahb_pdma_allow:1;
/** reg_lp_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1;
* NA
uint32_t lp_mm_hp_jpeg_allow:1;
/** lp_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP PPA.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_jpeg_allow:1;
/** reg_lp_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1;
* NA
uint32_t lp_mm_hp_ppa_allow:1;
/** lp_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP 2D-DMA.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_ppa_allow:1;
/** reg_lp_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1;
* NA
uint32_t lp_mm_hp_dma2d_allow:1;
/** lp_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP key
* manager.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_dma2d_allow:1;
/** reg_lp_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1;
* NA
uint32_t lp_mm_hp_key_manager_allow:1;
/** lp_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP GDMA-AXI.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_key_manager_allow:1;
/** reg_lp_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1;
* NA
uint32_t lp_mm_hp_axi_pdma_allow:1;
/** lp_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP flash
* MSPI controller.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_axi_pdma_allow:1;
/** reg_lp_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1;
* NA
uint32_t lp_mm_hp_flash_allow:1;
/** lp_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP PSRAM
* MSPI controller.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_flash_allow:1;
/** reg_lp_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1;
* NA
uint32_t lp_mm_hp_psram_allow:1;
/** lp_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP CRYPTO.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_psram_allow:1;
/** reg_lp_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1;
* NA
uint32_t lp_mm_hp_crypto_allow:1;
/** lp_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP EMAC.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_crypto_allow:1;
/** reg_lp_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1;
* NA
uint32_t lp_mm_hp_gmac_allow:1;
/** lp_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP
* high-speed USB 2.0 OTG PHY.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_gmac_allow:1;
/** reg_lp_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1;
* NA
uint32_t lp_mm_hp_usb_phy_allow:1;
/** lp_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP PVT.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_lp_mm_hp_usb_phy_allow:1;
/** reg_lp_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1;
* NA
uint32_t lp_mm_hp_pvt_allow:1;
/** lp_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP MIPI CSI
* host.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_pvt_allow:1;
/** reg_lp_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1;
* NA
uint32_t lp_mm_hp_csi_host_allow:1;
/** lp_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP MIPI DSI
* host.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_csi_host_allow:1;
/** reg_lp_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1;
* NA
uint32_t lp_mm_hp_dsi_host_allow:1;
/** lp_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP ISP.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_dsi_host_allow:1;
/** reg_lp_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1;
* NA
uint32_t lp_mm_hp_isp_allow:1;
/** lp_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP H264
* Encoder.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_isp_allow:1;
/** reg_lp_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1;
* NA
uint32_t lp_mm_hp_h264_core_allow:1;
/** lp_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP RMT.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_h264_core_allow:1;
/** reg_lp_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1;
* NA
uint32_t lp_mm_hp_rmt_allow:1;
/** lp_mm_hp_bitscrambler_allow : R/W; bitpos: [23]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP bit
* scrambler.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_rmt_allow:1;
/** reg_lp_mm_hp_bitscrambler_allow : R/W; bitpos: [23]; default: 1;
* NA
uint32_t lp_mm_hp_bitscrambler_allow:1;
/** lp_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP AXI ICM.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_bitscrambler_allow:1;
/** reg_lp_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1;
* NA
uint32_t lp_mm_hp_axi_icm_allow:1;
/** lp_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access
* HP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_axi_icm_allow:1;
/** reg_lp_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1;
* NA
uint32_t lp_mm_hp_peri_pms_allow:1;
/** lp_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access
* LP2HP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_peri_pms_allow:1;
/** reg_lp_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1;
* NA
uint32_t lp_mm_lp2hp_peri_pms_allow:1;
/** lp_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access
* HP_DMA_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp2hp_peri_pms_allow:1;
/** reg_lp_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1;
* NA
uint32_t lp_mm_dma_pms_allow:1;
/** lp_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access 2D-DMA.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_dma_pms_allow:1;
/** reg_lp_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1;
* NA
uint32_t lp_mm_hp_h264_dma2d_allow:1;
/** lp_mm_hp_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access AXI PERFMON.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_h264_dma2d_allow:1;
/** reg_lp_mm_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1;
* NA
*/
uint32_t reg_lp_mm_axi_perf_mon_allow:1;
uint32_t lp_mm_hp_axi_perf_mon_allow:1;
uint32_t reserved_30:2;
};
uint32_t val;
} tee_lp_mm_pms_reg1_reg_t;
} pms_lp_mm_pms_reg1_reg_t;
/** Group: TEE LP MM PMS REG2 REG */
/** Type of lp_mm_pms_reg2 register
* NA
* Permission control register2 for the LP CPU in machine mode
*/
typedef union {
struct {
/** reg_lp_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1;
* NA
/** lp_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP MCPWM0.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_mcpwm0_allow:1;
/** reg_lp_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1;
* NA
uint32_t lp_mm_hp_mcpwm0_allow:1;
/** lp_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP MCPWM1.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_mcpwm1_allow:1;
/** reg_lp_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1;
* NA
uint32_t lp_mm_hp_mcpwm1_allow:1;
/** lp_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP timer
* group0.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_timer_group0_allow:1;
/** reg_lp_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1;
* NA
uint32_t lp_mm_hp_timer_group0_allow:1;
/** lp_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP timer
* group1.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_timer_group1_allow:1;
/** reg_lp_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1;
* NA
uint32_t lp_mm_hp_timer_group1_allow:1;
/** lp_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP I2C0.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_i2c0_allow:1;
/** reg_lp_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1;
* NA
uint32_t lp_mm_hp_i2c0_allow:1;
/** lp_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP I2C1.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_i2c1_allow:1;
/** reg_lp_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1;
* NA
uint32_t lp_mm_hp_i2c1_allow:1;
/** lp_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP I2S0.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_i2s0_allow:1;
/** reg_lp_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1;
* NA
uint32_t lp_mm_hp_i2s0_allow:1;
/** lp_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP I2S1.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_i2s1_allow:1;
/** reg_lp_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1;
* NA
uint32_t lp_mm_hp_i2s1_allow:1;
/** lp_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP I2S2.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_i2s2_allow:1;
/** reg_lp_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1;
* NA
uint32_t lp_mm_hp_i2s2_allow:1;
/** lp_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP PCNT.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_pcnt_allow:1;
/** reg_lp_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1;
* NA
uint32_t lp_mm_hp_pcnt_allow:1;
/** lp_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP UART0.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_uart0_allow:1;
/** reg_lp_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1;
* NA
uint32_t lp_mm_hp_uart0_allow:1;
/** lp_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP UART1.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_uart1_allow:1;
/** reg_lp_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1;
* NA
uint32_t lp_mm_hp_uart1_allow:1;
/** lp_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP UART2.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_uart2_allow:1;
/** reg_lp_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1;
* NA
uint32_t lp_mm_hp_uart2_allow:1;
/** lp_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP UART3.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_uart3_allow:1;
/** reg_lp_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1;
* NA
uint32_t lp_mm_hp_uart3_allow:1;
/** lp_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP UART4.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_uart4_allow:1;
/** reg_lp_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1;
* NA
uint32_t lp_mm_hp_uart4_allow:1;
/** lp_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP PARLIO.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_parlio_allow:1;
/** reg_lp_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1;
* NA
uint32_t lp_mm_hp_parlio_allow:1;
/** lp_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP GP-SPI2.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_gpspi2_allow:1;
/** reg_lp_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1;
* NA
uint32_t lp_mm_hp_gpspi2_allow:1;
/** lp_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP GP-SPI3.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_gpspi3_allow:1;
/** reg_lp_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1;
* NA
uint32_t lp_mm_hp_gpspi3_allow:1;
/** lp_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP
* USB/Serial JTAG Controller.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_usbdevice_allow:1;
/** reg_lp_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1;
* NA
uint32_t lp_mm_hp_usbdevice_allow:1;
/** lp_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP LEDC.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_ledc_allow:1;
uint32_t lp_mm_hp_ledc_allow:1;
uint32_t reserved_20:1;
/** reg_lp_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1;
* NA
/** lp_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP ETM.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_etm_allow:1;
/** reg_lp_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1;
* NA
uint32_t lp_mm_hp_etm_allow:1;
/** lp_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP interrupt
* matrix.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_intrmtx_allow:1;
/** reg_lp_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1;
* NA
uint32_t lp_mm_hp_intrmtx_allow:1;
/** lp_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP TWAI0.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_twai0_allow:1;
/** reg_lp_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1;
* NA
uint32_t lp_mm_hp_twai0_allow:1;
/** lp_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP TWAI1.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_twai1_allow:1;
/** reg_lp_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1;
* NA
uint32_t lp_mm_hp_twai1_allow:1;
/** lp_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP TWAI2.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_twai2_allow:1;
/** reg_lp_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1;
* NA
uint32_t lp_mm_hp_twai2_allow:1;
/** lp_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP I3C
* master controller.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_i3c_mst_allow:1;
/** reg_lp_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1;
* NA
uint32_t lp_mm_hp_i3c_mst_allow:1;
/** lp_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP I3C slave
* controller.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_i3c_slv_allow:1;
/** reg_lp_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1;
* NA
uint32_t lp_mm_hp_i3c_slv_allow:1;
/** lp_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP LCD_CAM.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_lcdcam_allow:1;
uint32_t lp_mm_hp_lcdcam_allow:1;
uint32_t reserved_29:1;
/** reg_lp_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1;
* NA
/** lp_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP ADC.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_adc_allow:1;
/** reg_lp_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1;
* NA
uint32_t lp_mm_hp_adc_allow:1;
/** lp_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP UHCI.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_uhci_allow:1;
uint32_t lp_mm_hp_uhci_allow:1;
};
uint32_t val;
} tee_lp_mm_pms_reg2_reg_t;
} pms_lp_mm_pms_reg2_reg_t;
/** Group: TEE LP MM PMS REG3 REG */
/** Type of lp_mm_pms_reg3 register
* NA
* Permission control register3 for the LP CPU in machine mode
*/
typedef union {
struct {
/** reg_lp_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1;
* NA
/** lp_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP GPIO
* Matrix.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_gpio_allow:1;
/** reg_lp_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1;
* NA
uint32_t lp_mm_hp_gpio_allow:1;
/** lp_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP IO MUX.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_iomux_allow:1;
/** reg_lp_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1;
* NA
uint32_t lp_mm_hp_iomux_allow:1;
/** lp_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP system
* timer.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_systimer_allow:1;
/** reg_lp_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1;
* NA
uint32_t lp_mm_hp_systimer_allow:1;
/** lp_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access HP system
* register.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_sys_reg_allow:1;
/** reg_lp_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1;
* NA
uint32_t lp_mm_hp_sys_reg_allow:1;
/** lp_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1;
* Configures whether the LP CPU in machine mode has permission to access
* HP_SYS_CLKRST.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp_clkrst_allow:1;
uint32_t lp_mm_hp_clkrst_allow:1;
uint32_t reserved_5:27;
};
uint32_t val;
} tee_lp_mm_pms_reg3_reg_t;
} pms_lp_mm_pms_reg3_reg_t;
typedef struct {
volatile tee_lp2hp_pms_date_reg_t lp2hp_pms_date;
volatile tee_pms_clk_en_reg_t pms_clk_en;
volatile tee_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0;
volatile pms_lp2hp_peri_pms_date_reg_t lp2hp_peri_pms_date;
volatile pms_lp2hp_peri_pms_clk_en_reg_t lp2hp_peri_pms_clk_en;
volatile pms_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0;
uint32_t reserved_00c[9];
volatile tee_lp_mm_pms_reg1_reg_t lp_mm_pms_reg1;
volatile pms_lp_mm_pms_reg1_reg_t lp_mm_pms_reg1;
uint32_t reserved_034[28];
volatile tee_lp_mm_pms_reg2_reg_t lp_mm_pms_reg2;
volatile pms_lp_mm_pms_reg2_reg_t lp_mm_pms_reg2;
uint32_t reserved_0a8[29];
volatile tee_lp_mm_pms_reg3_reg_t lp_mm_pms_reg3;
} tee_dev_t;
volatile pms_lp_mm_pms_reg3_reg_t lp_mm_pms_reg3;
} lp2hp_peri_pms_dev_t;
extern tee_dev_t LP2HP_PERI_PMS;
extern lp2hp_peri_pms_dev_t LP2HP_PERI_PMS;
#ifndef __cplusplus
_Static_assert(sizeof(tee_dev_t) == 0x120, "Invalid size of tee_dev_t structure");
_Static_assert(sizeof(lp2hp_peri_pms_dev_t) == 0x120, "Invalid size of lp2hp_peri_pms_dev_t structure");
#endif
#ifdef __cplusplus
components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_eco5_reg.h
-491
View File
@@ -1,491 +0,0 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** TEE_PMS_DATE_REG register
* NA
*/
#define TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943;
* NA
*/
#define TEE_TEE_DATE 0xFFFFFFFFU
#define TEE_TEE_DATE_M (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
#define TEE_TEE_DATE_V 0xFFFFFFFFU
#define TEE_TEE_DATE_S 0
/** TEE_PMS_CLK_EN_REG register
* NA
*/
#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_CLK_EN (BIT(0))
#define TEE_REG_CLK_EN_M (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
#define TEE_REG_CLK_EN_V 0x00000001U
#define TEE_REG_CLK_EN_S 0
/** TEE_LP_MM_PMS_REG0_REG register
* NA
*/
#define TEE_LP_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
/** TEE_REG_LP_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_SYSREG_ALLOW (BIT(0))
#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_M (TEE_REG_LP_MM_LP_SYSREG_ALLOW_V << TEE_REG_LP_MM_LP_SYSREG_ALLOW_S)
#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_SYSREG_ALLOW_S 0
/** TEE_REG_LP_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW (BIT(1))
#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_M (TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_S)
#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_AONCLKRST_ALLOW_S 1
/** TEE_REG_LP_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_TIMER_ALLOW (BIT(2))
#define TEE_REG_LP_MM_LP_TIMER_ALLOW_M (TEE_REG_LP_MM_LP_TIMER_ALLOW_V << TEE_REG_LP_MM_LP_TIMER_ALLOW_S)
#define TEE_REG_LP_MM_LP_TIMER_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_TIMER_ALLOW_S 2
/** TEE_REG_LP_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW (BIT(3))
#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_M (TEE_REG_LP_MM_LP_ANAPERI_ALLOW_V << TEE_REG_LP_MM_LP_ANAPERI_ALLOW_S)
#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_ANAPERI_ALLOW_S 3
/** TEE_REG_LP_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_PMU_ALLOW (BIT(4))
#define TEE_REG_LP_MM_LP_PMU_ALLOW_M (TEE_REG_LP_MM_LP_PMU_ALLOW_V << TEE_REG_LP_MM_LP_PMU_ALLOW_S)
#define TEE_REG_LP_MM_LP_PMU_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_PMU_ALLOW_S 4
/** TEE_REG_LP_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_WDT_ALLOW (BIT(5))
#define TEE_REG_LP_MM_LP_WDT_ALLOW_M (TEE_REG_LP_MM_LP_WDT_ALLOW_V << TEE_REG_LP_MM_LP_WDT_ALLOW_S)
#define TEE_REG_LP_MM_LP_WDT_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_WDT_ALLOW_S 5
/** TEE_REG_LP_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW (BIT(6))
#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_M (TEE_REG_LP_MM_LP_MAILBOX_ALLOW_V << TEE_REG_LP_MM_LP_MAILBOX_ALLOW_S)
#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_MAILBOX_ALLOW_S 6
/** TEE_REG_LP_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_RTC_ALLOW (BIT(7))
#define TEE_REG_LP_MM_LP_RTC_ALLOW_M (TEE_REG_LP_MM_LP_RTC_ALLOW_V << TEE_REG_LP_MM_LP_RTC_ALLOW_S)
#define TEE_REG_LP_MM_LP_RTC_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_RTC_ALLOW_S 7
/** TEE_REG_LP_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW (BIT(8))
#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_M (TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_S)
#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_PERICLKRST_ALLOW_S 8
/** TEE_REG_LP_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_UART_ALLOW (BIT(9))
#define TEE_REG_LP_MM_LP_UART_ALLOW_M (TEE_REG_LP_MM_LP_UART_ALLOW_V << TEE_REG_LP_MM_LP_UART_ALLOW_S)
#define TEE_REG_LP_MM_LP_UART_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_UART_ALLOW_S 9
/** TEE_REG_LP_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_I2C_ALLOW (BIT(10))
#define TEE_REG_LP_MM_LP_I2C_ALLOW_M (TEE_REG_LP_MM_LP_I2C_ALLOW_V << TEE_REG_LP_MM_LP_I2C_ALLOW_S)
#define TEE_REG_LP_MM_LP_I2C_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_I2C_ALLOW_S 10
/** TEE_REG_LP_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_SPI_ALLOW (BIT(11))
#define TEE_REG_LP_MM_LP_SPI_ALLOW_M (TEE_REG_LP_MM_LP_SPI_ALLOW_V << TEE_REG_LP_MM_LP_SPI_ALLOW_S)
#define TEE_REG_LP_MM_LP_SPI_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_SPI_ALLOW_S 11
/** TEE_REG_LP_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_I2CMST_ALLOW (BIT(12))
#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_M (TEE_REG_LP_MM_LP_I2CMST_ALLOW_V << TEE_REG_LP_MM_LP_I2CMST_ALLOW_S)
#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_I2CMST_ALLOW_S 12
/** TEE_REG_LP_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_I2S_ALLOW (BIT(13))
#define TEE_REG_LP_MM_LP_I2S_ALLOW_M (TEE_REG_LP_MM_LP_I2S_ALLOW_V << TEE_REG_LP_MM_LP_I2S_ALLOW_S)
#define TEE_REG_LP_MM_LP_I2S_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_I2S_ALLOW_S 13
/** TEE_REG_LP_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_ADC_ALLOW (BIT(14))
#define TEE_REG_LP_MM_LP_ADC_ALLOW_M (TEE_REG_LP_MM_LP_ADC_ALLOW_V << TEE_REG_LP_MM_LP_ADC_ALLOW_S)
#define TEE_REG_LP_MM_LP_ADC_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_ADC_ALLOW_S 14
/** TEE_REG_LP_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_TOUCH_ALLOW (BIT(15))
#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_M (TEE_REG_LP_MM_LP_TOUCH_ALLOW_V << TEE_REG_LP_MM_LP_TOUCH_ALLOW_S)
#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_TOUCH_ALLOW_S 15
/** TEE_REG_LP_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_IOMUX_ALLOW (BIT(16))
#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_M (TEE_REG_LP_MM_LP_IOMUX_ALLOW_V << TEE_REG_LP_MM_LP_IOMUX_ALLOW_S)
#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_IOMUX_ALLOW_S 16
/** TEE_REG_LP_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_INTR_ALLOW (BIT(17))
#define TEE_REG_LP_MM_LP_INTR_ALLOW_M (TEE_REG_LP_MM_LP_INTR_ALLOW_V << TEE_REG_LP_MM_LP_INTR_ALLOW_S)
#define TEE_REG_LP_MM_LP_INTR_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_INTR_ALLOW_S 17
/** TEE_REG_LP_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_EFUSE_ALLOW (BIT(18))
#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_M (TEE_REG_LP_MM_LP_EFUSE_ALLOW_V << TEE_REG_LP_MM_LP_EFUSE_ALLOW_S)
#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_EFUSE_ALLOW_S 18
/** TEE_REG_LP_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_PMS_ALLOW (BIT(19))
#define TEE_REG_LP_MM_LP_PMS_ALLOW_M (TEE_REG_LP_MM_LP_PMS_ALLOW_V << TEE_REG_LP_MM_LP_PMS_ALLOW_S)
#define TEE_REG_LP_MM_LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_PMS_ALLOW_S 19
/** TEE_REG_LP_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW (BIT(20))
#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_M (TEE_REG_LP_MM_HP2LP_PMS_ALLOW_V << TEE_REG_LP_MM_HP2LP_PMS_ALLOW_S)
#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_HP2LP_PMS_ALLOW_S 20
/** TEE_REG_LP_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_TSENS_ALLOW (BIT(21))
#define TEE_REG_LP_MM_LP_TSENS_ALLOW_M (TEE_REG_LP_MM_LP_TSENS_ALLOW_V << TEE_REG_LP_MM_LP_TSENS_ALLOW_S)
#define TEE_REG_LP_MM_LP_TSENS_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_TSENS_ALLOW_S 21
/** TEE_REG_LP_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_HUK_ALLOW (BIT(22))
#define TEE_REG_LP_MM_LP_HUK_ALLOW_M (TEE_REG_LP_MM_LP_HUK_ALLOW_V << TEE_REG_LP_MM_LP_HUK_ALLOW_S)
#define TEE_REG_LP_MM_LP_HUK_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_HUK_ALLOW_S 22
/** TEE_REG_LP_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW (BIT(23))
#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_M (TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_S)
#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_TCM_RAM_ALLOW_S 23
/** TEE_REG_LP_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
* NA
*/
#define TEE_REG_LP_MM_LP_TRNG_ALLOW (BIT(24))
#define TEE_REG_LP_MM_LP_TRNG_ALLOW_M (TEE_REG_LP_MM_LP_TRNG_ALLOW_V << TEE_REG_LP_MM_LP_TRNG_ALLOW_S)
#define TEE_REG_LP_MM_LP_TRNG_ALLOW_V 0x00000001U
#define TEE_REG_LP_MM_LP_TRNG_ALLOW_S 24
/** TEE_PERI_REGION0_LOW_REG register
* NA
*/
#define TEE_PERI_REGION0_LOW_REG (DR_REG_TEE_BASE + 0xc)
/** TEE_REG_PERI_REGION0_LOW : R/W; bitpos: [31:2]; default: 0;
* NA
*/
#define TEE_REG_PERI_REGION0_LOW 0x3FFFFFFFU
#define TEE_REG_PERI_REGION0_LOW_M (TEE_REG_PERI_REGION0_LOW_V << TEE_REG_PERI_REGION0_LOW_S)
#define TEE_REG_PERI_REGION0_LOW_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION0_LOW_S 2
/** TEE_PERI_REGION0_HIGH_REG register
* NA
*/
#define TEE_PERI_REGION0_HIGH_REG (DR_REG_TEE_BASE + 0x10)
/** TEE_REG_PERI_REGION0_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
#define TEE_REG_PERI_REGION0_HIGH 0x3FFFFFFFU
#define TEE_REG_PERI_REGION0_HIGH_M (TEE_REG_PERI_REGION0_HIGH_V << TEE_REG_PERI_REGION0_HIGH_S)
#define TEE_REG_PERI_REGION0_HIGH_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION0_HIGH_S 2
/** TEE_PERI_REGION1_LOW_REG register
* NA
*/
#define TEE_PERI_REGION1_LOW_REG (DR_REG_TEE_BASE + 0x14)
/** TEE_REG_PERI_REGION1_LOW : R/W; bitpos: [31:2]; default: 0;
* NA
*/
#define TEE_REG_PERI_REGION1_LOW 0x3FFFFFFFU
#define TEE_REG_PERI_REGION1_LOW_M (TEE_REG_PERI_REGION1_LOW_V << TEE_REG_PERI_REGION1_LOW_S)
#define TEE_REG_PERI_REGION1_LOW_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION1_LOW_S 2
/** TEE_PERI_REGION1_HIGH_REG register
* NA
*/
#define TEE_PERI_REGION1_HIGH_REG (DR_REG_TEE_BASE + 0x18)
/** TEE_REG_PERI_REGION1_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
#define TEE_REG_PERI_REGION1_HIGH 0x3FFFFFFFU
#define TEE_REG_PERI_REGION1_HIGH_M (TEE_REG_PERI_REGION1_HIGH_V << TEE_REG_PERI_REGION1_HIGH_S)
#define TEE_REG_PERI_REGION1_HIGH_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION1_HIGH_S 2
/** TEE_PERI_REGION_PMS_REG register
* NA
*/
#define TEE_PERI_REGION_PMS_REG (DR_REG_TEE_BASE + 0x1c)
/** TEE_REG_LP_CORE_REGION_PMS : R/W; bitpos: [1:0]; default: 3;
* NA
*/
#define TEE_REG_LP_CORE_REGION_PMS 0x00000003U
#define TEE_REG_LP_CORE_REGION_PMS_M (TEE_REG_LP_CORE_REGION_PMS_V << TEE_REG_LP_CORE_REGION_PMS_S)
#define TEE_REG_LP_CORE_REGION_PMS_V 0x00000003U
#define TEE_REG_LP_CORE_REGION_PMS_S 0
/** TEE_REG_HP_CORE0_UM_REGION_PMS : R/W; bitpos: [3:2]; default: 3;
* NA
*/
#define TEE_REG_HP_CORE0_UM_REGION_PMS 0x00000003U
#define TEE_REG_HP_CORE0_UM_REGION_PMS_M (TEE_REG_HP_CORE0_UM_REGION_PMS_V << TEE_REG_HP_CORE0_UM_REGION_PMS_S)
#define TEE_REG_HP_CORE0_UM_REGION_PMS_V 0x00000003U
#define TEE_REG_HP_CORE0_UM_REGION_PMS_S 2
/** TEE_REG_HP_CORE0_MM_REGION_PMS : R/W; bitpos: [5:4]; default: 3;
* NA
*/
#define TEE_REG_HP_CORE0_MM_REGION_PMS 0x00000003U
#define TEE_REG_HP_CORE0_MM_REGION_PMS_M (TEE_REG_HP_CORE0_MM_REGION_PMS_V << TEE_REG_HP_CORE0_MM_REGION_PMS_S)
#define TEE_REG_HP_CORE0_MM_REGION_PMS_V 0x00000003U
#define TEE_REG_HP_CORE0_MM_REGION_PMS_S 4
/** TEE_REG_HP_CORE1_UM_REGION_PMS : R/W; bitpos: [7:6]; default: 3;
* NA
*/
#define TEE_REG_HP_CORE1_UM_REGION_PMS 0x00000003U
#define TEE_REG_HP_CORE1_UM_REGION_PMS_M (TEE_REG_HP_CORE1_UM_REGION_PMS_V << TEE_REG_HP_CORE1_UM_REGION_PMS_S)
#define TEE_REG_HP_CORE1_UM_REGION_PMS_V 0x00000003U
#define TEE_REG_HP_CORE1_UM_REGION_PMS_S 6
/** TEE_REG_HP_CORE1_MM_REGION_PMS : R/W; bitpos: [9:8]; default: 3;
* NA
*/
#define TEE_REG_HP_CORE1_MM_REGION_PMS 0x00000003U
#define TEE_REG_HP_CORE1_MM_REGION_PMS_M (TEE_REG_HP_CORE1_MM_REGION_PMS_V << TEE_REG_HP_CORE1_MM_REGION_PMS_S)
#define TEE_REG_HP_CORE1_MM_REGION_PMS_V 0x00000003U
#define TEE_REG_HP_CORE1_MM_REGION_PMS_S 8
/** TEE_PERI_REGION_2_TO_7_PMS_REG register
* NA
*/
#define TEE_PERI_REGION_2_TO_7_PMS_REG (DR_REG_TEE_BASE + 0x20)
/** TEE_REG_LP_CORE_REGION_2_TO_7_PMS : R/W; bitpos: [5:0]; default: 63;
* NA
*/
#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS 0x0000003FU
#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS_M (TEE_REG_LP_CORE_REGION_2_TO_7_PMS_V << TEE_REG_LP_CORE_REGION_2_TO_7_PMS_S)
#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS_V 0x0000003FU
#define TEE_REG_LP_CORE_REGION_2_TO_7_PMS_S 0
/** TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS : R/W; bitpos: [11:6]; default: 63;
* NA
*/
#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS 0x0000003FU
#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_M (TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_S)
#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_V 0x0000003FU
#define TEE_REG_HP_CORE0_UM_REGION_2_TO_7_PMS_S 6
/** TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS : R/W; bitpos: [17:12]; default: 63;
* NA
*/
#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS 0x0000003FU
#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_M (TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_S)
#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_V 0x0000003FU
#define TEE_REG_HP_CORE0_MM_REGION_2_TO_7_PMS_S 12
/** TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS : R/W; bitpos: [23:18]; default: 63;
* NA
*/
#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS 0x0000003FU
#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_M (TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_S)
#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_V 0x0000003FU
#define TEE_REG_HP_CORE1_UM_REGION_2_TO_7_PMS_S 18
/** TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS : R/W; bitpos: [29:24]; default: 63;
* NA
*/
#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS 0x0000003FU
#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_M (TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_V << TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_S)
#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_V 0x0000003FU
#define TEE_REG_HP_CORE1_MM_REGION_2_TO_7_PMS_S 24
/** TEE_PERI_REGION2_LOW_REG register
* NA
*/
#define TEE_PERI_REGION2_LOW_REG (DR_REG_TEE_BASE + 0x24)
/** TEE_REG_PERI_REGION2_LOW : R/W; bitpos: [31:2]; default: 0;
* NA
*/
#define TEE_REG_PERI_REGION2_LOW 0x3FFFFFFFU
#define TEE_REG_PERI_REGION2_LOW_M (TEE_REG_PERI_REGION2_LOW_V << TEE_REG_PERI_REGION2_LOW_S)
#define TEE_REG_PERI_REGION2_LOW_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION2_LOW_S 2
/** TEE_PERI_REGION2_HIGH_REG register
* NA
*/
#define TEE_PERI_REGION2_HIGH_REG (DR_REG_TEE_BASE + 0x28)
/** TEE_REG_PERI_REGION2_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
#define TEE_REG_PERI_REGION2_HIGH 0x3FFFFFFFU
#define TEE_REG_PERI_REGION2_HIGH_M (TEE_REG_PERI_REGION2_HIGH_V << TEE_REG_PERI_REGION2_HIGH_S)
#define TEE_REG_PERI_REGION2_HIGH_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION2_HIGH_S 2
/** TEE_PERI_REGION3_LOW_REG register
* NA
*/
#define TEE_PERI_REGION3_LOW_REG (DR_REG_TEE_BASE + 0x2c)
/** TEE_REG_PERI_REGION3_LOW : R/W; bitpos: [31:2]; default: 0;
* NA
*/
#define TEE_REG_PERI_REGION3_LOW 0x3FFFFFFFU
#define TEE_REG_PERI_REGION3_LOW_M (TEE_REG_PERI_REGION3_LOW_V << TEE_REG_PERI_REGION3_LOW_S)
#define TEE_REG_PERI_REGION3_LOW_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION3_LOW_S 2
/** TEE_PERI_REGION3_HIGH_REG register
* NA
*/
#define TEE_PERI_REGION3_HIGH_REG (DR_REG_TEE_BASE + 0x30)
/** TEE_REG_PERI_REGION3_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
#define TEE_REG_PERI_REGION3_HIGH 0x3FFFFFFFU
#define TEE_REG_PERI_REGION3_HIGH_M (TEE_REG_PERI_REGION3_HIGH_V << TEE_REG_PERI_REGION3_HIGH_S)
#define TEE_REG_PERI_REGION3_HIGH_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION3_HIGH_S 2
/** TEE_PERI_REGION4_LOW_REG register
* NA
*/
#define TEE_PERI_REGION4_LOW_REG (DR_REG_TEE_BASE + 0x34)
/** TEE_REG_PERI_REGION4_LOW : R/W; bitpos: [31:2]; default: 0;
* NA
*/
#define TEE_REG_PERI_REGION4_LOW 0x3FFFFFFFU
#define TEE_REG_PERI_REGION4_LOW_M (TEE_REG_PERI_REGION4_LOW_V << TEE_REG_PERI_REGION4_LOW_S)
#define TEE_REG_PERI_REGION4_LOW_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION4_LOW_S 2
/** TEE_PERI_REGION4_HIGH_REG register
* NA
*/
#define TEE_PERI_REGION4_HIGH_REG (DR_REG_TEE_BASE + 0x38)
/** TEE_REG_PERI_REGION4_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
#define TEE_REG_PERI_REGION4_HIGH 0x3FFFFFFFU
#define TEE_REG_PERI_REGION4_HIGH_M (TEE_REG_PERI_REGION4_HIGH_V << TEE_REG_PERI_REGION4_HIGH_S)
#define TEE_REG_PERI_REGION4_HIGH_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION4_HIGH_S 2
/** TEE_PERI_REGION5_LOW_REG register
* NA
*/
#define TEE_PERI_REGION5_LOW_REG (DR_REG_TEE_BASE + 0x3c)
/** TEE_REG_PERI_REGION5_LOW : R/W; bitpos: [31:2]; default: 0;
* NA
*/
#define TEE_REG_PERI_REGION5_LOW 0x3FFFFFFFU
#define TEE_REG_PERI_REGION5_LOW_M (TEE_REG_PERI_REGION5_LOW_V << TEE_REG_PERI_REGION5_LOW_S)
#define TEE_REG_PERI_REGION5_LOW_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION5_LOW_S 2
/** TEE_PERI_REGION5_HIGH_REG register
* NA
*/
#define TEE_PERI_REGION5_HIGH_REG (DR_REG_TEE_BASE + 0x40)
/** TEE_REG_PERI_REGION5_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
#define TEE_REG_PERI_REGION5_HIGH 0x3FFFFFFFU
#define TEE_REG_PERI_REGION5_HIGH_M (TEE_REG_PERI_REGION5_HIGH_V << TEE_REG_PERI_REGION5_HIGH_S)
#define TEE_REG_PERI_REGION5_HIGH_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION5_HIGH_S 2
/** TEE_PERI_REGION6_LOW_REG register
* NA
*/
#define TEE_PERI_REGION6_LOW_REG (DR_REG_TEE_BASE + 0x44)
/** TEE_REG_PERI_REGION6_LOW : R/W; bitpos: [31:2]; default: 0;
* NA
*/
#define TEE_REG_PERI_REGION6_LOW 0x3FFFFFFFU
#define TEE_REG_PERI_REGION6_LOW_M (TEE_REG_PERI_REGION6_LOW_V << TEE_REG_PERI_REGION6_LOW_S)
#define TEE_REG_PERI_REGION6_LOW_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION6_LOW_S 2
/** TEE_PERI_REGION6_HIGH_REG register
* NA
*/
#define TEE_PERI_REGION6_HIGH_REG (DR_REG_TEE_BASE + 0x48)
/** TEE_REG_PERI_REGION6_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
#define TEE_REG_PERI_REGION6_HIGH 0x3FFFFFFFU
#define TEE_REG_PERI_REGION6_HIGH_M (TEE_REG_PERI_REGION6_HIGH_V << TEE_REG_PERI_REGION6_HIGH_S)
#define TEE_REG_PERI_REGION6_HIGH_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION6_HIGH_S 2
/** TEE_PERI_REGION7_LOW_REG register
* NA
*/
#define TEE_PERI_REGION7_LOW_REG (DR_REG_TEE_BASE + 0x4c)
/** TEE_REG_PERI_REGION7_LOW : R/W; bitpos: [31:2]; default: 0;
* NA
*/
#define TEE_REG_PERI_REGION7_LOW 0x3FFFFFFFU
#define TEE_REG_PERI_REGION7_LOW_M (TEE_REG_PERI_REGION7_LOW_V << TEE_REG_PERI_REGION7_LOW_S)
#define TEE_REG_PERI_REGION7_LOW_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION7_LOW_S 2
/** TEE_PERI_REGION7_HIGH_REG register
* NA
*/
#define TEE_PERI_REGION7_HIGH_REG (DR_REG_TEE_BASE + 0x50)
/** TEE_REG_PERI_REGION7_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
#define TEE_REG_PERI_REGION7_HIGH 0x3FFFFFFFU
#define TEE_REG_PERI_REGION7_HIGH_M (TEE_REG_PERI_REGION7_HIGH_V << TEE_REG_PERI_REGION7_HIGH_S)
#define TEE_REG_PERI_REGION7_HIGH_V 0x3FFFFFFFU
#define TEE_REG_PERI_REGION7_HIGH_S 2
#ifdef __cplusplus
}
#endif
components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_reg.h
+209 -1
View File
@@ -14,7 +14,7 @@ extern "C" {
* Version control register
*/
#define PMS_LP_PERI_PMS_DATE_REG (DR_REG_LP_PERI_PMS_BASE + 0x0)
/** PMS_LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537;
/** PMS_LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2363943;
* Version control register
*/
#define PMS_LP_PERI_PMS_DATE 0xFFFFFFFFU
@@ -267,6 +267,15 @@ extern "C" {
#define PMS_LP_MM_LP_SRAM_ALLOW_M (PMS_LP_MM_LP_SRAM_ALLOW_V << PMS_LP_MM_LP_SRAM_ALLOW_S)
#define PMS_LP_MM_LP_SRAM_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_SRAM_ALLOW_S 23
/** PMS_LP_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
* Configures whether LP CPU in machine mode has permission to access RNG.
* 0: Not allowed
* 1: Allow
*/
#define PMS_LP_MM_LP_TRNG_ALLOW (BIT(24))
#define PMS_LP_MM_LP_TRNG_ALLOW_M (PMS_LP_MM_LP_TRNG_ALLOW_V << PMS_LP_MM_LP_TRNG_ALLOW_S)
#define PMS_LP_MM_LP_TRNG_ALLOW_V 0x00000001U
#define PMS_LP_MM_LP_TRNG_ALLOW_S 24
/** PMS_PERI_REGION0_LOW_REG register
* Region0 start address configuration register
@@ -371,6 +380,205 @@ extern "C" {
#define PMS_HP_CORE1_MM_REGION_PMS_V 0x00000003U
#define PMS_HP_CORE1_MM_REGION_PMS_S 8
/** PMS_PERI_REGION_2_TO_7_PMS_REG register
* Permission register of region 2 to 7
*/
#define PMS_PERI_REGION_2_TO_7_PMS_REG (DR_REG_LP_PERI_PMS_BASE + 0x20)
/** PMS_LP_CORE_REGION_2_TO_7_PMS : R/W; bitpos: [5:0]; default: 63;
* Configures whether LP core in machine mode has permission to access address region2
* to region7. Bit0 corresponds to region2, bit1 to region3, ..., bit5 to region7.
* 0: Not allowed
* 1: Allow
*/
#define PMS_LP_CORE_REGION_2_TO_7_PMS 0x0000003FU
#define PMS_LP_CORE_REGION_2_TO_7_PMS_M (PMS_LP_CORE_REGION_2_TO_7_PMS_V << PMS_LP_CORE_REGION_2_TO_7_PMS_S)
#define PMS_LP_CORE_REGION_2_TO_7_PMS_V 0x0000003FU
#define PMS_LP_CORE_REGION_2_TO_7_PMS_S 0
/** PMS_HP_CORE0_UM_REGION_2_TO_7_PMS : R/W; bitpos: [11:6]; default: 63;
* Configures whether HP CPU0 in user mode has permission to access address region2
* to region7. Bit6 corresponds to region2, bit7 to region3, ..., bit11 to region7.
* 0: Not allowed
* 1: Allow
*/
#define PMS_HP_CORE0_UM_REGION_2_TO_7_PMS 0x0000003FU
#define PMS_HP_CORE0_UM_REGION_2_TO_7_PMS_M (PMS_HP_CORE0_UM_REGION_2_TO_7_PMS_V << PMS_HP_CORE0_UM_REGION_2_TO_7_PMS_S)
#define PMS_HP_CORE0_UM_REGION_2_TO_7_PMS_V 0x0000003FU
#define PMS_HP_CORE0_UM_REGION_2_TO_7_PMS_S 6
/** PMS_HP_CORE0_MM_REGION_2_TO_7_PMS : R/W; bitpos: [17:12]; default: 63;
* Configures whether HP CPU0 in machine mode has permission to access address region2
* to region7. Bit12 corresponds to region2, bit13 to region3, ..., bit17 to region7.
* 0: Not allowed
* 1: Allow
*/
#define PMS_HP_CORE0_MM_REGION_2_TO_7_PMS 0x0000003FU
#define PMS_HP_CORE0_MM_REGION_2_TO_7_PMS_M (PMS_HP_CORE0_MM_REGION_2_TO_7_PMS_V << PMS_HP_CORE0_MM_REGION_2_TO_7_PMS_S)
#define PMS_HP_CORE0_MM_REGION_2_TO_7_PMS_V 0x0000003FU
#define PMS_HP_CORE0_MM_REGION_2_TO_7_PMS_S 12
/** PMS_HP_CORE1_UM_REGION_2_TO_7_PMS : R/W; bitpos: [23:18]; default: 63;
* Configures whether HP CPU1 in user mode has permission to access address region2
* to region7. Bit18 corresponds to region2, bit19 to region3, ..., bit23 to region7.
* 0: Not allowed
* 1: Allow
*/
#define PMS_HP_CORE1_UM_REGION_2_TO_7_PMS 0x0000003FU
#define PMS_HP_CORE1_UM_REGION_2_TO_7_PMS_M (PMS_HP_CORE1_UM_REGION_2_TO_7_PMS_V << PMS_HP_CORE1_UM_REGION_2_TO_7_PMS_S)
#define PMS_HP_CORE1_UM_REGION_2_TO_7_PMS_V 0x0000003FU
#define PMS_HP_CORE1_UM_REGION_2_TO_7_PMS_S 18
/** PMS_HP_CORE1_MM_REGION_2_TO_7_PMS : R/W; bitpos: [29:24]; default: 63;
* Configures whether HP CPU1 in machine mode has permission to access address region2
* to region7. Bit24 corresponds to region2, bit25 to region3, ..., bit29 to region7.
* 0: Not allowed
* 1: Allow
*/
#define PMS_HP_CORE1_MM_REGION_2_TO_7_PMS 0x0000003FU
#define PMS_HP_CORE1_MM_REGION_2_TO_7_PMS_M (PMS_HP_CORE1_MM_REGION_2_TO_7_PMS_V << PMS_HP_CORE1_MM_REGION_2_TO_7_PMS_S)
#define PMS_HP_CORE1_MM_REGION_2_TO_7_PMS_V 0x0000003FU
#define PMS_HP_CORE1_MM_REGION_2_TO_7_PMS_S 24
/** PMS_PERI_REGION2_LOW_REG register
* Region2 start address configuration register
*/
#define PMS_PERI_REGION2_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x24)
/** PMS_PERI_REGION2_LOW : R/W; bitpos: [31:2]; default: 0;
* Configures the high 30 bits of the start address of peripheral register's region2.
*/
#define PMS_PERI_REGION2_LOW 0x3FFFFFFFU
#define PMS_PERI_REGION2_LOW_M (PMS_PERI_REGION2_LOW_V << PMS_PERI_REGION2_LOW_S)
#define PMS_PERI_REGION2_LOW_V 0x3FFFFFFFU
#define PMS_PERI_REGION2_LOW_S 2
/** PMS_PERI_REGION2_HIGH_REG register
* Region2 end address configuration register
*/
#define PMS_PERI_REGION2_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x28)
/** PMS_PERI_REGION2_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* Configures the high 30 bits of the end address of peripheral register's region2.
*/
#define PMS_PERI_REGION2_HIGH 0x3FFFFFFFU
#define PMS_PERI_REGION2_HIGH_M (PMS_PERI_REGION2_HIGH_V << PMS_PERI_REGION2_HIGH_S)
#define PMS_PERI_REGION2_HIGH_V 0x3FFFFFFFU
#define PMS_PERI_REGION2_HIGH_S 2
/** PMS_PERI_REGION3_LOW_REG register
* Region3 start address configuration register
*/
#define PMS_PERI_REGION3_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x2c)
/** PMS_PERI_REGION3_LOW : R/W; bitpos: [31:2]; default: 0;
* Configures the high 30 bits of the start address of peripheral register's region3.
*/
#define PMS_PERI_REGION3_LOW 0x3FFFFFFFU
#define PMS_PERI_REGION3_LOW_M (PMS_PERI_REGION3_LOW_V << PMS_PERI_REGION3_LOW_S)
#define PMS_PERI_REGION3_LOW_V 0x3FFFFFFFU
#define PMS_PERI_REGION3_LOW_S 2
/** PMS_PERI_REGION3_HIGH_REG register
* Region3 end address configuration register
*/
#define PMS_PERI_REGION3_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x30)
/** PMS_PERI_REGION3_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* Configures the high 30 bits of the end address of peripheral register's region3.
*/
#define PMS_PERI_REGION3_HIGH 0x3FFFFFFFU
#define PMS_PERI_REGION3_HIGH_M (PMS_PERI_REGION3_HIGH_V << PMS_PERI_REGION3_HIGH_S)
#define PMS_PERI_REGION3_HIGH_V 0x3FFFFFFFU
#define PMS_PERI_REGION3_HIGH_S 2
/** PMS_PERI_REGION4_LOW_REG register
* Region4 start address configuration register
*/
#define PMS_PERI_REGION4_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x34)
/** PMS_PERI_REGION4_LOW : R/W; bitpos: [31:2]; default: 0;
* Configures the high 30 bits of the start address of peripheral register's region4.
*/
#define PMS_PERI_REGION4_LOW 0x3FFFFFFFU
#define PMS_PERI_REGION4_LOW_M (PMS_PERI_REGION4_LOW_V << PMS_PERI_REGION4_LOW_S)
#define PMS_PERI_REGION4_LOW_V 0x3FFFFFFFU
#define PMS_PERI_REGION4_LOW_S 2
/** PMS_PERI_REGION4_HIGH_REG register
* Region4 end address configuration register
*/
#define PMS_PERI_REGION4_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x38)
/** PMS_PERI_REGION4_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* Configures the high 30 bits of the end address of peripheral register's region4.
*/
#define PMS_PERI_REGION4_HIGH 0x3FFFFFFFU
#define PMS_PERI_REGION4_HIGH_M (PMS_PERI_REGION4_HIGH_V << PMS_PERI_REGION4_HIGH_S)
#define PMS_PERI_REGION4_HIGH_V 0x3FFFFFFFU
#define PMS_PERI_REGION4_HIGH_S 2
/** PMS_PERI_REGION5_LOW_REG register
* Region5 start address configuration register
*/
#define PMS_PERI_REGION5_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x3c)
/** PMS_PERI_REGION5_LOW : R/W; bitpos: [31:2]; default: 0;
* Configures the high 30 bits of the start address of peripheral register's region5.
*/
#define PMS_PERI_REGION5_LOW 0x3FFFFFFFU
#define PMS_PERI_REGION5_LOW_M (PMS_PERI_REGION5_LOW_V << PMS_PERI_REGION5_LOW_S)
#define PMS_PERI_REGION5_LOW_V 0x3FFFFFFFU
#define PMS_PERI_REGION5_LOW_S 2
/** PMS_PERI_REGION5_HIGH_REG register
* Region5 end address configuration register
*/
#define PMS_PERI_REGION5_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x40)
/** PMS_PERI_REGION5_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* Configures the high 30 bits of the end address of peripheral register's region5.
*/
#define PMS_PERI_REGION5_HIGH 0x3FFFFFFFU
#define PMS_PERI_REGION5_HIGH_M (PMS_PERI_REGION5_HIGH_V << PMS_PERI_REGION5_HIGH_S)
#define PMS_PERI_REGION5_HIGH_V 0x3FFFFFFFU
#define PMS_PERI_REGION5_HIGH_S 2
/** PMS_PERI_REGION6_LOW_REG register
* Region6 start address configuration register
*/
#define PMS_PERI_REGION6_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x44)
/** PMS_PERI_REGION6_LOW : R/W; bitpos: [31:2]; default: 0;
* Configures the high 30 bits of the start address of peripheral register's region6.
*/
#define PMS_PERI_REGION6_LOW 0x3FFFFFFFU
#define PMS_PERI_REGION6_LOW_M (PMS_PERI_REGION6_LOW_V << PMS_PERI_REGION6_LOW_S)
#define PMS_PERI_REGION6_LOW_V 0x3FFFFFFFU
#define PMS_PERI_REGION6_LOW_S 2
/** PMS_PERI_REGION6_HIGH_REG register
* Region6 end address configuration register
*/
#define PMS_PERI_REGION6_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x48)
/** PMS_PERI_REGION6_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* Configures the high 30 bits of the end address of peripheral register's region6.
*/
#define PMS_PERI_REGION6_HIGH 0x3FFFFFFFU
#define PMS_PERI_REGION6_HIGH_M (PMS_PERI_REGION6_HIGH_V << PMS_PERI_REGION6_HIGH_S)
#define PMS_PERI_REGION6_HIGH_V 0x3FFFFFFFU
#define PMS_PERI_REGION6_HIGH_S 2
/** PMS_PERI_REGION7_LOW_REG register
* Region7 start address configuration register
*/
#define PMS_PERI_REGION7_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x4c)
/** PMS_PERI_REGION7_LOW : R/W; bitpos: [31:2]; default: 0;
* Configures the high 30 bits of the start address of peripheral register's region7.
*/
#define PMS_PERI_REGION7_LOW 0x3FFFFFFFU
#define PMS_PERI_REGION7_LOW_M (PMS_PERI_REGION7_LOW_V << PMS_PERI_REGION7_LOW_S)
#define PMS_PERI_REGION7_LOW_V 0x3FFFFFFFU
#define PMS_PERI_REGION7_LOW_S 2
/** PMS_PERI_REGION7_HIGH_REG register
* Region7 end address configuration register
*/
#define PMS_PERI_REGION7_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x50)
/** PMS_PERI_REGION7_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
* Configures the high 30 bits of the end address of peripheral register's region7.
*/
#define PMS_PERI_REGION7_HIGH 0x3FFFFFFFU
#define PMS_PERI_REGION7_HIGH_M (PMS_PERI_REGION7_HIGH_V << PMS_PERI_REGION7_HIGH_S)
#define PMS_PERI_REGION7_HIGH_V 0x3FFFFFFFU
#define PMS_PERI_REGION7_HIGH_S 2
#ifdef __cplusplus
}
#endif
components/soc/esp32p4/register/hw_ver3/soc/lp_peri_pms_struct.h
+260 -395
View File
@@ -10,497 +10,362 @@
extern "C" {
#endif
/** Group: TEE PMS DATE REG */
/** Type of pms_date register
* NA
/** Group: Version Control Registers */
/** Type of lp_peri_pms_date register
* Version control register
*/
typedef union {
struct {
/** tee_date : R/W; bitpos: [31:0]; default: 2363943;
* NA
/** lp_peri_pms_date : R/W; bitpos: [31:0]; default: 2363943;
* Version control register
*/
uint32_t tee_date:32;
uint32_t lp_peri_pms_date:32;
};
uint32_t val;
} tee_pms_date_reg_t;
} pms_lp_peri_pms_date_reg_t;
/** Group: TEE PMS CLK EN REG */
/** Type of pms_clk_en register
* NA
/** Group: Clock Gating Registers */
/** Type of lp_peri_pms_clk_en register
* Clock gating register
*/
typedef union {
struct {
/** reg_clk_en : R/W; bitpos: [0]; default: 1;
* NA
/** lp_peri_pms_clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: Enable automatic clock gating
* 1: Keep the clock always on
*/
uint32_t reg_clk_en:1;
uint32_t lp_peri_pms_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} tee_pms_clk_en_reg_t;
} pms_lp_peri_pms_clk_en_reg_t;
/** Group: TEE LP MM PMS REG0 REG */
/** Type of lp_mm_pms_reg0 register
* NA
/** Group: LP CPU Permission Control Registers */
/** Type of lp_mm_lp_peri_pms_reg0 register
* Permission control register0 for LP CPU in machine mode
*/
typedef union {
struct {
/** reg_lp_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* NA
/** lp_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP system
* registers.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_sysreg_allow:1;
/** reg_lp_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* NA
uint32_t lp_mm_lp_sysreg_allow:1;
/** lp_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP_AONCLKRST (LP
* always-on clock and reset).
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_aonclkrst_allow:1;
/** reg_lp_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* NA
uint32_t lp_mm_lp_aonclkrst_allow:1;
/** lp_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP timer.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_timer_allow:1;
/** reg_lp_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* NA
uint32_t lp_mm_lp_timer_allow:1;
/** lp_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP ANAPERI
* (analog peripherals).
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_anaperi_allow:1;
/** reg_lp_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* NA
uint32_t lp_mm_lp_anaperi_allow:1;
/** lp_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP PMU (Power
* Management Unit).
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_pmu_allow:1;
/** reg_lp_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* NA
uint32_t lp_mm_lp_pmu_allow:1;
/** lp_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP WDT (watchdog
* timer).
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_wdt_allow:1;
/** reg_lp_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* NA
uint32_t lp_mm_lp_wdt_allow:1;
/** lp_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP Mailbox
* Controller.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_mailbox_allow:1;
/** reg_lp_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* NA
uint32_t lp_mm_lp_mailbox_allow:1;
/** lp_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP RTC.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_lp_mm_lp_rtc_allow:1;
/** reg_lp_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* NA
uint32_t lp_mm_lp_rtc_allow:1;
/** lp_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP PREICLKRST
* (peripheral clock and reset).
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_periclkrst_allow:1;
/** reg_lp_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* NA
uint32_t lp_mm_lp_periclkrst_allow:1;
/** lp_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP UART.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_uart_allow:1;
/** reg_lp_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* NA
uint32_t lp_mm_lp_uart_allow:1;
/** lp_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP I2S.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_i2c_allow:1;
/** reg_lp_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* NA
uint32_t lp_mm_lp_i2c_allow:1;
/** lp_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP SPI.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_spi_allow:1;
/** reg_lp_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* NA
uint32_t lp_mm_lp_spi_allow:1;
/** lp_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP I2C master.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_i2cmst_allow:1;
/** reg_lp_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* NA
uint32_t lp_mm_lp_i2cmst_allow:1;
/** lp_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP I2S.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_i2s_allow:1;
/** reg_lp_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* NA
uint32_t lp_mm_lp_i2s_allow:1;
/** lp_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP ADC.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_adc_allow:1;
/** reg_lp_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* NA
uint32_t lp_mm_lp_adc_allow:1;
/** lp_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP touch sensor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_touch_allow:1;
/** reg_lp_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* NA
uint32_t lp_mm_lp_touch_allow:1;
/** lp_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP IO MUX.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_iomux_allow:1;
/** reg_lp_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* NA
uint32_t lp_mm_lp_iomux_allow:1;
/** lp_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP INTR
* (interrupt).
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_intr_allow:1;
/** reg_lp_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* NA
uint32_t lp_mm_lp_intr_allow:1;
/** lp_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP eFuse.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_efuse_allow:1;
/** reg_lp_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* NA
uint32_t lp_mm_lp_efuse_allow:1;
/** lp_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_pms_allow:1;
/** reg_lp_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* NA
uint32_t lp_mm_lp_pms_allow:1;
/** lp_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
* Configures whether LP CPU in machine mode has permission to access
* HP2LP_PERI_PMS_REG.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_hp2lp_pms_allow:1;
/** reg_lp_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* NA
uint32_t lp_mm_hp2lp_pms_allow:1;
/** lp_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP temperature
* sensor.
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_tsens_allow:1;
/** reg_lp_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* NA
uint32_t lp_mm_lp_tsens_allow:1;
/** lp_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP HUK (Hardware
* Unique Key).
* 0: Not allowed
* 1: Allowed
*/
uint32_t reg_lp_mm_lp_huk_allow:1;
/** reg_lp_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
* NA
uint32_t lp_mm_lp_huk_allow:1;
/** lp_mm_lp_sram_allow : R/W; bitpos: [23]; default: 1;
* Configures whether LP CPU in machine mode has permission to access LP SRAM.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_lp_mm_lp_tcm_ram_allow:1;
/** reg_lp_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1;
* NA
uint32_t lp_mm_lp_sram_allow:1;
/** lp_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1;
* Configures whether LP CPU in machine mode has permission to access RNG.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_lp_mm_lp_trng_allow:1;
uint32_t lp_mm_lp_trng_allow:1;
uint32_t reserved_25:7;
};
uint32_t val;
} tee_lp_mm_pms_reg0_reg_t;
} pms_lp_mm_lp_peri_pms_reg0_reg_t;
/** Group: TEE PERI REGION0 LOW REG */
/** Type of peri_region0_low register
* NA
/** Group: Configurable Address Range Configuration Registers */
/** Type of peri_regionn_low register
* Regionn start address configuration register
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region0_low : R/W; bitpos: [31:2]; default: 0;
* NA
/** peri_regionn_low : R/W; bitpos: [31:2]; default: 0;
* Configures the high 30 bits of the start address of peripheral register's regionn.
*/
uint32_t reg_peri_region0_low:30;
uint32_t peri_regionn_low:30;
};
uint32_t val;
} tee_peri_region0_low_reg_t;
} pms_peri_regionn_low_reg_t;
/** Group: TEE PERI REGION0 HIGH REG */
/** Type of peri_region0_high register
* NA
/** Type of peri_regionn_high register
* Regionn end address configuration register
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region0_high : R/W; bitpos: [31:2]; default: 1073741823;
* NA
/** peri_regionn_high : R/W; bitpos: [31:2]; default: 1073741823;
* Configures the high 30 bits of the end address of peripheral register's regionn.
*/
uint32_t reg_peri_region0_high:30;
uint32_t peri_regionn_high:30;
};
uint32_t val;
} tee_peri_region0_high_reg_t;
} pms_peri_regionn_high_reg_t;
/** Group: TEE PERI REGION1 LOW REG */
/** Type of peri_region1_low register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region1_low : R/W; bitpos: [31:2]; default: 0;
* NA
*/
uint32_t reg_peri_region1_low:30;
};
uint32_t val;
} tee_peri_region1_low_reg_t;
/** Group: TEE PERI REGION1 HIGH REG */
/** Type of peri_region1_high register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region1_high : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
uint32_t reg_peri_region1_high:30;
};
uint32_t val;
} tee_peri_region1_high_reg_t;
/** Group: TEE PERI REGION PMS REG */
/** Group: PMS Peripheral Region Permission Control Registers */
/** Type of peri_region_pms register
* NA
* Permission register of regions 0-1
*/
typedef union {
struct {
/** reg_lp_core_region_pms : R/W; bitpos: [1:0]; default: 3;
* NA
/** lp_core_region_pms : R/W; bitpos: [1:0]; default: 3;
* Configures whether LP core in machine mode has permission to access address region0
* and address region1. Bit0 corresponds to region0 and bit1 corresponds to region1.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_lp_core_region_pms:2;
/** reg_hp_core0_um_region_pms : R/W; bitpos: [3:2]; default: 3;
* NA
uint32_t lp_core_region_pms:2;
/** hp_core0_um_region_pms : R/W; bitpos: [3:2]; default: 3;
* Configures whether HP CPU0 in user mode has permission to access address region0
* and address region1. Bit2 corresponds to region0 and bit3 corresponds to region1.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core0_um_region_pms:2;
/** reg_hp_core0_mm_region_pms : R/W; bitpos: [5:4]; default: 3;
* NA
uint32_t hp_core0_um_region_pms:2;
/** hp_core0_mm_region_pms : R/W; bitpos: [5:4]; default: 3;
* Configures whether HP CPU0 in machine mode has permission to access address region0
* and address region1. Bit4 corresponds to region0 and bit5 corresponds to region1.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core0_mm_region_pms:2;
/** reg_hp_core1_um_region_pms : R/W; bitpos: [7:6]; default: 3;
* NA
uint32_t hp_core0_mm_region_pms:2;
/** hp_core1_um_region_pms : R/W; bitpos: [7:6]; default: 3;
* Configures whether HP CPU1 in user mode has permission to access address region0
* and address region1. Bit6 corresponds to region0 and bit7 corresponds to region1.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core1_um_region_pms:2;
/** reg_hp_core1_mm_region_pms : R/W; bitpos: [9:8]; default: 3;
* NA
uint32_t hp_core1_um_region_pms:2;
/** hp_core1_mm_region_pms : R/W; bitpos: [9:8]; default: 3;
* Configures whether HP CPU1 in machine mode has permission to access address region0
* and address region1. Bit8 corresponds to region0 and bit9 corresponds to region1.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core1_mm_region_pms:2;
uint32_t hp_core1_mm_region_pms:2;
uint32_t reserved_10:22;
};
uint32_t val;
} tee_peri_region_pms_reg_t;
} pms_peri_region_pms_reg_t;
/** Group: TEE PERI REGION 2 TO 7 PMS REG */
/** Type of peri_region_2_to_7_pms register
* NA
/** Group: PMS Peripheral Region Permission Control Registers */
/** Type of peri_region_pms register
* Permission register of regions 2-7
*/
typedef union {
struct {
/** reg_lp_core_region_2_to_7_pms : R/W; bitpos: [5:0]; default: 63;
* NA
/** lp_core_region_pms : R/W; bitpos: [5:0]; default: 63;
* Configures whether LP core in machine mode has permission to access address region2
* to region7. Bit0 corresponds to region2, bit1 to region3, ..., bit5 to region7.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_lp_core_region_2_to_7_pms:6;
/** reg_hp_core0_um_region_2_to_7_pms : R/W; bitpos: [11:6]; default: 63;
* NA
uint32_t lp_core_region_pms:6;
/** hp_core0_um_region_pms : R/W; bitpos: [11:6]; default: 63;
* Configures whether HP CPU0 in user mode has permission to access address region2
* to region7. Bit6 corresponds to region2, bit7 to region3, ..., bit11 to region7.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core0_um_region_2_to_7_pms:6;
/** reg_hp_core0_mm_region_2_to_7_pms : R/W; bitpos: [17:12]; default: 63;
* NA
uint32_t hp_core0_um_region_pms:6;
/** hp_core0_mm_region_pms : R/W; bitpos: [17:12]; default: 63;
* Configures whether HP CPU0 in machine mode has permission to access address region2
* to region7. Bit12 corresponds to region2, bit13 to region3, ..., bit17 to region7.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core0_mm_region_2_to_7_pms:6;
/** reg_hp_core1_um_region_2_to_7_pms : R/W; bitpos: [23:18]; default: 63;
* NA
uint32_t hp_core0_mm_region_pms:6;
/** hp_core1_um_region_pms : R/W; bitpos: [23:18]; default: 63;
* Configures whether HP CPU1 in user mode has permission to access address region2
* to region7. Bit18 corresponds to region2, bit19 to region3, ..., bit23 to region7.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core1_um_region_2_to_7_pms:6;
/** reg_hp_core1_mm_region_2_to_7_pms : R/W; bitpos: [29:24]; default: 63;
* NA
uint32_t hp_core1_um_region_pms:6;
/** hp_core1_mm_region_pms : R/W; bitpos: [29:24]; default: 63;
* Configures whether HP CPU1 in machine mode has permission to access address region2
* to region7. Bit24 corresponds to region2, bit25 to region3, ..., bit29 to region7.
* 0: Not allowed
* 1: Allow
*/
uint32_t reg_hp_core1_mm_region_2_to_7_pms:6;
uint32_t hp_core1_mm_region_pms:6;
uint32_t reserved_30:2;
};
uint32_t val;
} tee_peri_region_2_to_7_pms_reg_t;
/** Group: TEE PERI REGION2 LOW REG */
/** Type of peri_region2_low register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region2_low : R/W; bitpos: [31:2]; default: 0;
* NA
*/
uint32_t reg_peri_region2_low:30;
};
uint32_t val;
} tee_peri_region2_low_reg_t;
/** Group: TEE PERI REGION2 HIGH REG */
/** Type of peri_region2_high register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region2_high : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
uint32_t reg_peri_region2_high:30;
};
uint32_t val;
} tee_peri_region2_high_reg_t;
/** Group: TEE PERI REGION3 LOW REG */
/** Type of peri_region3_low register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region3_low : R/W; bitpos: [31:2]; default: 0;
* NA
*/
uint32_t reg_peri_region3_low:30;
};
uint32_t val;
} tee_peri_region3_low_reg_t;
/** Group: TEE PERI REGION3 HIGH REG */
/** Type of peri_region3_high register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region3_high : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
uint32_t reg_peri_region3_high:30;
};
uint32_t val;
} tee_peri_region3_high_reg_t;
/** Group: TEE PERI REGION4 LOW REG */
/** Type of peri_region4_low register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region4_low : R/W; bitpos: [31:2]; default: 0;
* NA
*/
uint32_t reg_peri_region4_low:30;
};
uint32_t val;
} tee_peri_region4_low_reg_t;
/** Group: TEE PERI REGION4 HIGH REG */
/** Type of peri_region4_high register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region4_high : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
uint32_t reg_peri_region4_high:30;
};
uint32_t val;
} tee_peri_region4_high_reg_t;
/** Group: TEE PERI REGION5 LOW REG */
/** Type of peri_region5_low register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region5_low : R/W; bitpos: [31:2]; default: 0;
* NA
*/
uint32_t reg_peri_region5_low:30;
};
uint32_t val;
} tee_peri_region5_low_reg_t;
/** Group: TEE PERI REGION5 HIGH REG */
/** Type of peri_region5_high register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region5_high : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
uint32_t reg_peri_region5_high:30;
};
uint32_t val;
} tee_peri_region5_high_reg_t;
/** Group: TEE PERI REGION6 LOW REG */
/** Type of peri_region6_low register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region6_low : R/W; bitpos: [31:2]; default: 0;
* NA
*/
uint32_t reg_peri_region6_low:30;
};
uint32_t val;
} tee_peri_region6_low_reg_t;
/** Group: TEE PERI REGION6 HIGH REG */
/** Type of peri_region6_high register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region6_high : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
uint32_t reg_peri_region6_high:30;
};
uint32_t val;
} tee_peri_region6_high_reg_t;
/** Group: TEE PERI REGION7 LOW REG */
/** Type of peri_region7_low register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region7_low : R/W; bitpos: [31:2]; default: 0;
* NA
*/
uint32_t reg_peri_region7_low:30;
};
uint32_t val;
} tee_peri_region7_low_reg_t;
/** Group: TEE PERI REGION7 HIGH REG */
/** Type of peri_region7_high register
* NA
*/
typedef union {
struct {
uint32_t reserved_0:2;
/** reg_peri_region7_high : R/W; bitpos: [31:2]; default: 1073741823;
* NA
*/
uint32_t reg_peri_region7_high:30;
};
uint32_t val;
} tee_peri_region7_high_reg_t;
} pms_peri_region_pms_2_to_7_reg_t;
typedef struct {
volatile tee_pms_date_reg_t pms_date;
volatile tee_pms_clk_en_reg_t pms_clk_en;
volatile tee_lp_mm_pms_reg0_reg_t lp_mm_pms_reg0;
volatile tee_peri_region0_low_reg_t peri_region0_low;
volatile tee_peri_region0_high_reg_t peri_region0_high;
volatile tee_peri_region1_low_reg_t peri_region1_low;
volatile tee_peri_region1_high_reg_t peri_region1_high;
volatile tee_peri_region_pms_reg_t peri_region_pms;
volatile tee_peri_region_2_to_7_pms_reg_t peri_region_2_to_7_pms;
volatile tee_peri_region2_low_reg_t peri_region2_low;
volatile tee_peri_region2_high_reg_t peri_region2_high;
volatile tee_peri_region3_low_reg_t peri_region3_low;
volatile tee_peri_region3_high_reg_t peri_region3_high;
volatile tee_peri_region4_low_reg_t peri_region4_low;
volatile tee_peri_region4_high_reg_t peri_region4_high;
volatile tee_peri_region5_low_reg_t peri_region5_low;
volatile tee_peri_region5_high_reg_t peri_region5_high;
volatile tee_peri_region6_low_reg_t peri_region6_low;
volatile tee_peri_region6_high_reg_t peri_region6_high;
volatile tee_peri_region7_low_reg_t peri_region7_low;
volatile tee_peri_region7_high_reg_t peri_region7_high;
} tee_dev_t;
volatile pms_lp_peri_pms_date_reg_t lp_peri_pms_date;
volatile pms_lp_peri_pms_clk_en_reg_t lp_peri_pms_clk_en;
volatile pms_lp_mm_lp_peri_pms_reg0_reg_t lp_mm_lp_peri_pms_reg0;
volatile pms_peri_regionn_low_reg_t peri_region0_low;
volatile pms_peri_regionn_high_reg_t peri_region0_high;
volatile pms_peri_regionn_low_reg_t peri_region1_low;
volatile pms_peri_regionn_high_reg_t peri_region1_high;
volatile pms_peri_region_pms_reg_t peri_region_pms;
volatile pms_peri_region_pms_2_to_7_reg_t peri_region_2_to_7_pms;
volatile pms_peri_regionn_low_reg_t peri_region2_low;
volatile pms_peri_regionn_high_reg_t peri_region2_high;
volatile pms_peri_regionn_low_reg_t peri_region3_low;
volatile pms_peri_regionn_high_reg_t peri_region3_high;
volatile pms_peri_regionn_low_reg_t peri_region4_low;
volatile pms_peri_regionn_high_reg_t peri_region4_high;
volatile pms_peri_regionn_low_reg_t peri_region5_low;
volatile pms_peri_regionn_high_reg_t peri_region5_high;
volatile pms_peri_regionn_low_reg_t peri_region6_low;
volatile pms_peri_regionn_high_reg_t peri_region6_high;
volatile pms_peri_regionn_low_reg_t peri_region7_low;
volatile pms_peri_regionn_high_reg_t peri_region7_high;
} lp_peri_pms_dev_t;
extern tee_dev_t LP_PERI_PMS;
extern lp_peri_pms_dev_t LP_PERI_PMS;
#ifndef __cplusplus
_Static_assert(sizeof(tee_dev_t) == 0x54, "Invalid size of tee_dev_t structure");
_Static_assert(sizeof(lp_peri_pms_dev_t) == 0x54, "Invalid size of lp_peri_pms_dev_t structure");
#endif
#ifdef __cplusplus