Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 11:10:54 +03:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'fix/fix_esp32s31_secureboot_fastwake' into 'master'

Browse Source 
fix(esp_system): support rom secure boot fast wake feature for esp32s31

Closes PM-832

See merge request espressif/esp-idf!51265
This commit is contained in:
Jiang Jiang Jian
2026-07-31 14:12:25 +08:00
parent e85b99fc49 e1d60fb89f
commit 3808652972
16 changed files with 98 additions and 84 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_system/ld/esp32c5/memory.ld.in
+1 -1
View File
@@ -93,7 +93,7 @@ MEMORY
* - Bootloader retain memory (for reboot counter, OTA info, etc.)
*
* +-----------------------------+ 0x50004000 (LP RAM end)
* | Secure Boot Image Digest | ( For ROM using, must keep it at the end ESP_SECURE_BOOT_DIGEST_LEN bytes of LP RAM)
* | Secure Boot Image Digest | ( For ROM using, must keep it at the end CONFIG_SECURE_BOOT_ROM_FAST_WAKE_RESERVE_SIZE bytes of LP RAM)
* | for fast wake secure boot. |
* |(only if CONFIG_SECURE_BOOT) |
* |- - - - - - - - - - - - - - -|
components/esp_system/ld/esp32c6/memory.ld.in
+1 -1
View File
@@ -95,7 +95,7 @@ MEMORY
*
* +-----------------------------+ 0x50004000 (LP RAM end)
* | Secure Boot Image Digest |
* | for fast wake secure boot. | ( For ROM using, must keep it at the end 32 bytes of LP RAM)
* | for fast wake secure boot. | ( For ROM using, must keep it at the end CONFIG_SECURE_BOOT_ROM_FAST_WAKE_RESERVE_SIZE bytes of LP RAM)
* |(only if CONFIG_SECURE_BOOT) |
* |- - - - - - - - - - - - - - -|
* | bootloader_data_rtc_mem |
components/esp_system/ld/esp32h2/memory.ld.in
+1 -1
View File
@@ -91,7 +91,7 @@ MEMORY
*
* +-----------------------------+ 0x50001000 (LP RAM end)
* | Secure Boot Image Digest |
* | for fast wake secure boot. | ( For ROM using, must keep it at the end 32 bytes of LP RAM)
* | for fast wake secure boot. | ( For ROM using, must keep it at the end CONFIG_SECURE_BOOT_ROM_FAST_WAKE_RESERVE_SIZE bytes of LP RAM)
* |(only if CONFIG_SECURE_BOOT) |
* |- - - - - - - - - - - - - - -|
* | bootloader_data_rtc_mem |
components/esp_system/ld/esp32h21/memory.ld.in
+1 -1
View File
@@ -74,7 +74,7 @@ MEMORY
*
* +-----------------------------+ 0x50001000 (LP RAM end)
* | Secure Boot Image Digest |
* | for fast wake secure boot. | ( For ROM using, must keep it at the end 32 bytes of LP RAM)
* | for fast wake secure boot. | ( For ROM using, must keep it at the end CONFIG_SECURE_BOOT_ROM_FAST_WAKE_RESERVE_SIZE bytes of LP RAM)
* |(only if CONFIG_SECURE_BOOT) |
* |- - - - - - - - - - - - - - -|
* | bootloader_data_rtc_mem |
components/esp_system/ld/esp32s31/memory.ld.in
+36
View File
@@ -64,6 +64,42 @@ MEMORY
/* (See irom_seg for meaning of 0x20 offset in the above.) */
#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
/**
* LP RAM (RTC Memory) Layout for ESP32-S31
* Total Size: 32KB (0x8000)
* Address Range: 0x2E000000 - 0x2E008000
*
* ESP32-S31 has only unified LP RAM (no separate RTC FAST/SLOW).
* The LP RAM persists over deep sleep and is used for:
* - ULP coprocessor code and data (optional)
* - RTC wake stub code and data
* - Data that needs to survive deep sleep
* - Bootloader retain memory (for reboot counter, OTA info, etc.)
*
* +-----------------------------+ 0x2E008000 (LP RAM end)
* | Secure Boot Image Digest | ( For ROM using, must keep it at the end CONFIG_SECURE_BOOT_ROM_FAST_WAKE_RESERVE_SIZE bytes of LP RAM)
* | for fast wake secure boot. |
* |(only if CONFIG_SECURE_BOOT) |
* |- - - - - - - - - - - - - - -|
* | bootloader_data_rtc_mem |
* | (ESP_BOOTLOADER_RESERVE_RTC)| lp_reserved_seg (RESERVE_RTC_MEM)
* |- - - - - - - - - - - - - - -|
* | rtc_timer_data_in_rtc_mem |
* | (RTC_TIMER_RESERVE_RTC=24B) |
* +-----------------------------+ 0x2E008000 - RESERVE_RTC_MEM
* | .rtc.force_slow |
* | .rtc_noinit (NOLOAD) |
* | .rtc.bss (NOLOAD) |
* | .rtc.data | lp_ram_seg (= rtc_iram_seg = rtc_data_seg = rtc_slow_seg)
* | .rtc.force_fast |
* |- - - - - - - - - - - - - - -|
* | .rtc.text | RTC wake stub code
* +-----------------------------+ 0x2E000000 + CONFIG_ULP_COPROC_RESERVE_MEM (if ULP enabled)
* | ULP Coprocessor Reserve | (Optional, CONFIG_ULP_COPROC_RESERVE_MEM)
* | (code + data) |
* +-----------------------------+ 0x2E000000 (LP RAM start)
*/
/**
* lp ram memory (RWX). Persists over deep sleep.
*/
components/esp_system/ld/ld.common
+4 -11
View File
@@ -11,13 +11,6 @@
/* CPU instruction prefetch padding size for flash mmap scenario */
#define _esp_flash_mmap_prefetch_pad_size 16
/* Copy from esp_secure_boot.h */
#ifdef CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
#define ESP_SECURE_BOOT_DIGEST_LEN 48
#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define ESP_SECURE_BOOT_DIGEST_LEN 32
#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
/*
* PMP region granularity size
* Software may determine the PMP granularity by writing zero to pmp0cfg, then writing all ones
@@ -76,11 +69,11 @@
/* RTC Reserved is placed before ULP memory, expand it to make sure the ULP start address
has the required alignment */
#define ULP_ALIGNMENT_REQ_BYTES 256
#define RESERVE_RTC_MEM ALIGN_UP(ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC, ULP_ALIGNMENT_REQ_BYTES)
#elif CONFIG_SECURE_BOOT && CONFIG_ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
#define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC + ESP_SECURE_BOOT_DIGEST_LEN)
#define RESERVE_RTC_MEM ALIGN_UP(ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC \
+ CONFIG_SECURE_BOOT_ROM_FAST_WAKE_RESERVE_SIZE, ULP_ALIGNMENT_REQ_BYTES)
#else
#define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC)
#define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC \
+ CONFIG_SECURE_BOOT_ROM_FAST_WAKE_RESERVE_SIZE)
#endif
#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
components/esp_system/ld/ld.rtc.sections
+9
View File
@@ -147,11 +147,20 @@
*/
*(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*))
_bootloader_data_rtc_mem_end = ABSOLUTE(.);
/* ROM keeps the verified image digest in the last bytes of RTC RAM */
. = . + CONFIG_SECURE_BOOT_ROM_FAST_WAKE_RESERVE_SIZE;
#endif // CONFIG_IDF_TARGET_ESP32P4
_rtc_reserved_end = ABSOLUTE(.);
} > rtc_reserved_seg
#if CONFIG_SECURE_BOOT_ROM_FAST_WAKE_RESERVE_SIZE > 0
ASSERT((_bootloader_data_rtc_mem_end == ORIGIN(rtc_reserved_seg) + LENGTH(rtc_reserved_seg)
- CONFIG_SECURE_BOOT_ROM_FAST_WAKE_RESERVE_SIZE),
"The ROM secure boot fast wake up digest must occupy the last bytes of RTC RAM, and the bootloader retain mem must end where it begins. bootloader_common_get_rtc_retain_mem() computes that address.")
#endif
_rtc_ulp_memory_start = _rtc_reserved_start + LENGTH(rtc_reserved_seg);
_rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start;
ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)),