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feat(driver_spi): support esp32h4 spi driver

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This commit is contained in:
wanckl
2025-08-05 15:08:02 +08:00
committed by Wan Lei
parent 72cb973022
commit 37c6608ab3
54 changed files with 1716 additions and 231 deletions
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components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+36
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@@ -47,6 +47,10 @@ config SOC_RMT_SUPPORTED
bool
default y
config SOC_GPSPI_SUPPORTED
bool
default y
config SOC_I2C_SUPPORTED
bool
default y
@@ -551,6 +555,38 @@ config SOC_SPI_MAX_CS_NUM
int
default 6
config SOC_SPI_MAXIMUM_BUFFER_SIZE
int
default 64
config SOC_SPI_SUPPORT_DDRCLK
bool
default y
config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
bool
default y
config SOC_SPI_SUPPORT_CD_SIG
bool
default y
config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
bool
default y
config SOC_SPI_SUPPORT_SLAVE_HD_VER2
bool
default y
config SOC_SPI_SUPPORT_CLK_XTAL
bool
default y
config SOC_SPI_SUPPORT_CLK_RC_FAST
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
components/soc/esp32h4/include/soc/clk_tree_defs.h
+3 -3
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@@ -240,15 +240,15 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of SPI
*/
#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
#define SOC_SPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F48M,SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of SPI clock source.
*/
typedef enum {
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_48M as SPI source clock */
SPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_48M as SPI source clock */
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select XTAL as SPI source clock */
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
SPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_48M as SPI source clock */
SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */
} soc_periph_spi_clk_src_t;
components/soc/esp32h4/include/soc/retention_periph_defs.h
+8 -6
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@@ -46,14 +46,15 @@ typedef enum periph_retention_module {
SLEEP_RETENTION_MODULE_TWAI0 = 22,
SLEEP_RETENTION_MODULE_PARLIO0 = 23,
SLEEP_RETENTION_MODULE_GPSPI2 = 24,
SLEEP_RETENTION_MODULE_LEDC = 25,
SLEEP_RETENTION_MODULE_PCNT0 = 26,
SLEEP_RETENTION_MODULE_MCPWM0 = 27,
SLEEP_RETENTION_MODULE_GPSPI3 = 25,
SLEEP_RETENTION_MODULE_LEDC = 26,
SLEEP_RETENTION_MODULE_PCNT0 = 27,
SLEEP_RETENTION_MODULE_MCPWM0 = 28,
/* Modem module, which includes BLE and 802.15.4 */
SLEEP_RETENTION_MODULE_BLE_MAC = 28,
SLEEP_RETENTION_MODULE_BT_BB = 29,
SLEEP_RETENTION_MODULE_802154_MAC = 30,
SLEEP_RETENTION_MODULE_BLE_MAC = 29,
SLEEP_RETENTION_MODULE_BT_BB = 30,
SLEEP_RETENTION_MODULE_802154_MAC = 31,
SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1
} periph_retention_module_t;
@@ -83,6 +84,7 @@ typedef enum periph_retention_module {
: ((m) == SLEEP_RETENTION_MODULE_TWAI0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_PARLIO0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_GPSPI2) ? true \
: ((m) == SLEEP_RETENTION_MODULE_GPSPI3) ? true \
: ((m) == SLEEP_RETENTION_MODULE_LEDC) ? true \
: ((m) == SLEEP_RETENTION_MODULE_PCNT0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_MCPWM0) ? true \
components/soc/esp32h4/include/soc/soc_caps.h
+10 -12
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@@ -57,7 +57,7 @@
#define SOC_I2S_SUPPORTED 1
#define SOC_RMT_SUPPORTED 1
// #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12348
// #define SOC_GPSPI_SUPPORTED 1 // TODO: [ESP32H4] IDF-12362 IDF-12364 IDF-12366
#define SOC_GPSPI_SUPPORTED 1
// #define SOC_LEDC_SUPPORTED 1 // TODO: [ESP32H4] IDF-12343
#define SOC_I2C_SUPPORTED 1
#define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32H4] IDF-12375 IDF-12377
@@ -404,18 +404,16 @@
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 3
#define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3))
#define SOC_SPI_MAX_CS_NUM 6
#define SOC_SPI_MAX_CS_NUM 6
// #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
// #define SOC_SPI_SUPPORT_DDRCLK 1
// #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
// #define SOC_SPI_SUPPORT_CD_SIG 1
// #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
// #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
// #define SOC_SPI_SUPPORT_CLK_XTAL 1
// #define SOC_SPI_SUPPORT_CLK_PLL_F80M 1
// #define SOC_SPI_SUPPORT_CLK_RC_FAST 1
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define SOC_SPI_SUPPORT_DDRCLK 1
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
#define SOC_SPI_SUPPORT_CLK_XTAL 1
#define SOC_SPI_SUPPORT_CLK_RC_FAST 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
components/soc/esp32h4/include/soc/spi_pins.h
-1
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@@ -6,7 +6,6 @@
#pragma once
// TODO: [ESP32H4] IDF-12388
#define MSPI_FUNC_NUM 0
#define MSPI_IOMUX_PIN_NUM_CS0 7
#define MSPI_IOMUX_PIN_NUM_CS1 6