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change(esp_hw_support): fix wifi mac rx buffer link exception caused by pll clock

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This commit is contained in:
Li Shuai
2025-01-17 17:16:39 +08:00
parent 2fce894c82
commit 377914d579
3 changed files with 32 additions and 8 deletions
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components/esp_system/port/soc/esp32c5/clk.c
+7 -8
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@@ -23,6 +23,7 @@
#include "esp_cpu.h"
#include "hal/efuse_hal.h"
#include "hal/wdt_hal.h"
#include "hal/clk_tree_ll.h"
#if SOC_MODEM_CLOCK_SUPPORTED
#include "hal/modem_lpcon_ll.h"
#endif
@@ -222,14 +223,12 @@ __attribute__((weak)) void esp_perip_clk_init(void)
modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
#endif
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
/* On ESP32-C5 ECO1, clearing BIT(31) of PCR_FPGA_DEBUG_REG is used to fix
* the issue where the modem module fails to transmit and receive packets
* due to the loss of the modem root clock caused by automatic clock gating
* during soc root clock source switching. For detailed information, refer
* to IDF-11064. */
REG_CLR_BIT(PCR_FPGA_DEBUG_REG, BIT(31));
}
/* On ESP32-C5 ECO1, clearing BIT(31) of PCR_FPGA_DEBUG_REG is used to fix
* the issue where the modem module fails to transmit and receive packets
* due to the loss of the modem root clock caused by automatic clock gating
* during soc root clock source switching. For detailed information, refer
* to IDF-11064. */
clk_ll_soc_root_clk_auto_gating_bypass(true);
ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");
#if 0 // TODO: [ESP32C5] IDF-8844