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Merge branch 'fix/esp32p4_v3_lp_peri_pmp_entry_v6.0' into 'release/v6.0'

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fix(esp_hw_support): Add PMP entry for the LP peripherals region (v6.0)

See merge request espressif/esp-idf!46386
This commit is contained in:
Mahavir Jain
2026-03-21 12:23:48 +05:30
parent 2498e4903b 4143547196
commit 372d0b2c28
1 changed files with 6 additions and 2 deletions
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components/esp_hw_support/port/esp32p4/cpu_region_protect.c
+6 -2
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@@ -209,7 +209,7 @@ static void esp_cpu_configure_region_protection_rev_v3(void)
PMP_RESET_AND_ENTRY_SET(27, pmpaddr27, PMP_NAPOT | RW);
_Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
// 9. LP memory
// 9. LP memory and LP peripherals
#if CONFIG_ESP_SYSTEM_MEMPROT && CONFIG_ESP_SYSTEM_MEMPROT_PMP && !BOOTLOADER_BUILD
extern int _rtc_text_start;
extern int _rtc_text_end;
@@ -224,11 +224,15 @@ static void esp_cpu_configure_region_protection_rev_v3(void)
PMP_RESET_AND_ENTRY_SET(29, (int)&_rtc_text_start, PMP_TOR | RW);
#endif
PMP_RESET_AND_ENTRY_SET(30, (int)&_rtc_text_end, PMP_TOR | RX);
PMP_RESET_AND_ENTRY_SET(31, SOC_RTC_IRAM_HIGH, PMP_TOR | RW);
// LP peripherals are contiguous with LP memory; this entry covers both with R/W
PMP_RESET_AND_ENTRY_SET(31, SOC_LP_PERIPH_HIGH, PMP_TOR | RW);
#else
const uint32_t pmpaddr28 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH);
PMP_RESET_AND_ENTRY_SET(28, pmpaddr28, PMP_NAPOT | CONDITIONAL_RWX);
_Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region");
PMP_ENTRY_SET(29, SOC_LP_PERIPH_LOW, NONE);
PMP_ENTRY_SET(30, SOC_LP_PERIPH_HIGH, PMP_TOR | CONDITIONAL_RW);
#endif
}
#else