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refactor(esp_hw_support): changed reserved interrupt functions to be now defined per SoC

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This commit is contained in:
Omar Chebib
2024-05-30 11:49:13 +08:00
parent 8cd37950c7
commit 35dd4e1557
12 changed files with 395 additions and 180 deletions
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components/esp_hw_support/cpu.c
+1 -179
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -144,184 +144,6 @@ void esp_cpu_wait_for_intr(void)
#endif // __XTENSA__
}
/* -------------------------------------------------- CPU Registers ----------------------------------------------------
*
* ------------------------------------------------------------------------------------------------------------------ */
/* ------------------------------------------------- CPU Interrupts ----------------------------------------------------
*
* ------------------------------------------------------------------------------------------------------------------ */
// ---------------- Interrupt Descriptors ------------------
#if SOC_CPU_HAS_FLEXIBLE_INTC
#if SOC_INT_CLIC_SUPPORTED
static bool is_intr_num_resv(int ext_intr_num) {
/* On targets that uses CLIC as the interrupt controller, the first 16 lines (0..15) are reserved for software
* interrupts, all the other lines starting from 16 and above can be used by external peripheral.
* in the case of this function, the parameter only refers to the external peripheral index, so if
* `ext_intr_num` is 0, it refers to interrupt index 16.
*
* Only interrupt line 6 is reserved at the moment since it is used for disabling interrupts */
return ext_intr_num == 6;
}
#else // !SOC_INT_CLIC_SUPPORTED
static bool is_intr_num_resv(int intr_num)
{
// Workaround to reserve interrupt number 1 for Wi-Fi, 5,8 for Bluetooth, 6 for "permanently disabled interrupt"
// [TODO: IDF-2465]
uint32_t reserved = BIT(1) | BIT(5) | BIT(6) | BIT(8);
// int_num 0,3,4,7 are unavailable for PULP cpu
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2// TODO: IDF-5728 replace with a better macro name
reserved |= BIT(0) | BIT(3) | BIT(4) | BIT(7);
#endif
if (reserved & BIT(intr_num)) {
return true;
}
extern int _vector_table;
extern int _interrupt_handler;
const intptr_t pc = (intptr_t)(&_vector_table + intr_num);
/* JAL instructions are relative to the PC there are executed from. */
const intptr_t destination = pc + riscv_decode_offset_from_jal_instruction(pc);
return destination != (intptr_t)&_interrupt_handler;
}
#endif // SOC_INT_CLIC_SUPPORTED
void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
{
intr_desc_ret->priority = 1; //Todo: We should make this -1
intr_desc_ret->type = ESP_CPU_INTR_TYPE_NA;
#if __riscv
intr_desc_ret->flags = is_intr_num_resv(intr_num) ? ESP_CPU_INTR_DESC_FLAG_RESVD : 0;
#else
intr_desc_ret->flags = 0;
#endif
}
#else // SOC_CPU_HAS_FLEXIBLE_INTC
typedef struct {
int priority;
esp_cpu_intr_type_t type;
uint32_t flags[SOC_CPU_CORES_NUM];
} intr_desc_t;
#if SOC_CPU_CORES_NUM > 1
// Note: We currently only have dual core targets, so the table initializer is hard coded
const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //0
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //1
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //2
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //3
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, //4
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //5
#if CONFIG_FREERTOS_CORETIMER_0
{ 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //6
#else
{ 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //6
#endif
{ 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //7
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //8
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //9
{ 1, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, //10
{ 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //11
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0} }, //12
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0} }, //13
{ 7, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //14, NMI
#if CONFIG_FREERTOS_CORETIMER_1
{ 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //15
#else
{ 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //15
#endif
{ 5, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //16
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //17
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //18
{ 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //19
{ 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //20
{ 2, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //21
{ 3, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, //22
{ 3, ESP_CPU_INTR_TYPE_LEVEL, { 0, 0 } }, //23
{ 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, 0 } }, //24
{ 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //25
{ 5, ESP_CPU_INTR_TYPE_LEVEL, { 0, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //26
{ 3, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //27
{ 4, ESP_CPU_INTR_TYPE_EDGE, { 0, 0 } }, //28
{ 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL, ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //29
{ 4, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //30
{ 5, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD, ESP_CPU_INTR_DESC_FLAG_RESVD } }, //31
};
#else // SOC_CPU_CORES_NUM > 1
const static intr_desc_t intr_desc_table [SOC_CPU_INTR_NUM] = {
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //0
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //1
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //2
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //3
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //4
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //5
#if CONFIG_FREERTOS_CORETIMER_0
{ 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //6
#else
{ 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //6
#endif
{ 1, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //7
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //8
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //9
{ 1, ESP_CPU_INTR_TYPE_EDGE, { 0 } }, //10
{ 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //11
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //12
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //13
{ 7, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //14, NMI
#if CONFIG_FREERTOS_CORETIMER_1
{ 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //15
#else
{ 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //15
#endif
{ 5, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //16
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //17
{ 1, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //18
{ 2, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //19
{ 2, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //20
{ 2, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //21
{ 3, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //22
{ 3, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //23
{ 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //24
{ 4, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //25
{ 5, ESP_CPU_INTR_TYPE_LEVEL, { 0 } }, //26
{ 3, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //27
{ 4, ESP_CPU_INTR_TYPE_EDGE, { 0 } }, //28
{ 3, ESP_CPU_INTR_TYPE_NA, { ESP_CPU_INTR_DESC_FLAG_SPECIAL } }, //29
{ 4, ESP_CPU_INTR_TYPE_EDGE, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //30
{ 5, ESP_CPU_INTR_TYPE_LEVEL, { ESP_CPU_INTR_DESC_FLAG_RESVD } }, //31
};
#endif // SOC_CPU_CORES_NUM > 1
void esp_cpu_intr_get_desc(int core_id, int intr_num, esp_cpu_intr_desc_t *intr_desc_ret)
{
assert(core_id >= 0 && core_id < SOC_CPU_CORES_NUM);
#if SOC_CPU_CORES_NUM == 1
core_id = 0; //If this is a single core target, hard code CPU ID to 0
#endif
intr_desc_ret->priority = intr_desc_table[intr_num].priority;
intr_desc_ret->type = intr_desc_table[intr_num].type;
intr_desc_ret->flags = intr_desc_table[intr_num].flags[core_id];
}
#endif // SOC_CPU_HAS_FLEXIBLE_INTC
/* ---------------------------------------------------- Debugging ------------------------------------------------------
*
* ------------------------------------------------------------------------------------------------------------------ */