Merge branch 'lld_orphan' into 'master'

esp_system: enable linking with LLD on RISC-V targets

Closes LLVM-216

See merge request espressif/esp-idf!48712

components/bootloader/subproject/main/ld/bootloader.sections.common.ld

@@ -100,6 +100,8 @@ SECTIONS
     KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
     KEEP (*(SORT(.ctors.*)))
     KEEP (*(.ctors))
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*)))
+    KEEP (*(.init_array))
     __init_array_end = ABSOLUTE(.);
     KEEP (*crtbegin.*(.dtors))
     KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
@@ -153,6 +155,8 @@ SECTIONS
    */
   /DISCARD/ : { *(.rela.*) }
 
+#include "ld.elf.internal.sections"
+
   /**
    * This section is not included in the binary image; it is only present in the ELF file.
    * It is used to keep certain symbols in the ELF file.

components/esp_system/ld/ld.debug.sections

@@ -70,6 +70,7 @@
   .note.GNU-stack     0 : { *(.note.GNU-stack) }
 
   .riscv.attributes   0 : { *(.riscv.attributes) }
+#include "ld.elf.internal.sections"
 
 /**
  * .xt.prop and .xt.lit sections will be used by the debugger and disassembler

components/esp_system/ld/ld.discard.sections

@@ -15,6 +15,8 @@
 #endif // CONFIG_LIBC_NEWLIB
 
    *(.fini)
+   *(.fini_array)
+   *(.fini_array.*)
 #if CONFIG_IDF_TARGET_ARCH_XTENSA
    *(.eh_frame_hdr)
 #endif // CONFIG_IDF_TARGET_ARCH_XTENSA

components/esp_system/ld/ld.elf.internal.sections

@@ -0,0 +1,8 @@
+  /**
+   * Linker-generated ELF sections. Must be explicitly placed in linker scripts
+   * when using ld.lld with --orphan-handling=warn/error. GNU ld special-cases
+   * these sections; ld.lld does not.
+   */
+  .symtab             0 : { *(.symtab) }
+  .strtab             0 : { *(.strtab) }
+  .shstrtab           0 : { *(.shstrtab) }

components/esp_tee/subproject/main/arch/riscv/esp_tee_vector_table_clic.S

@@ -17,11 +17,16 @@
     #define ASTDBG_ISR _tee_ns_intr_handler
 #endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD
 
-    .section .exception_vectors_table.text
+    .section .exception_vectors_table.text, "ax"
 
     /* Prevent the compiler from generating 2-byte instruction in the vector tables */
     .option push
     .option norvc
+    /* The vector tables have a fixed layout, so keep linker relaxation from
+     * touching them: with relaxation enabled the assembler emits the .balign
+     * padding as R_RISCV_ALIGN-managed bytes, of which GNU ld may retain more
+     * than the exact amount, changing the table size between builds. */
+    .option norelax
 
     /**
      * Non-hardware vectored interrupt entry. MTVEC CSR points here.

components/esp_tee/subproject/main/ld/elf_misc.ld.in

@@ -56,6 +56,7 @@
 
   .comment 0 : { *(.comment) }
   .note.GNU-stack 0: { *(.note.GNU-stack) }
+#include "ld.elf.internal.sections"
 
 #if CONFIG_IDF_TARGET_ARCH_RISCV
   .riscv.attributes 0: { *(.riscv.attributes) }
@@ -70,5 +71,18 @@
     */
    *(.rela.*)
    *(.got .got.plt) /* TODO: GCC-382 */
+
+   /**
+    * GNU ld removes them via --gc-sections; LLD treats them as GC roots,
+    * so they must be discarded explicitly to not trip --orphan-handling=error.
+    */
+   *(.init)
+   *(.init_array)
+   *(.init_array.*)
+   *(.fini)
+   *(.fini_array)
+   *(.fini_array.*)
+   *(.eh_frame_hdr)
+   *(.eh_frame)
   }
 #endif

components/esp_tee/subproject/main/ld/esp_tee_ld.cmake

@@ -18,11 +18,13 @@ target_linker_script(${COMPONENT_LIB} INTERFACE "${heap_dir}/port/${target}/ld/$
 
 file(MAKE_DIRECTORY "${CMAKE_CURRENT_BINARY_DIR}/ld")
 
+idf_component_get_property(esp_system_dir esp_system COMPONENT_DIR)
+
 # Preprocess esp_tee.ld.in linker script to include configuration, becomes esp_tee.ld
 add_custom_command(
     OUTPUT ${ld_output}
     COMMAND "${CMAKE_C_COMPILER}" -C -P -x c -E -o ${ld_output} -I ${config_dir}
-            -I "${CMAKE_CURRENT_LIST_DIR}" ${ld_input}
+            -I "${CMAKE_CURRENT_LIST_DIR}" -I "${esp_system_dir}/ld" ${ld_input}
     MAIN_DEPENDENCY ${ld_input}
     DEPENDS ${sdkconfig_header}
     COMMENT "Generating esp_tee.ld linker script..."

components/riscv/vectors_clic.S

@@ -29,11 +29,16 @@
     .global _interrupt_handler
     .global _panic_handler
 
-    .section .exception_vectors_table.text
+    .section .exception_vectors_table.text, "ax"
 
     /* Prevent the compiler from generating 2-byte instruction in the vector tables */
     .option push
     .option norvc
+    /* The vector tables have a fixed layout, so keep linker relaxation from
+     * touching them: with relaxation enabled the assembler emits the .balign
+     * padding as R_RISCV_ALIGN-managed bytes, of which GNU ld may retain more
+     * than the exact amount, changing the table size between builds. */
+    .option norelax
 
     /**
      * Non-hardware vectored interrupt entry. MTVEC CSR points here.