feat(phy): add check for required clock bits during phy enable

components/esp_hw_support/periph_ctrl.c

@@ -10,6 +10,7 @@
 #ifdef __PERIPH_CTRL_ALLOW_LEGACY_API
 #include "hal/clk_gate_ll.h"
 #endif
+#include "esp_log.h"
 
 // TODO: [ESP32C61] IDF-9513, modem support
 #if SOC_MODEM_CLOCK_IS_INDEPENDENT && SOC_MODEM_CLOCK_SUPPORTED
@@ -211,4 +212,23 @@ IRAM_ATTR void phy_module_disable(void)
     portEXIT_CRITICAL_SAFE(&periph_spinlock);
 #endif
 }
+
+IRAM_ATTR bool phy_module_has_clock_bits(uint32_t mask)
+{
+    uint32_t val = 0;
+#if SOC_MODEM_CLOCK_IS_INDEPENDENT
+    val = modem_clock_module_bits_get(PERIPH_PHY_MODULE);
+#else
+#if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED
+    val = DPORT_REG_READ(periph_ll_get_clk_en_reg(PERIPH_WIFI_BT_COMMON_MODULE));
+#else
+    return true;
+#endif
+#endif
+    if ((val & mask) != mask) {
+        ESP_LOGW("periph_ctrl", "phy module clock bits 0x%x, required 0x%x", val, mask);
+        return false;
+    }
+    return true;
+}
 #endif  //#if SOC_BT_SUPPORTED || SOC_WIFI_SUPPORTED || SOC_IEEE802154_SUPPORTED