From 335fd1c24f804656c4897f4b7f7bc4c6d3583f6e Mon Sep 17 00:00:00 2001 From: Renz Bagaporo Date: Fri, 22 May 2026 09:59:07 +0900 Subject: [PATCH] fix(esp_system): configure ESP32-H4 ICACHE1_USAGE in app startup Configure the ESP32-H4 ICACHE1_USAGE SRAM ownership bit during app startup instead of relying on the value left by the bootloader. Clear ICACHE1_USAGE before external memory/cache setup so single-core apps can reclaim the ICACHE1 SRAM region as RAM. For multicore apps, set the bit again when applying multicore cache settings so the region is assigned back to ICACHE1. This keeps the app behavior aligned with its own single-core or multicore configuration even when bootloader and app configs differ. --- components/esp_system/port/cpu_start.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 752e9eef304..f4fd9e92cfe 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -63,6 +63,7 @@ #elif CONFIG_IDF_TARGET_ESP32H21 #include "esp_memprot.h" #elif CONFIG_IDF_TARGET_ESP32H4 +#include "soc/lp_aon_reg.h" #include "esp_memprot.h" #elif CONFIG_IDF_TARGET_ESP32S31 #endif @@ -374,6 +375,12 @@ void IRAM_ATTR do_multicore_settings(void) restore_app_mmu_from_pro_mmu(); #endif +#if CONFIG_IDF_TARGET_ESP32H4 + // Reassign Layer6 memory to ICache1 for multicore apps before enabling + // cache settings for the other cores. + REG_SET_BIT(LP_AON_SRAM_USAGE_CONF_REG, LP_AON_ICACHE1_USAGE); +#endif + cache_bus_mask_t cache_bus_mask_core0 = cache_ll_l1_get_enabled_bus(0); #ifndef CONFIG_IDF_TARGET_ESP32 // 1. disable the cache before changing its settings. @@ -489,6 +496,12 @@ FORCE_INLINE_ATTR IRAM_ATTR void ram_app_init(void) //Keep this static, the compiler will check output parameters are initialized. FORCE_INLINE_ATTR IRAM_ATTR void ext_mem_init(void) { +#if CONFIG_IDF_TARGET_ESP32H4 + // Initially assign Layer6 memory to CPU RAM. Multicore startup will + // reassign it to ICache1 if the app is not configured for single-core mode. + REG_CLR_BIT(LP_AON_SRAM_USAGE_CONF_REG, LP_AON_ICACHE1_USAGE); +#endif + #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE // It helps to fix missed cache settings for other cores. It happens when bootloader is unicore. do_multicore_settings();