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feat(mailbox): define and implement a mailbox API with hardware and software support
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -522,6 +522,11 @@ FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_intr_status(pmu_dev_t *hw)
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hw->hp_ext.int_clr.reject = 1;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_enable_sw_intr(pmu_dev_t *hw, bool enable)
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{
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hw->hp_ext.int_ena.sw = enable;
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}
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FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_wakeup_cause(pmu_dev_t *hw)
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{
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return hw->wakeup.status0;
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@@ -703,6 +708,16 @@ FORCE_INLINE_ATTR void pmu_ll_lp_clear_intsts_mask(pmu_dev_t *hw, uint32_t mask)
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hw->lp_ext.int_clr.val = mask;
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}
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FORCE_INLINE_ATTR void pmu_ll_lp_trigger_sw_intr(pmu_dev_t *hw)
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{
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hw->hp_lp_cpu_comm.lp_trigger_hp = 1;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_trigger_sw_intr(pmu_dev_t *hw)
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{
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hw->hp_lp_cpu_comm.hp_trigger_lp = 1;
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}
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FORCE_INLINE_ATTR void pmu_ll_lp_clear_sw_intr_status(pmu_dev_t *hw)
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{
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hw->lp_ext.int_clr.sw_trigger = 1;
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