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Merge branch 'refactor/rcc_atomic_usage' into 'master'

Browse Source 
refactor(rcc): unify the usage of clock control macros for peripherals

See merge request espressif/esp-idf!45283
This commit is contained in:
morris
2026-01-25 18:53:34 +08:00
parent 201ca7d00a 0469db2f83
commit 31fd511523
77 changed files with 212 additions and 551 deletions
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components/app_trace/port/port_uart.c
+7 -7
View File
@@ -11,19 +11,19 @@
#include "esp_log.h"
#include "esp_cpu.h"
#include "esp_attr.h"
#include "esp_private/uart_share_hw_ctrl.h"
#include "hal/uart_hal.h"
#include "hal/gpio_hal.h"
#include "driver/uart.h"
#include "hal/uart_periph.h"
#include "esp_clk_tree.h"
#include "esp_private/esp_clk_tree_common.h"
#include "soc/gpio_periph.h"
#include "esp_rom_gpio.h"
#include "hal/uart_ll.h"
#include "esp_intr_alloc.h"
#include "esp_heap_caps.h"
#include "esp_private/esp_clk_tree_common.h"
#include "esp_private/esp_gpio_reserve.h"
#include "esp_private/periph_ctrl.h"
#include "esp_app_trace_port.h"
#include "esp_app_trace_util.h"
@@ -244,11 +244,11 @@ static esp_err_t esp_apptrace_uart_init(void *hw_data, const esp_apptrace_config
uart_data->hal_ctx.dev = UART_LL_GET_HW(uart_config->uart_num);
HP_UART_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_ll_enable_bus_clock(uart_config->uart_num, true);
uart_ll_reset_register(uart_config->uart_num);
}
HP_UART_SRC_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_ll_sclk_enable(uart_data->hal_ctx.dev);
}
@@ -260,7 +260,7 @@ static esp_err_t esp_apptrace_uart_init(void *hw_data, const esp_apptrace_config
/* Initialize UART HAL (sets default 8N1 mode) */
uart_hal_init(&uart_data->hal_ctx, uart_config->uart_num);
HP_UART_SRC_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_hal_set_sclk(&uart_data->hal_ctx, UART_SCLK_DEFAULT);
uart_hal_set_baudrate(&uart_data->hal_ctx, uart_config->baud_rate, sclk_hz);
}
@@ -338,10 +338,10 @@ err_alloc_msg_buff:
heap_caps_free(uart_data->tx_ring.buffer);
err_init_ring_buff:
esp_clk_tree_enable_src(UART_SCLK_DEFAULT, false);
HP_UART_SRC_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_ll_sclk_disable(uart_data->hal_ctx.dev);
}
HP_UART_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_ll_enable_bus_clock(uart_config->uart_num, false);
}
esp_gpio_revoke(gpio_mask);
components/driver/i2c/i2c.c
+8 -20
View File
@@ -115,18 +115,6 @@ static const char *I2C_TAG = "i2c";
#endif
#define I2C_MEM_ALLOC_CAPS_DEFAULT MALLOC_CAP_DEFAULT
#if SOC_PERIPH_CLK_CTRL_SHARED
#define I2C_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define I2C_CLOCK_SRC_ATOMIC()
#endif
#if !SOC_RCC_IS_INDEPENDENT
#define I2C_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define I2C_RCC_ATOMIC()
#endif
#define I2C_CLR_BUS_TIMEOUT_MS (50) // 50ms is sufficient for clearing the bus
/**
@@ -269,7 +257,7 @@ static void i2c_hw_disable(i2c_port_t i2c_num)
{
I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock));
if (i2c_context[i2c_num].hw_enabled != false) {
I2C_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_ll_enable_bus_clock(i2c_num, false);
}
i2c_context[i2c_num].hw_enabled = false;
@@ -281,7 +269,7 @@ static void i2c_hw_enable(i2c_port_t i2c_num)
{
I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock));
if (i2c_context[i2c_num].hw_enabled != true) {
I2C_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_ll_enable_bus_clock(i2c_num, true);
i2c_ll_reset_register(i2c_num);
}
@@ -420,7 +408,7 @@ esp_err_t i2c_driver_install(i2c_port_t i2c_num, i2c_mode_t mode, size_t slv_rx_
return ESP_FAIL;
}
i2c_hw_enable(i2c_num);
I2C_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_hal_init(&i2c_context[i2c_num].hal, i2c_num);
}
//Disable I2C interrupt.
@@ -542,7 +530,7 @@ esp_err_t i2c_driver_delete(i2c_port_t i2c_num)
}
#endif
I2C_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_hal_deinit(&i2c_context[i2c_num].hal);
}
free(p_i2c_obj[i2c_num]);
@@ -827,7 +815,7 @@ esp_err_t i2c_param_config(i2c_port_t i2c_num, const i2c_config_t *i2c_conf)
return ret;
}
i2c_hw_enable(i2c_num);
I2C_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_hal_init(&i2c_context[i2c_num].hal, i2c_num);
}
I2C_ENTER_CRITICAL(&(i2c_context[i2c_num].spinlock));
@@ -837,7 +825,7 @@ esp_err_t i2c_param_config(i2c_port_t i2c_num, const i2c_config_t *i2c_conf)
if (i2c_conf->mode == I2C_MODE_SLAVE) { //slave mode
i2c_hal_slave_init(&(i2c_context[i2c_num].hal));
i2c_ll_slave_enable_auto_start(i2c_context[i2c_num].hal.dev, true);
I2C_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_ll_set_source_clk(i2c_context[i2c_num].hal.dev, src_clk);
}
i2c_ll_set_slave_addr(i2c_context[i2c_num].hal.dev, i2c_conf->slave.slave_addr, i2c_conf->slave.addr_10bit_en);
@@ -851,12 +839,12 @@ esp_err_t i2c_param_config(i2c_port_t i2c_num, const i2c_config_t *i2c_conf)
#endif // SOC_I2C_SUPPORT_SLAVE
{
i2c_hal_master_init(&(i2c_context[i2c_num].hal));
I2C_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_ll_set_source_clk(i2c_context[i2c_num].hal.dev, src_clk);
}
//Default, we enable hardware filter
i2c_ll_master_set_filter(i2c_context[i2c_num].hal.dev, I2C_FILTER_CYC_NUM_DEF);
I2C_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_hal_set_bus_timing(&(i2c_context[i2c_num].hal), i2c_conf->master.clk_speed, src_clk, s_get_src_clk_freq(src_clk));
}
}
components/driver/test_apps/legacy_i2c_driver/main/test_i2c.c
+2 -3
View File
@@ -15,7 +15,6 @@
#include "esp_system.h"
#include "soc/uart_struct.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/uart_share_hw_ctrl.h"
#include "esp_rom_gpio.h"
#include "hal/gpio_types.h"
#include "hal/uart_ll.h"
@@ -680,7 +679,7 @@ static void uart_aut_baud_det_init(int rxd_io_num)
gpio_set_direction(rxd_io_num, GPIO_MODE_INPUT_OUTPUT);
esp_rom_gpio_connect_out_signal(rxd_io_num, i2c_periph_signal[0].scl_out_sig, 0, 0);
esp_rom_gpio_connect_in_signal(rxd_io_num, UART_PERIPH_SIGNAL(1, SOC_UART_PERIPH_SIGNAL_RX), 0);
HP_UART_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_ll_enable_bus_clock(1, true);
uart_ll_reset_register(1);
}
@@ -715,7 +714,7 @@ static void i2c_scl_freq_cal(void)
printf("\nSCL high period %.3f (us), SCL low_period %.3f (us)\n\n", (float)(i2c_cource_clk_period * high_period_cnt), (float)(i2c_cource_clk_period * low_period_cnt));
uart_ll_set_autobaud_en(&UART1, false);
HP_UART_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_ll_enable_bus_clock(1, false);
}
}
components/driver/twai/twai.c
+5 -17
View File
@@ -58,18 +58,6 @@
#define ALERT_LOG_LEVEL_WARNING TWAI_ALERT_ARB_LOST //Alerts above and including this level use ESP_LOGW
#define ALERT_LOG_LEVEL_ERROR TWAI_ALERT_TX_FAILED //Alerts above and including this level use ESP_LOGE
#if !SOC_RCC_IS_INDEPENDENT
#define TWAI_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define TWAI_RCC_ATOMIC()
#endif
#if SOC_PERIPH_CLK_CTRL_SHARED
#define TWAI_PERI_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define TWAI_PERI_ATOMIC()
#endif
#define TWAI_USE_RETENTION_LINK (SOC_TWAI_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
/* ------------------ Typedefs, structures, and variables ------------------- */
@@ -232,7 +220,7 @@ static void twai_intr_handler_main(void *arg)
if (events & TWAI_HAL_EVENT_NEED_PERIPH_RESET) {
ESP_EARLY_LOGD(TWAI_TAG, "Triggered peripheral reset");
twai_hal_prepare_for_reset(p_twai_obj->hal);
TWAI_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
twai_ll_reset_register(p_twai_obj->controller_id);
}
twai_hal_recover_from_reset(p_twai_obj->hal);
@@ -547,11 +535,11 @@ esp_err_t twai_driver_install_v2(const twai_general_config_t *g_config, const tw
portEXIT_CRITICAL(&g_spinlock);
//Enable TWAI peripheral register clock
TWAI_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
twai_ll_enable_bus_clock(controller_id, true);
twai_ll_reset_register(controller_id);
}
TWAI_PERI_ATOMIC() {
PERIPH_RCC_ATOMIC() {
//Enable functional clock
twai_ll_set_clock_source(p_twai_obj->controller_id, clk_src);
twai_ll_enable_clock(p_twai_obj->controller_id, true);
@@ -622,10 +610,10 @@ esp_err_t twai_driver_uninstall_v2(twai_handle_t handle)
//Clear registers by reading
twai_hal_deinit(p_twai_obj->hal);
TWAI_PERI_ATOMIC() {
PERIPH_RCC_ATOMIC() {
twai_ll_enable_clock(controller_id, false);
}
TWAI_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
twai_ll_enable_bus_clock(controller_id, false);
}
components/esp_driver_bitscrambler/src/bitscrambler.c
+4 -11
View File
@@ -21,13 +21,6 @@ static const char *TAG = "bitscrambler";
#define BITSCRAMBLER_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
#endif
#if !SOC_RCC_IS_INDEPENDENT
// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
#define BS_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define BS_RCC_ATOMIC()
#endif
#define BITSCRAMBLER_BINARY_VER 1 //max version we're compatible with
#define BITSCRAMBLER_HW_REV 0
@@ -71,7 +64,7 @@ static bool claim_channel(bitscrambler_direction_t dir)
{
int old_use_count = atomic_fetch_add(&group_ref_count, 1);
if (old_use_count == 0) {
BS_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
// This is the first client using the module, so we need to enable the sys clock
bitscrambler_ll_set_bus_clock_sys_enable(true);
bitscrambler_ll_reset_sys();
@@ -84,7 +77,7 @@ static bool claim_channel(bitscrambler_direction_t dir)
if (old_val) {
goto err;
} else {
BS_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
bitscrambler_ll_set_bus_clock_tx_enable(true);
bitscrambler_ll_reset_tx();
}
@@ -94,7 +87,7 @@ static bool claim_channel(bitscrambler_direction_t dir)
if (old_val) {
goto err;
} else {
BS_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
bitscrambler_ll_set_bus_clock_rx_enable(true);
bitscrambler_ll_reset_rx();
}
@@ -117,7 +110,7 @@ static void release_channel(bitscrambler_direction_t dir)
int old_use_count = atomic_fetch_sub(&group_ref_count, 1);
if (old_use_count == 1) {
// This is the last client using the module, so we need to disable the sys clock
BS_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
bitscrambler_ll_set_bus_clock_sys_enable(false);
bitscrambler_ll_mem_force_power_off();
}
components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c
+3 -9
View File
@@ -37,12 +37,6 @@
#define DVP_CAM_BK_BUFFER_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA)
#endif
#if SOC_PERIPH_CLK_CTRL_SHARED
#define DVP_CAM_CLK_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define DVP_CAM_CLK_ATOMIC()
#endif
#if CAM_LL_DATA_WIDTH_MAX
#define CAP_DVP_PERIPH_NUM CAM_LL_PERIPH_NUM /*!< DVP port number */
#define CAM_DVP_DATA_SIG_NUM CAM_LL_DATA_WIDTH_MAX /*!< DVP data bus width of CAM */
@@ -363,7 +357,7 @@ esp_err_t esp_cam_ctlr_dvp_init(int ctlr_id, cam_clock_source_t clk_src, const e
}
ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true));
DVP_CAM_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
cam_ll_enable_clk(ctlr_id, true);
cam_ll_select_clk_src(ctlr_id, clk_src);
};
@@ -394,7 +388,7 @@ esp_err_t esp_cam_ctlr_dvp_output_clock(int ctlr_id, cam_clock_source_t clk_src,
ESP_LOGD(TAG, "DVP clock source frequency %" PRIu32 "Hz", src_clk_hz);
if ((src_clk_hz % xclk_freq) == 0) {
DVP_CAM_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
// The camera sensors require precision without frequency and duty cycle jitter,
// so the fractional divisor can't be used.
cam_ll_set_group_clock_coeff(ctlr_id, src_clk_hz / xclk_freq, 0, 0);
@@ -456,7 +450,7 @@ esp_err_t esp_cam_ctlr_dvp_deinit(int ctlr_id)
{
ESP_RETURN_ON_FALSE(ctlr_id < CAP_DVP_PERIPH_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid argument: ctlr_id >= %d", CAP_DVP_PERIPH_NUM);
DVP_CAM_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
cam_ll_enable_clk(ctlr_id, false);
};
components/esp_driver_dma/src/dw_gdma.c
+2 -9
View File
@@ -34,13 +34,6 @@
ESP_LOG_ATTR_TAG(TAG, "dw-gdma");
#if !SOC_RCC_IS_INDEPENDENT
// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
#define DW_GDMA_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define DW_GDMA_RCC_ATOMIC()
#endif
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
#define DW_GDMA_GET_NON_CACHE_ADDR(addr) ((addr) ? CACHE_LL_L2MEM_NON_CACHE_ADDR(addr) : 0)
#define DW_GDMA_GET_CACHE_ADDRESS(nc_addr) ((nc_addr) ? CACHE_LL_L2MEM_CACHE_ADDR(nc_addr) : 0)
@@ -116,7 +109,7 @@ static dw_gdma_group_t *dw_gdma_acquire_group_handle(int group_id)
new_group = true;
s_platform.groups[group_id] = group;
// enable APB to access DMA registers
DW_GDMA_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
dw_gdma_ll_enable_bus_clock(group_id, true);
dw_gdma_ll_reset_register(group_id);
}
@@ -157,7 +150,7 @@ static void dw_gdma_release_group_handle(dw_gdma_group_t *group)
s_platform.groups[group_id] = NULL;
// deinitialize the HAL context
dw_gdma_hal_deinit(&group->hal);
DW_GDMA_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
dw_gdma_ll_enable_bus_clock(group_id, false);
}
}
components/esp_driver_gptimer/src/gptimer.c
+1 -1
View File
@@ -201,7 +201,7 @@ esp_err_t gptimer_del_timer(gptimer_handle_t timer)
timer_hal_context_t *hal = &timer->hal;
ESP_LOGD(TAG, "del timer (%d,%d)", group_id, timer_id);
// disable the source clock
GPTIMER_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
timer_ll_enable_clock(group_id, hal->timer_id, false);
}
timer_hal_deinit(hal);
components/esp_driver_gptimer/src/gptimer_common.c
+1 -1
View File
@@ -143,7 +143,7 @@ esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t s
// !!! HARDWARE SHARED RESOURCE !!!
// on some ESP chip, different peripheral's clock source setting are mixed in the same register
// so we need to make this done in an atomic way
GPTIMER_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
timer_ll_set_clock_source(group_id, timer_id, src_clk);
timer_ll_enable_clock(group_id, timer_id, true);
}
components/esp_driver_gptimer/src/gptimer_priv.h
-6
View File
@@ -54,12 +54,6 @@ extern "C" {
#define GPTIMER_USE_RETENTION_LINK (SOC_TIMER_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
#if SOC_PERIPH_CLK_CTRL_SHARED
#define GPTIMER_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define GPTIMER_CLOCK_SRC_ATOMIC()
#endif
///!< Logging settings
#define TAG "gptimer"
components/esp_driver_i2c/i2c_common.c
+5 -5
View File
@@ -113,21 +113,21 @@ static esp_err_t s_i2c_bus_handle_acquire(i2c_port_num_t port_num, i2c_bus_handl
// Enable the I2C module
if (!bus->is_lp_i2c) {
I2C_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_ll_enable_bus_clock(bus->port_num, true);
i2c_ll_reset_register(bus->port_num);
}
}
#if SOC_LP_I2C_SUPPORTED
else {
LP_I2C_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
lp_i2c_ll_enable_bus_clock(bus->port_num - SOC_HP_I2C_NUM, true);
lp_i2c_ll_reset_register(bus->port_num - SOC_HP_I2C_NUM);
}
}
#endif
I2C_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_hal_init(&bus->hal, port_num);
}
}
@@ -217,13 +217,13 @@ esp_err_t i2c_release_bus_handle(i2c_bus_handle_t i2c_bus)
#endif
// Disable I2C module
if (!i2c_bus->is_lp_i2c) {
I2C_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_ll_enable_bus_clock(port_num, false);
}
}
#if SOC_LP_I2C_SUPPORTED
else {
LP_I2C_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
lp_i2c_ll_enable_bus_clock(port_num - SOC_HP_I2C_NUM, false);
}
}
components/esp_driver_i2c/i2c_master.c
+6 -6
View File
@@ -123,13 +123,13 @@ static esp_err_t s_i2c_hw_fsm_reset(i2c_master_bus_handle_t i2c_master, bool cle
if (clear_bus) {
ret = s_i2c_master_clear_bus(i2c_master->base);
}
I2C_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_ll_reset_register(i2c_master->base->port_num);
}
i2c_hal_master_init(hal);
// Restore the clock source here.
I2C_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_ll_set_source_clk(hal->dev, i2c_master->base->clk_src);
}
i2c_ll_enable_fifo_mode(hal->dev, true);
@@ -696,7 +696,7 @@ static esp_err_t s_i2c_transaction_start(i2c_master_dev_handle_t i2c_dev, int xf
i2c_master->read_len_static = 0;
i2c_master->read_buf_pos = 0;
I2C_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_hal_set_bus_timing(hal, i2c_dev->scl_speed_hz, i2c_master->base->clk_src, i2c_master->base->clk_src_freq_hz);
}
@@ -1061,7 +1061,7 @@ esp_err_t i2c_new_master_bus(const i2c_master_bus_config_t *bus_config, i2c_mast
ESP_GOTO_ON_ERROR(i2c_param_master_config(i2c_master->base, bus_config), err, TAG, "i2c configure parameter failed");
if (!i2c_master->base->is_lp_i2c) {
I2C_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_ll_set_source_clk(hal->dev, i2c_master->base->clk_src);
}
}
@@ -1080,7 +1080,7 @@ esp_err_t i2c_new_master_bus(const i2c_master_bus_config_t *bus_config, i2c_mast
ESP_GOTO_ON_FALSE(lp_clock_match, ESP_ERR_NOT_SUPPORTED, err, TAG, "the clock source does not support lp i2c, please check");
LP_I2C_SRC_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
lp_i2c_ll_set_source_clk(hal->dev, i2c_master->base->clk_src);
}
}
@@ -1385,7 +1385,7 @@ esp_err_t i2c_master_probe(i2c_master_bus_handle_t bus_handle, uint16_t address,
// I2C probe does not have i2c device module. So set the clock parameter independently
// This will not influence device transaction.
I2C_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_ll_set_source_clk(hal->dev, bus_handle->base->clk_src);
i2c_hal_set_bus_timing(hal, 100000, bus_handle->base->clk_src, bus_handle->base->clk_src_freq_hz);
}
components/esp_driver_i2c/i2c_private.h
-17
View File
@@ -25,23 +25,6 @@
extern "C" {
#endif
#if SOC_PERIPH_CLK_CTRL_SHARED
#define I2C_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define I2C_CLOCK_SRC_ATOMIC()
#endif
#if !SOC_RCC_IS_INDEPENDENT
#define I2C_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define I2C_RCC_ATOMIC()
#endif
#if SOC_LP_I2C_SUPPORTED
#define LP_I2C_SRC_CLK_ATOMIC() PERIPH_RCC_ATOMIC()
#define LP_I2C_BUS_CLK_ATOMIC() PERIPH_RCC_ATOMIC()
#endif
#ifdef CONFIG_I2C_MASTER_ISR_HANDLER_IN_IRAM
#define I2C_MASTER_ISR_ATTR IRAM_ATTR
#else
components/esp_driver_i2c/i2c_slave.c
+1 -1
View File
@@ -305,7 +305,7 @@ esp_err_t i2c_new_slave_device(const i2c_slave_config_t *slave_config, i2c_slave
i2c_ll_set_slave_addr(hal->dev, slave_config->slave_addr, false);
i2c_ll_set_tout(hal->dev, I2C_LL_MAX_TIMEOUT);
I2C_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_ll_set_source_clk(hal->dev, slave_config->clk_source);
}
bool addr_10bit_en = slave_config->addr_bit_len != I2C_ADDR_BIT_LEN_7;
components/esp_driver_i2s/i2s_common.c
+3 -3
View File
@@ -1079,7 +1079,7 @@ esp_err_t i2s_del_channel(i2s_chan_handle_t handle)
bool is_bound = true;
#if SOC_I2S_HW_VERSION_2
I2S_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
if (dir == I2S_DIR_TX) {
i2s_ll_tx_disable_clock(handle->controller->hal.dev);
} else {
@@ -1092,7 +1092,7 @@ esp_err_t i2s_del_channel(i2s_chan_handle_t handle)
/* Must switch back to D2CLK on ESP32-S2,
* because the clock of some registers are bound to APLL,
* otherwise, once APLL is disabled, the registers can't be updated anymore */
I2S_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
if (handle->dir == I2S_DIR_TX) {
i2s_ll_tx_clk_set_src(handle->controller->hal.dev, I2S_CLK_SRC_DEFAULT);
} else {
@@ -1481,7 +1481,7 @@ esp_err_t i2s_channel_tune_rate(i2s_chan_handle_t handle, const i2s_tuning_confi
return ESP_ERR_INVALID_ARG;
}
/* Set the new divider for MCLK */
I2S_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
if (handle->dir == I2S_DIR_TX) {
i2s_ll_tx_set_mclk(handle->controller->hal.dev, &mclk_div);
#if SOC_I2S_HW_VERSION_2
components/esp_driver_i2s/i2s_pdm.c
+4 -4
View File
@@ -85,7 +85,7 @@ static esp_err_t i2s_pdm_tx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_tx
hal_utils_clk_div_t ret_mclk_div = {};
portENTER_CRITICAL(&g_i2s.spinlock);
/* Set clock configurations in HAL*/
I2S_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2s_hal_set_tx_clock(&handle->controller->hal, &clk_info, clk_cfg->clk_src, &ret_mclk_div);
}
#if SOC_I2S_HW_VERSION_2
@@ -184,7 +184,7 @@ static esp_err_t i2s_pdm_tx_set_gpio(i2s_chan_handle_t handle, const i2s_pdm_tx_
i2s_gpio_check_and_set(handle, gpio_cfg->clk, i2s_periph_signal[id].m_tx_ws_sig, false, gpio_cfg->invert_flags.clk_inv);
}
#if SOC_I2S_HW_VERSION_2
I2S_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2s_ll_mclk_bind_to_tx_clk(handle->controller->hal.dev);
}
#endif
@@ -422,7 +422,7 @@ static esp_err_t i2s_pdm_rx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_rx
hal_utils_clk_div_t ret_mclk_div = {};
portENTER_CRITICAL(&g_i2s.spinlock);
/* Set clock configurations in HAL*/
I2S_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2s_hal_set_rx_clock(&handle->controller->hal, &clk_info, clk_cfg->clk_src, &ret_mclk_div);
}
portEXIT_CRITICAL(&g_i2s.spinlock);
@@ -517,7 +517,7 @@ static esp_err_t i2s_pdm_rx_set_gpio(i2s_chan_handle_t handle, const i2s_pdm_rx_
}
}
#if SOC_I2S_HW_VERSION_2
I2S_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2s_ll_mclk_bind_to_rx_clk(handle->controller->hal.dev);
}
#endif
components/esp_driver_i2s/i2s_platform.c
+4 -4
View File
@@ -41,7 +41,7 @@ esp_err_t i2s_platform_acquire_occupation(i2s_ctlr_t type, int id, const char *c
if ((!g_i2s.controller[id]) && (g_i2s.comp_name[id] == NULL)) {
g_i2s.comp_name[id] = comp_name;
/* Enable module clock */
I2S_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2s_ll_enable_bus_clock(id, true);
i2s_ll_reset_register(id);
i2s_ll_enable_core_clock(I2S_LL_GET_HW(id), true);
@@ -58,7 +58,7 @@ esp_err_t i2s_platform_acquire_occupation(i2s_ctlr_t type, int id, const char *c
if ((!g_i2s.lp_controller[id]) && (g_i2s.lp_comp_name[id] == NULL)) {
g_i2s.lp_comp_name[id] = comp_name;
/* Enable module clock */
I2S_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
lp_i2s_ll_enable_module_clock(id, true);
lp_i2s_ll_reset_module_clock(id);
lp_i2s_ll_enable_rx_module_clock(id, true);
@@ -86,7 +86,7 @@ esp_err_t i2s_platform_release_occupation(i2s_ctlr_t type, int id)
if (!g_i2s.controller[id]) {
g_i2s.comp_name[id] = NULL;
/* Disable module clock */
I2S_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2s_ll_enable_bus_clock(id, false);
i2s_ll_enable_core_clock(I2S_LL_GET_HW(id), false);
}
@@ -101,7 +101,7 @@ esp_err_t i2s_platform_release_occupation(i2s_ctlr_t type, int id)
if (!g_i2s.lp_controller[id]) {
g_i2s.lp_comp_name[id] = NULL;
/* Disable module clock */
I2S_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
lp_i2s_ll_enable_module_clock(id, false);
lp_i2s_ll_enable_rx_module_clock(id, false);
}
components/esp_driver_i2s/i2s_private.h
-12
View File
@@ -50,18 +50,6 @@ extern "C" {
#endif //CONFIG_I2S_ISR_IRAM_SAFE
#define I2S_DMA_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_8BIT)
#if SOC_PERIPH_CLK_CTRL_SHARED
#define I2S_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define I2S_CLOCK_SRC_ATOMIC()
#endif
#if !SOC_RCC_IS_INDEPENDENT
#define I2S_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define I2S_RCC_ATOMIC()
#endif
#define I2S_USE_RETENTION_LINK (SOC_HAS(PAU) && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
#define I2S_NULL_POINTER_CHECK(tag, p) ESP_RETURN_ON_FALSE((p), ESP_ERR_INVALID_ARG, tag, "input parameter '"#p"' is NULL")
components/esp_driver_i2s/i2s_std.c
+5 -5
View File
@@ -88,7 +88,7 @@ static esp_err_t i2s_std_set_clock(i2s_chan_handle_t handle, const i2s_std_clk_c
hal_utils_clk_div_t ret_mclk_div = {};
portENTER_CRITICAL(&g_i2s.spinlock);
/* Set clock configurations in HAL*/
I2S_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
if (handle->dir == I2S_DIR_TX) {
i2s_hal_set_tx_clock(&handle->controller->hal, &clk_info, clk_cfg->clk_src, &ret_mclk_div);
} else {
@@ -190,21 +190,21 @@ static esp_err_t i2s_std_set_gpio(i2s_chan_handle_t handle, const i2s_std_gpio_c
/* Bind the MCLK signal to the TX or RX clock source */
if (!handle->controller->full_duplex) {
if (handle->dir == I2S_DIR_TX) {
I2S_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2s_ll_mclk_bind_to_tx_clk(handle->controller->hal.dev);
}
} else {
I2S_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2s_ll_mclk_bind_to_rx_clk(handle->controller->hal.dev);
}
}
} else if (handle->role == I2S_ROLE_MASTER) {
if (handle->dir == I2S_DIR_TX) {
I2S_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2s_ll_mclk_bind_to_tx_clk(handle->controller->hal.dev);
}
} else {
I2S_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2s_ll_mclk_bind_to_rx_clk(handle->controller->hal.dev);
}
}
components/esp_driver_i2s/i2s_tdm.c
+5 -5
View File
@@ -85,7 +85,7 @@ static esp_err_t i2s_tdm_set_clock(i2s_chan_handle_t handle, const i2s_tdm_clk_c
hal_utils_clk_div_t ret_mclk_div = {};
portENTER_CRITICAL(&g_i2s.spinlock);
/* Set clock configurations in HAL*/
I2S_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
if (handle->dir == I2S_DIR_TX) {
i2s_hal_set_tx_clock(&handle->controller->hal, &clk_info, clk_cfg->clk_src, &ret_mclk_div);
} else {
@@ -203,21 +203,21 @@ static esp_err_t i2s_tdm_set_gpio(i2s_chan_handle_t handle, const i2s_tdm_gpio_c
/* Bind the MCLK signal to the TX or RX clock source */
if (!handle->controller->full_duplex) {
if (handle->dir == I2S_DIR_TX) {
I2S_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2s_ll_mclk_bind_to_tx_clk(handle->controller->hal.dev);
}
} else {
I2S_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2s_ll_mclk_bind_to_rx_clk(handle->controller->hal.dev);
}
}
} else if (handle->role == I2S_ROLE_MASTER) {
if (handle->dir == I2S_DIR_TX) {
I2S_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2s_ll_mclk_bind_to_tx_clk(handle->controller->hal.dev);
}
} else {
I2S_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2s_ll_mclk_bind_to_rx_clk(handle->controller->hal.dev);
}
}
components/esp_driver_i3c/i3c_master.c
+3 -3
View File
@@ -730,11 +730,11 @@ esp_err_t i3c_new_master_bus(const i3c_master_bus_config_t *bus_config, i3c_mast
i3c_master_hal_init(&i3c_master_handle->hal, i3c_master_handle->i3c_num);
/// clock enable
I3C_MASTER_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i3c_master_ll_enable_bus_clock(i3c_master_handle->hal.dev, true);
i3c_master_ll_reset_register(i3c_master_handle->hal.dev);
}
I3C_MASTER_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i3c_master_ll_enable_controller_clock(i3c_master_handle->hal.dev, true);
}
@@ -743,7 +743,7 @@ esp_err_t i3c_new_master_bus(const i3c_master_bus_config_t *bus_config, i3c_mast
i3c_master_handle->clock_source = bus_config->clock_source;
esp_clk_tree_enable_src((soc_module_clk_t)i3c_master_handle->clock_source, true);
I3C_MASTER_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i3c_master_ll_set_source_clk(i3c_master_handle->hal.dev, i3c_master_handle->clock_source);
}
components/esp_driver_i3c/i3c_master_private.h
-12
View File
@@ -40,18 +40,6 @@ extern "C" {
// interface between i3c and dma need 4 bytes aligned.
#define I3C_MASTER_DMA_INTERFACE_ALIGNMENT (4)
#if SOC_PERIPH_CLK_CTRL_SHARED
#define I3C_MASTER_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define I3C_MASTER_CLOCK_SRC_ATOMIC()
#endif
#if !SOC_RCC_IS_INDEPENDENT
#define I3C_MASTER_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define I3C_MASTER_RCC_ATOMIC()
#endif
#if CONFIG_I3C_MASTER_ISR_CACHE_SAFE
#define I3C_MASTER_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
#else
components/esp_driver_ledc/src/ledc.c
+3 -15
View File
@@ -47,18 +47,6 @@ static __attribute__((unused)) const char *LEDC_TAG = "ledc";
#define LEDC_CLK_SRC_FREQ_PRECISION ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX
#endif
#if !SOC_RCC_IS_INDEPENDENT
#define LEDC_BUS_CLOCK_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define LEDC_BUS_CLOCK_ATOMIC()
#endif
#if SOC_PERIPH_CLK_CTRL_SHARED
#define LEDC_FUNC_CLOCK_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define LEDC_FUNC_CLOCK_ATOMIC()
#endif
#define LEDC_USE_RETENTION_LINK (SOC_LEDC_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
typedef enum {
@@ -428,12 +416,12 @@ static bool ledc_speed_mode_ctx_create(ledc_mode_t speed_mode)
ledc_obj_t *ledc_new_mode_obj = (ledc_obj_t *) heap_caps_calloc(1, sizeof(ledc_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
if (ledc_new_mode_obj) {
new_ctx = true;
LEDC_BUS_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
ledc_ll_enable_bus_clock(true);
ledc_ll_enable_reset_reg(false);
}
// Enable core clock gating at early stage, some LEDC registers and gamma RAM rely on the LEDC core clock existence
LEDC_FUNC_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
ledc_ll_enable_clock(LEDC_LL_GET_HW(), true);
}
ledc_hal_init(&(ledc_new_mode_obj->ledc_hal), speed_mode);
@@ -711,7 +699,7 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
// TODO: release old glb_clk (if not UNINIT), and acquire new glb_clk [clk_tree]
p_ledc_obj[speed_mode]->glb_clk = glb_clk;
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)glb_clk, true), LEDC_TAG, "clock source enable failed");
LEDC_FUNC_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
ledc_hal_set_slow_clk_sel(&(p_ledc_obj[speed_mode]->ledc_hal), glb_clk);
}
}
components/esp_driver_mcpwm/src/mcpwm_com.c
+6 -18
View File
@@ -10,18 +10,6 @@
#include "esp_private/periph_ctrl.h"
#include "esp_private/rtc_clk.h"
#if SOC_PERIPH_CLK_CTRL_SHARED
#define MCPWM_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define MCPWM_CLOCK_SRC_ATOMIC()
#endif
#if !SOC_RCC_IS_INDEPENDENT
#define MCPWM_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define MCPWM_RCC_ATOMIC()
#endif
#if MCPWM_USE_RETENTION_LINK
static esp_err_t mcpwm_create_sleep_retention_link_cb(void *arg);
#endif
@@ -67,14 +55,14 @@ mcpwm_group_t *mcpwm_acquire_group_handle(int group_id)
}
#endif // MCPWM_USE_RETENTION_LINK
// enable APB to access MCPWM registers
MCPWM_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
mcpwm_ll_enable_bus_clock(group_id, true);
mcpwm_ll_reset_register(group_id);
}
// enable function clock before initialize HAL context
// MCPWM registers are in the core clock domain, there's a bridge between APB and the Core clock domain
// if the core clock is not enabled, then even the APB clock is enabled, the MCPWM registers are still not accessible
MCPWM_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
mcpwm_ll_group_enable_clock(group_id, true);
}
// initialize HAL context
@@ -112,12 +100,12 @@ void mcpwm_release_group_handle(mcpwm_group_t *group)
if (s_platform.group_ref_counts[group_id] == 0) {
do_deinitialize = true;
s_platform.groups[group_id] = NULL; // deregister from platform
MCPWM_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
mcpwm_ll_group_enable_clock(group_id, false);
}
// hal layer deinitialize
mcpwm_hal_deinit(&group->hal);
MCPWM_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
mcpwm_ll_enable_bus_clock(group_id, false);
}
#if CONFIG_PM_ENABLE
@@ -202,7 +190,7 @@ esp_err_t mcpwm_select_periph_clock(mcpwm_group_t *group, soc_module_clk_t clk_s
#endif // CONFIG_PM_ENABLE
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), TAG, "clock source enable failed");
MCPWM_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
mcpwm_ll_group_set_clock_source(group_id, clk_src);
}
}
@@ -261,7 +249,7 @@ esp_err_t mcpwm_set_prescale(mcpwm_group_t *group, uint32_t expect_module_resolu
if (group->prescale == 0) {
group->prescale = group_prescale;
group->resolution_hz = group_resolution_hz;
MCPWM_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
mcpwm_ll_group_set_clock_prescale(group_id, group_prescale);
}
} else {
components/esp_driver_parlio/src/parlio_common.c
+2 -2
View File
@@ -29,7 +29,7 @@ parlio_group_t *parlio_acquire_group_handle(int group_id)
if (group) {
new_group = true;
s_platform.groups[group_id] = group;
PARLIO_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_enable_bus_clock(group_id, true);
parlio_ll_reset_register(group_id);
}
@@ -84,7 +84,7 @@ void parlio_release_group_handle(parlio_group_t *group)
s_platform.groups[group_id] = NULL;
// hal layer deinitialize
parlio_hal_deinit(&group->hal);
PARLIO_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_enable_bus_clock(group_id, false);
}
}
components/esp_driver_parlio/src/parlio_priv.h
-13
View File
@@ -86,19 +86,6 @@
// loop transmission requires ping-pong link to prevent data tearing.
#define PARLIO_DMA_LINK_NUM 2
#if SOC_PERIPH_CLK_CTRL_SHARED
#define PARLIO_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define PARLIO_CLOCK_SRC_ATOMIC()
#endif
#if !SOC_RCC_IS_INDEPENDENT
// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
#define PARLIO_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define PARLIO_RCC_ATOMIC()
#endif // SOC_RCC_IS_INDEPENDENT
///!< Logging settings
#define TAG "parlio"
components/esp_driver_parlio/src/parlio_rx.c
+14 -14
View File
@@ -332,7 +332,7 @@ static bool parlio_rx_default_eof_callback(gdma_channel_handle_t dma_chan, gdma_
/* The current transaction finished, try to get the next transaction from the transaction queue */
if (xQueueReceiveFromISR(rx_unit->trans_que, &next_trans, &high_task_woken) == pdTRUE) {
if (rx_unit->cfg.flags.free_clk) {
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_rx_enable_clock(rx_unit->base.group->hal.regs, false);
}
}
@@ -345,7 +345,7 @@ static bool parlio_rx_default_eof_callback(gdma_channel_handle_t dma_chan, gdma_
gdma_start(rx_unit->dma_chan, gdma_link_get_head_addr(rx_unit->dma_link));
if (rx_unit->cfg.flags.free_clk) {
parlio_ll_rx_start(rx_unit->base.group->hal.regs, true);
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_rx_enable_clock(rx_unit->base.group->hal.regs, true);
}
}
@@ -533,7 +533,7 @@ static esp_err_t parlio_select_periph_clock(parlio_rx_unit_handle_t rx_unit, con
#endif
/* Set clock configuration */
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_rx_set_clock_source(hal->regs, clk_src);
parlio_ll_rx_set_clock_div(hal->regs, &clk_div);
}
@@ -659,11 +659,11 @@ esp_err_t parlio_new_rx_unit(const parlio_rx_unit_config_t *config, parlio_rx_un
}
/* Reset RX module */
PARLIO_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_rx_reset_clock(hal->regs);
}
parlio_ll_rx_reset_fifo(hal->regs);
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_rx_enable_clock(hal->regs, false);
}
parlio_ll_rx_start(hal->regs, false);
@@ -732,7 +732,7 @@ esp_err_t parlio_rx_unit_enable(parlio_rx_unit_handle_t rx_unit, bool reset_queu
if (!rx_unit->cfg.flags.free_clk) {
parlio_ll_rx_reset_fifo(hal->regs);
parlio_ll_rx_start(hal->regs, true);
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_rx_enable_clock(hal->regs, true);
}
}
@@ -755,7 +755,7 @@ esp_err_t parlio_rx_unit_enable(parlio_rx_unit_handle_t rx_unit, bool reset_queu
trans.aligned_payload.buf.body.recovery_address = rx_unit->dma_buf;
}
if (rx_unit->cfg.flags.free_clk) {
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_rx_enable_clock(hal->regs, false);
}
}
@@ -765,7 +765,7 @@ esp_err_t parlio_rx_unit_enable(parlio_rx_unit_handle_t rx_unit, bool reset_queu
gdma_start(rx_unit->dma_chan, gdma_link_get_head_addr(rx_unit->dma_link));
if (rx_unit->cfg.flags.free_clk) {
parlio_ll_rx_start(hal->regs, true);
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_rx_enable_clock(hal->regs, true);
}
}
@@ -788,7 +788,7 @@ esp_err_t parlio_rx_unit_disable(parlio_rx_unit_handle_t rx_unit)
rx_unit->is_enabled = false;
/* stop the RX engine */
gdma_stop(rx_unit->dma_chan);
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_rx_enable_clock(hal->regs, false);
}
parlio_ll_rx_start(hal->regs, false);
@@ -943,7 +943,7 @@ static esp_err_t parlio_rx_unit_do_transaction(parlio_rx_unit_handle_t rx_unit,
portEXIT_CRITICAL_ISR(&s_rx_spinlock);
if (is_stopped) {
if (rx_unit->cfg.flags.free_clk) {
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_rx_enable_clock(rx_unit->base.group->hal.regs, false);
}
}
@@ -956,7 +956,7 @@ static esp_err_t parlio_rx_unit_do_transaction(parlio_rx_unit_handle_t rx_unit,
gdma_start(rx_unit->dma_chan, gdma_link_get_head_addr(rx_unit->dma_link));
if (rx_unit->cfg.flags.free_clk) {
parlio_ll_rx_start(rx_unit->base.group->hal.regs, true);
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_rx_enable_clock(rx_unit->base.group->hal.regs, true);
}
}
@@ -1158,18 +1158,18 @@ esp_err_t parlio_rx_unit_trigger_fake_eof(parlio_rx_unit_handle_t rx_unit, bool
/* Save the current register values */
parl_io_dev_t save_curr_regs = *(parl_io_dev_t *)hal->regs;
/* Reset the hardware FSM of the parlio module */
PARLIO_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_reset_register(rx_unit->base.group->group_id);
}
/* Switch to the default clock source to ensure the register values can be written back successfully */
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_rx_set_clock_source(hal->regs, PARLIO_CLK_SRC_DEFAULT);
}
portEXIT_CRITICAL_SAFE(&s_rx_spinlock);
/* Restore the register values and clock source*/
memcpy(hal->regs, &save_curr_regs, sizeof(parl_io_dev_t));
parlio_ll_rx_update_config(hal->regs);
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_rx_set_clock_source(hal->regs, rx_unit->clk_src);
}
components/esp_driver_parlio/src/parlio_tx.c
+11 -11
View File
@@ -232,7 +232,7 @@ static esp_err_t parlio_select_periph_clock(parlio_tx_unit_t *tx_unit, const par
#else
tx_unit->out_clk_freq_hz = hal_utils_calc_clk_div_integer(&clk_info, &clk_div.integer);
#endif
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
// turn on the tx module clock to sync the clock divider configuration because of the CDC (Cross Domain Crossing)
parlio_ll_tx_enable_clock(hal->regs, true);
parlio_ll_tx_set_clock_source(hal->regs, clk_src);
@@ -304,11 +304,11 @@ esp_err_t parlio_new_tx_unit(const parlio_tx_unit_config_t *config, parlio_tx_un
ESP_GOTO_ON_ERROR(parlio_tx_unit_init_dma(unit, config), err, TAG, "install tx DMA failed");
// reset fifo and core clock domain
PARLIO_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_tx_reset_clock(hal->regs);
}
parlio_ll_tx_reset_fifo(hal->regs);
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
// stop output clock
parlio_ll_tx_enable_clock(hal->regs, false);
}
@@ -482,11 +482,11 @@ static void parlio_tx_do_transaction(parlio_tx_unit_t *tx_unit, parlio_tx_trans_
// And then switched back to the actual clock after the reset is completed.
bool switch_clk = tx_unit->clk_src == PARLIO_CLK_SRC_EXTERNAL ? true : false;
if (switch_clk) {
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_tx_set_clock_source(hal->regs, PARLIO_CLK_SRC_XTAL);
}
}
PARLIO_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_tx_reset_clock(hal->regs);
}
// Since the threshold of the clock divider counter is not updated simultaneously with the clock source switching.
@@ -494,11 +494,11 @@ static void parlio_tx_do_transaction(parlio_tx_unit_t *tx_unit, parlio_tx_trans_
// We place parlio_mount_buffer between reset clock and disable clock to ensure enough time for updating the threshold of the clock divider counter.
parlio_mount_buffer(tx_unit, t);
if (switch_clk) {
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_tx_set_clock_source(hal->regs, PARLIO_CLK_SRC_EXTERNAL);
}
}
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_tx_enable_clock(hal->regs, false);
}
// reset tx fifo after disabling tx core clk to avoid unexpected rempty interrupt
@@ -539,7 +539,7 @@ static void parlio_tx_do_transaction(parlio_tx_unit_t *tx_unit, parlio_tx_trans_
while (parlio_ll_tx_is_ready(hal->regs) == false);
// turn on the core clock after we start the TX unit
parlio_ll_tx_start(hal->regs, true);
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_tx_enable_clock(hal->regs, true);
}
}
@@ -563,7 +563,7 @@ esp_err_t parlio_tx_unit_enable(parlio_tx_unit_handle_t tx_unit)
}
// the chip may resumes from light-sleep, in which case the register configuration needs to be resynchronized
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_tx_enable_clock(hal->regs, true);
}
@@ -610,10 +610,10 @@ esp_err_t parlio_tx_unit_disable(parlio_tx_unit_handle_t tx_unit)
// stop the DMA engine, reset the peripheral state
parlio_hal_context_t *hal = &tx_unit->base.group->hal;
// to stop the undergoing transaction, disable and reset clock
PARLIO_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_tx_enable_clock(hal->regs, false);
}
PARLIO_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
parlio_ll_tx_reset_clock(hal->regs);
}
gdma_stop(tx_unit->dma_chan);
components/esp_driver_pcnt/src/pulse_cnt.c
+3 -15
View File
@@ -50,18 +50,6 @@
#define PCNT_ALLOW_INTR_PRIORITY_MASK ESP_INTR_FLAG_LOWMED
#if SOC_PERIPH_CLK_CTRL_SHARED
#define PCNT_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define PCNT_CLOCK_SRC_ATOMIC()
#endif
#if !SOC_RCC_IS_INDEPENDENT
#define PCNT_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define PCNT_RCC_ATOMIC()
#endif
static const char *TAG = "pcnt";
typedef struct pcnt_platform_t pcnt_platform_t;
@@ -922,7 +910,7 @@ static pcnt_group_t *pcnt_acquire_group_handle(int group_id)
group->intr_priority = -1;
group->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
// enable APB access pcnt registers
PCNT_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
pcnt_ll_enable_bus_clock(group_id, true);
pcnt_ll_reset_register(group_id);
}
@@ -962,7 +950,7 @@ static void pcnt_release_group_handle(pcnt_group_t *group)
assert(s_platform.groups[group_id]);
do_deinitialize = true;
s_platform.groups[group_id] = NULL; // deregister from platform
PCNT_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
pcnt_ll_enable_bus_clock(group_id, false);
}
#if PCNT_USE_RETENTION_LINK
@@ -1017,7 +1005,7 @@ static esp_err_t pcnt_select_periph_clock(pcnt_unit_t *unit, pcnt_clock_source_t
ESP_RETURN_ON_ERROR(ret, TAG, "create pm lock failed");
#endif // CONFIG_PM_ENABLE
PCNT_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
pcnt_ll_set_clock_source(group->hal.dev, clk_src);
}
}
components/esp_driver_rmt/src/rmt_common.c
+5 -17
View File
@@ -9,18 +9,6 @@
#include "soc/rtc.h"
#include "driver/gpio.h"
#if SOC_PERIPH_CLK_CTRL_SHARED
#define RMT_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define RMT_CLOCK_SRC_ATOMIC()
#endif
#if !SOC_RCC_IS_INDEPENDENT
#define RMT_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define RMT_RCC_ATOMIC()
#endif
typedef struct rmt_platform_t {
_lock_t mutex; // platform level mutex lock
rmt_group_t *groups[RMT_LL_GET(INST_NUM)]; // array of RMT group instances
@@ -54,7 +42,7 @@ rmt_group_t *rmt_acquire_group_handle(int group_id)
// group interrupt priority is shared between all channels, it will be set when allocate the first channel
group->intr_priority = RMT_GROUP_INTR_PRIORITY_UNINITIALIZED;
// enable the bus clock for the RMT peripheral
RMT_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
rmt_ll_enable_bus_clock(group_id, true);
rmt_ll_reset_register(group_id);
}
@@ -105,13 +93,13 @@ void rmt_release_group_handle(rmt_group_t *group)
do_deinitialize = true;
s_platform.groups[group_id] = NULL;
// disable core clock
RMT_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
rmt_ll_enable_group_clock(hal->regs, false);
}
// hal layer deinitialize
rmt_hal_deinit(hal);
// disable bus clock
RMT_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
rmt_ll_enable_bus_clock(group_id, false);
}
}
@@ -180,7 +168,7 @@ static esp_err_t rmt_set_group_prescale(rmt_channel_t *chan, uint32_t expect_res
portENTER_CRITICAL(&group->spinlock);
if (group->resolution_hz == 0) {
group->resolution_hz = group_resolution_hz;
RMT_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
rmt_ll_set_group_clock_src(group->hal.regs, chan->channel_id, group->clk_src, group_prescale, 1, 0);
rmt_ll_enable_group_clock(group->hal.regs, true);
}
@@ -241,7 +229,7 @@ esp_err_t rmt_select_periph_clock(rmt_channel_handle_t chan, rmt_clock_source_t
// get clock source frequency
ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &periph_src_clk_hz),
TAG, "get clock source frequency failed");
RMT_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
rmt_ll_set_group_clock_src(group->hal.regs, chan->channel_id, clk_src, 1, 1, 0);
rmt_ll_enable_group_clock(group->hal.regs, true);
}
components/esp_driver_sdio/src/sdio_slave.c
+2 -8
View File
@@ -104,12 +104,6 @@ static const char TAG[] = "sdio_slave";
#define SDIO_SLAVE_LOGE(s, ...) ESP_LOGE(TAG, "%s(%d): "s, __FUNCTION__,__LINE__,##__VA_ARGS__)
#define SDIO_SLAVE_LOGW(s, ...) ESP_LOGW(TAG, "%s: "s, __FUNCTION__,##__VA_ARGS__)
#if !SOC_RCC_IS_INDEPENDENT
#define SDIO_SLAVE_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define SDIO_SLAVE_RCC_ATOMIC()
#endif
// sdio_slave_buf_handle_t is of type recv_desc_t*;
typedef struct recv_desc_s {
union {
@@ -312,7 +306,7 @@ static inline esp_err_t sdio_slave_hw_init(sdio_slave_config_t *config)
configure_pin(slot->d3_gpio, slot->func, pullup);
//enable register clock
SDIO_SLAVE_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
sdio_slave_ll_enable_bus_clock(true);
sdio_slave_ll_reset_register();
}
@@ -345,7 +339,7 @@ static void sdio_slave_hw_deinit(void)
recover_pin(slot->d3_gpio, slot->func);
//disable register clock
SDIO_SLAVE_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
sdio_slave_ll_enable_bus_clock(false);
}
}
components/esp_driver_sdmmc/include/esp_private/sd_host_private.h
-14
View File
@@ -43,20 +43,6 @@ extern "C" {
#define SD_HOST_SDMMC_DMA_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA)
#endif
#if !SOC_RCC_IS_INDEPENDENT
// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
#define SD_HOST_SDMMC_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define SD_HOST_SDMMC_RCC_ATOMIC()
#endif
#if SOC_PERIPH_CLK_CTRL_SHARED
// Clock source and related clock settings are mixing with other peripherals, so we need to use a critical section
#define SD_HOST_SDMMC_CLK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define SD_HOST_SDMMC_CLK_SRC_ATOMIC()
#endif
#define SD_HOST_SDMMC_CLOCK_UPDATE_CMD_TIMEOUT_US (1000 * 1000)
#define SD_HOST_SDMMC_START_CMD_TIMEOUT_US (1000 * 1000)
#define SD_HOST_SDMMC_RESET_TIMEOUT_US (5000 * 1000)
components/esp_driver_sdmmc/src/sd_host_sdmmc.c
+4 -4
View File
@@ -663,7 +663,7 @@ esp_err_t sd_host_set_delay_phase(sd_host_sdmmc_slot_t *slot)
delay_phase_num = 0;
break;
}
SD_HOST_SDMMC_CLK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
sdmmc_ll_set_din_delay_phase(slot->ctlr->hal.dev, phase, speed_mode);
sdmmc_ll_set_dout_delay_phase(slot->ctlr->hal.dev, phase, speed_mode);
}
@@ -753,7 +753,7 @@ static esp_err_t sd_host_claim_controller(sd_host_sdmmc_ctlr_t *controller)
if (found) {
s_platform.controllers[i] = controller;
controller->host_id = i;
SD_HOST_SDMMC_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
sdmmc_ll_enable_bus_clock(i, true);
sdmmc_ll_reset_register(i);
}
@@ -774,7 +774,7 @@ static esp_err_t sd_host_declaim_controller(sd_host_sdmmc_ctlr_t *controller)
_lock_acquire(&s_platform.mutex);
s_platform.controllers[controller->host_id] = NULL;
SD_HOST_SDMMC_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
sdmmc_ll_enable_bus_clock(0, false);
}
_lock_release(&s_platform.mutex);
@@ -980,7 +980,7 @@ static esp_err_t sd_host_reset(sd_host_sdmmc_ctlr_t *ctlr)
static void sd_host_set_clk_div(sd_host_sdmmc_ctlr_t *ctlr, soc_periph_sdmmc_clk_src_t src, int div)
{
ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)src, true));
SD_HOST_SDMMC_CLK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
sdmmc_ll_set_clock_div(ctlr->hal.dev, div);
sdmmc_ll_select_clk_source(ctlr->hal.dev, src);
sdmmc_ll_init_phase_delay(ctlr->hal.dev);
components/esp_driver_spi/src/gpspi/spi_common.c
+6 -12
View File
@@ -29,12 +29,6 @@
#include "soc/dport_reg.h"
#endif
#if SOC_PERIPH_CLK_CTRL_SHARED
#define SPI_COMMON_PERI_CLOCK_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define SPI_COMMON_PERI_CLOCK_ATOMIC()
#endif
#if CONFIG_SPI_MASTER_ISR_IN_IRAM || CONFIG_SPI_SLAVE_ISR_IN_IRAM
#define SPI_COMMON_ISR_ATTR IRAM_ATTR
#else
@@ -93,7 +87,7 @@ esp_err_t spicommon_bus_alloc(spi_host_device_t host_id, const char *name)
spicommon_periph_free(host_id);
return ESP_ERR_NO_MEM;
}
SPI_COMMON_PERI_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
spi_ll_enable_clock(host_id, true);
}
ctx->host_id = host_id;
@@ -105,7 +99,7 @@ esp_err_t spicommon_bus_free(spi_host_device_t host_id)
{
assert(bus_ctx[host_id]);
spicommon_periph_free(host_id);
SPI_COMMON_PERI_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
spi_ll_enable_clock(host_id, false);
}
free(bus_ctx[host_id]);
@@ -180,7 +174,7 @@ static bool claim_dma_chan(int dma_chan, uint32_t *out_actual_dma_chan)
}
}
#else
SPI_COMMON_RCC_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
//esp32: have only one spi_dma
spi_dma_ll_enable_bus_clock(dma_chan, true);
spi_dma_ll_reset_register(dma_chan);
@@ -397,7 +391,7 @@ esp_err_t spicommon_dma_chan_free(spi_dma_ctx_t *dma_ctx)
}
}
#else
SPI_COMMON_RCC_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
spi_dma_ll_enable_bus_clock(dma_ctx->tx_dma_chan.host_id, false);
}
#endif
@@ -1046,7 +1040,7 @@ bool SPI_COMMON_ISR_ATTR spicommon_dmaworkaround_req_reset(int dmachan, dmaworka
ret = false;
} else {
//Reset DMA
SPI_COMMON_RCC_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
spi_dma_ll_reset_register(dmachan);
}
ret = true;
@@ -1066,7 +1060,7 @@ void SPI_COMMON_ISR_ATTR spicommon_dmaworkaround_idle(int dmachan)
dmaworkaround_channels_busy[dmachan - 1] = 0;
if (dmaworkaround_waiting_for_chan == dmachan) {
//Reset DMA
SPI_COMMON_RCC_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
spi_dma_ll_reset_register(dmachan);
}
dmaworkaround_waiting_for_chan = 0;
components/esp_driver_spi/src/gpspi/spi_master.c
+2 -8
View File
@@ -151,12 +151,6 @@ We have two bits to control the interrupt:
#define SPI_MASTER_MALLOC_CAPS (MALLOC_CAP_DEFAULT)
#endif
#if SOC_PERIPH_CLK_CTRL_SHARED
#define SPI_MASTER_PERI_CLOCK_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define SPI_MASTER_PERI_CLOCK_ATOMIC()
#endif
#define SPI_PERIPH_SRC_FREQ_MAX (80*1000*1000) //peripheral hardware limitation for clock source into peripheral
/**
@@ -614,7 +608,7 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle)
// because `SPI_CLK_SRC_RC_FAST` will be disabled then, which block following transactions
if (handle->host->cur_cs == DEV_NUM_MAX) {
spi_device_acquire_bus(handle, portMAX_DELAY);
SPI_MASTER_PERI_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
spi_ll_set_clk_source(handle->host->hal.hw, SPI_CLK_SRC_DEFAULT);
}
spi_device_release_bus(handle);
@@ -689,7 +683,7 @@ static SPI_MASTER_ISR_ATTR void spi_setup_device(spi_device_t *dev, spi_trans_pr
if (spi_bus_lock_touch(dev_lock) || clock_changed) {
/* Configuration has not been applied yet. */
spi_hal_setup_device(hal, hal_dev);
SPI_MASTER_PERI_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
#if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV
//we set mst_div as const 2, then (hs_clk = 2*mst_clk) to ensure timing turning work as past
//and sure (hs_div * mst_div = source_pre_div)
components/esp_driver_spi/src/gpspi/spi_slave.c
+2 -2
View File
@@ -378,7 +378,7 @@ esp_err_t spi_slave_enable(spi_host_device_t host)
// If going to TOP_PD power down, the bus_clock is required during reg_dma, and will be disabled by sleep flow then
#if !CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
SPI_COMMON_RCC_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
spi_ll_enable_bus_clock(host, true);
}
#endif
@@ -398,7 +398,7 @@ esp_err_t spi_slave_disable(spi_host_device_t host)
// same as above
#if !CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
SPI_COMMON_RCC_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
spi_ll_enable_bus_clock(host, false);
}
#endif
components/esp_driver_spi/src/gpspi/spi_slave_hd.c
+2 -2
View File
@@ -376,7 +376,7 @@ esp_err_t spi_slave_hd_enable(spi_host_device_t host_id)
// If going to TOP_PD power down, the bus_clock is required during reg_dma, and will be disabled by sleep flow then
#if !CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
SPI_COMMON_RCC_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
spi_ll_enable_bus_clock(host_id, true);
}
#endif
@@ -396,7 +396,7 @@ esp_err_t spi_slave_hd_disable(spi_host_device_t host_id)
// same as above
#if !CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
SPI_COMMON_RCC_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
spi_ll_enable_bus_clock(host_id, false);
}
#endif
components/esp_driver_twai/esp_twai_onchip.c
+5 -17
View File
@@ -15,31 +15,19 @@
#include "hal/twaifd_ll.h"
#endif
#if !SOC_RCC_IS_INDEPENDENT
#define TWAI_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define TWAI_RCC_ATOMIC()
#endif
#if SOC_PERIPH_CLK_CTRL_SHARED
#define TWAI_PERI_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define TWAI_PERI_ATOMIC()
#endif
static void _twai_rcc_clock_ctrl(uint8_t ctrlr_id, bool enable)
{
TWAI_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
twai_ll_enable_bus_clock(ctrlr_id, enable);
twai_ll_reset_register(ctrlr_id);
}
TWAI_PERI_ATOMIC() {
PERIPH_RCC_ATOMIC() {
twai_ll_enable_clock(ctrlr_id, enable);
}
}
static void _twai_rcc_clock_sel(uint8_t ctrlr_id, twai_clock_source_t clock)
{
TWAI_PERI_ATOMIC() {
PERIPH_RCC_ATOMIC() {
twai_ll_set_clock_source(ctrlr_id, clock);
}
}
@@ -191,7 +179,7 @@ static void _node_isr_main(void *arg)
if (events & TWAI_HAL_EVENT_NEED_PERIPH_RESET) {
ESP_EARLY_LOGD(TAG, "Triggered peripheral reset");
twai_hal_prepare_for_reset(twai_ctx->hal);
TWAI_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
twai_ll_reset_register(twai_ctx->ctrlr_id);
}
twai_hal_recover_from_reset(twai_ctx->hal);
@@ -489,7 +477,7 @@ static esp_err_t _node_disable(twai_node_handle_t node)
// when `disable` happens during hardware busy, the next RX frame is corrupted, a HW reset can fix it
if (twai_hal_is_hw_busy(twai_ctx->hal)) {
twai_hal_backup_config(twai_ctx->hal);
TWAI_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
twai_ll_reset_register(twai_ctx->ctrlr_id);
}
twai_hal_restore_config(twai_ctx->hal);
components/esp_driver_uart/src/uart.c
+17 -17
View File
@@ -6,6 +6,7 @@
#include <string.h>
#include <sys/param.h>
#include <sys/lock.h>
#include "sdkconfig.h"
#include "esp_types.h"
#include "esp_attr.h"
#include "esp_intr_alloc.h"
@@ -26,9 +27,9 @@
#include "esp_private/esp_clk_tree_common.h"
#include "esp_private/gpio.h"
#include "esp_private/esp_gpio_reserve.h"
#include "esp_private/uart_share_hw_ctrl.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/sleep_retention.h"
#include "esp_clk_tree.h"
#include "sdkconfig.h"
#include "esp_rom_gpio.h"
#if (SOC_UART_LP_NUM >= 1)
#include "driver/rtc_io.h"
@@ -40,7 +41,6 @@
#endif
#include "clk_ctrl_os.h"
#include "esp_pm.h"
#include "esp_private/sleep_retention.h"
#ifdef CONFIG_UART_ISR_IN_IRAM
#define UART_ISR_ATTR IRAM_ATTR
@@ -222,7 +222,7 @@ static bool uart_module_enable(uart_port_t uart_num)
_lock_acquire(&(uart_context[uart_num].mutex));
if (uart_context[uart_num].hw_enabled != true) {
if (uart_num < SOC_UART_HP_NUM) {
HP_UART_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_ll_enable_bus_clock(uart_num, true);
}
if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) {
@@ -230,10 +230,10 @@ static bool uart_module_enable(uart_port_t uart_num)
if (uart_context[uart_num].rx_io_num == -1) {
esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_RX), false);
}
HP_UART_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_ll_reset_register(uart_num);
}
HP_UART_SRC_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_ll_sclk_enable(uart_context[uart_num].hal.dev);
}
}
@@ -270,7 +270,7 @@ static bool uart_module_enable(uart_port_t uart_num)
gpio_pullup_en(io_num);
#endif
}
LP_UART_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
lp_uart_ll_enable_bus_clock(TO_LP_UART_NUM(uart_num), true);
lp_uart_ll_reset_register(TO_LP_UART_NUM(uart_num));
}
@@ -297,17 +297,17 @@ static void uart_module_disable(uart_port_t uart_num)
sleep_retention_module_deinit(module);
}
#endif
HP_UART_SRC_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_ll_sclk_disable(uart_context[uart_num].hal.dev);
}
HP_UART_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_ll_enable_bus_clock(uart_num, false);
}
}
#if (SOC_UART_LP_NUM >= 1)
else if (uart_num >= SOC_UART_HP_NUM) {
lp_uart_ll_sclk_disable(TO_LP_UART_NUM(uart_num));
LP_UART_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
lp_uart_ll_enable_bus_clock(TO_LP_UART_NUM(uart_num), false);
}
}
@@ -389,7 +389,7 @@ esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baud_rate)
bool success = false;
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
if (uart_num < SOC_UART_HP_NUM) {
HP_UART_SRC_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
success = uart_hal_set_baudrate(&(uart_context[uart_num].hal), baud_rate, sclk_freq);
}
}
@@ -1095,14 +1095,14 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
uart_hal_init(&(uart_context[uart_num].hal), uart_num);
if (uart_num < SOC_UART_HP_NUM) {
HP_UART_SRC_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_sclk_sel);
success = uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq);
}
}
#if (SOC_UART_LP_NUM >= 1)
else {
LP_UART_SRC_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
lp_uart_ll_set_source_clk(uart_context[uart_num].hal.dev, (soc_periph_lp_uart_clk_src_t)uart_sclk_sel);
}
success = lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, uart_config->baud_rate, sclk_freq);
@@ -2086,13 +2086,13 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
esp_clk_tree_enable_src(default_sclk, true);
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
if (uart_num < SOC_UART_HP_NUM) {
HP_UART_SRC_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_hal_set_sclk(&(uart_context[uart_num].hal), default_sclk);
}
}
#if (SOC_UART_LP_NUM >= 1)
else {
LP_UART_SRC_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
lp_uart_ll_set_source_clk(uart_context[uart_num].hal.dev, (soc_periph_lp_uart_clk_src_t)default_sclk);
}
}
@@ -2275,7 +2275,7 @@ esp_err_t uart_set_wakeup_threshold(uart_port_t uart_num, int wakeup_threshold)
"wakeup_threshold out of bounds");
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
uart_hal_set_wakeup_edge_thrd(&(uart_context[uart_num].hal), wakeup_threshold);
HP_UART_PAD_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_ll_enable_pad_sleep_clock(uart_context[uart_num].hal.dev, true);
}
UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
@@ -2352,7 +2352,7 @@ esp_err_t uart_detect_bitrate_start(uart_port_t uart_num, const uart_bitrate_det
}
#endif
UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
HP_UART_SRC_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_sclk_sel);
uart_hal_set_baudrate(&(uart_context[uart_num].hal), 57600, sclk_freq); // set to any baudrate
}
components/esp_driver_uart/src/uhci.c
+2 -2
View File
@@ -426,7 +426,7 @@ esp_err_t uhci_del_controller(uhci_controller_handle_t uhci_ctrl)
return ESP_ERR_INVALID_STATE;
}
UHCI_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uhci_ll_enable_bus_clock(uhci_ctrl->uhci_num, false);
}
@@ -507,7 +507,7 @@ esp_err_t uhci_new_controller(const uhci_controller_config_t *config, uhci_contr
xQueueSend(uhci_ctrl->tx_dir.trans_queues[UHCI_TRANS_QUEUE_READY], &p_trans_desc, 0);
}
UHCI_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uhci_ll_enable_bus_clock(uhci_ctrl->uhci_num, true);
uhci_ll_reset_register(uhci_ctrl->uhci_num);
}
components/esp_driver_uart/src/uhci_private.h
-12
View File
@@ -32,18 +32,6 @@ typedef struct uhci_controller_t uhci_controller_t;
#define UHCI_MEM_ALLOC_CAPS (MALLOC_CAP_DEFAULT)
#endif
#if SOC_PERIPH_CLK_CTRL_SHARED
#define UHCI_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define UHCI_CLOCK_SRC_ATOMIC()
#endif
#if !SOC_RCC_IS_INDEPENDENT
#define UHCI_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define UHCI_RCC_ATOMIC()
#endif
typedef struct {
void *buffer; // buffer for saving the received symbols
size_t buffer_size; // size of the buffer, in bytes
components/esp_driver_usb_serial_jtag/src/usb_serial_jtag.c
+1 -7
View File
@@ -26,12 +26,6 @@
it shouldn't need anything more than a simple, straightforward driver.
*/
#if !SOC_RCC_IS_INDEPENDENT
#define USJ_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define USJ_RCC_ATOMIC()
#endif
// The hardware buffer max size is 64, both for RX and TX.
#define USB_SER_JTAG_ENDP_SIZE (64)
#define USB_SER_JTAG_RX_MAX_SIZE (USB_SER_JTAG_ENDP_SIZE)
@@ -204,7 +198,7 @@ esp_err_t usb_serial_jtag_driver_install(usb_serial_jtag_driver_config_t *usb_se
}
// Enable USB-Serial-JTAG peripheral module clock
USJ_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
usb_serial_jtag_ll_enable_bus_clock(true);
}
components/esp_eth/src/mac/esp_eth_mac_esp.c
+8 -15
View File
@@ -52,13 +52,6 @@ static const char *TAG = "esp.emac";
#define EMAC_MULTI_REG_MUTEX_TIMEOUT_MS (100)
#if CONFIG_IDF_TARGET_ESP32P4
// ESP32P4 EMAC interface clock configuration is shared among other modules in registers
#define EMAC_IF_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define EMAC_IF_RCC_ATOMIC()
#endif
#define EMAC_USE_RETENTION_LINK (CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_EMAC_SUPPORT_SLEEP_RETENTION)
typedef struct {
@@ -285,11 +278,11 @@ static esp_err_t emac_esp32_set_speed(esp_eth_mac_t *mac, eth_speed_t speed)
// Set RMII clk_rx/clk_tx divider to get 25MHz for 100mbps mode or 2.5MHz for 10mbps mode
if (emac_hal_get_phy_intf(&emac->hal) == EMAC_DATA_INTERFACE_RMII) {
if (speed == ETH_SPEED_10M) {
EMAC_IF_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
emac_hal_clock_rmii_rx_tx_div(&emac->hal, RMII_10M_SPEED_RX_TX_CLK_DIV);
}
} else {
EMAC_IF_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
emac_hal_clock_rmii_rx_tx_div(&emac->hal, RMII_100M_SPEED_RX_TX_CLK_DIV);
}
}
@@ -778,7 +771,7 @@ static esp_err_t emac_esp_config_data_interface(const eth_esp32_emac_config_t *e
ESP_GOTO_ON_ERROR(emac_esp_iomux_init_mii(mii_data_gpio), err, TAG, "invalid EMAC MII data plane GPIO");
#endif // SOC_EMAC_MII_USE_GPIO_MATRIX
/* Enable MII clock */
EMAC_IF_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
emac_hal_clock_enable_mii(&emac->hal);
}
break;
@@ -793,7 +786,7 @@ static esp_err_t emac_esp_config_data_interface(const eth_esp32_emac_config_t *e
/* If ref_clk is configured as input */
if (esp32_emac_config->clock_config.rmii.clock_mode == EMAC_CLK_EXT_IN) {
ESP_GOTO_ON_ERROR(emac_esp_iomux_rmii_clk_input(esp32_emac_config->clock_config.rmii.clock_gpio), err, TAG, "invalid EMAC RMII clock input GPIO");
EMAC_IF_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
emac_hal_clock_enable_rmii_input(&emac->hal);
}
} else if (esp32_emac_config->clock_config.rmii.clock_mode == EMAC_CLK_OUT) {
@@ -803,7 +796,7 @@ static esp_err_t emac_esp_config_data_interface(const eth_esp32_emac_config_t *e
ESP_GOTO_ON_FALSE(esp32_emac_config->clock_config_out_in.rmii.clock_mode == EMAC_CLK_EXT_IN && esp32_emac_config->clock_config_out_in.rmii.clock_gpio >= 0,
ESP_ERR_INVALID_ARG, err, TAG, "invalid EMAC input of output clock mode");
ESP_GOTO_ON_ERROR(emac_esp_iomux_rmii_clk_input(esp32_emac_config->clock_config_out_in.rmii.clock_gpio), err, TAG, "invalid EMAC RMII clock input GPIO");
EMAC_IF_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
emac_hal_clock_enable_rmii_input(&emac->hal);
}
#elif CONFIG_IDF_TARGET_ESP32
@@ -817,7 +810,7 @@ static esp_err_t emac_esp_config_data_interface(const eth_esp32_emac_config_t *e
ESP_GOTO_ON_ERROR(emac_esp_iomux_rmii_clk_ouput(esp32_emac_config->clock_config.rmii.clock_gpio), err, TAG, "invalid EMAC RMII clock output GPIO");
}
/* Enable RMII Output clock */
EMAC_IF_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
emac_hal_clock_enable_rmii_output(&emac->hal);
}
} else {
@@ -837,7 +830,7 @@ esp_err_t esp_eth_mac_ptp_enable(esp_eth_mac_t *mac, const eth_mac_ptp_config_t
{
ESP_RETURN_ON_FALSE(mac && config, ESP_ERR_INVALID_ARG, TAG, "invalid argument, can't be NULL");
emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
EMAC_IF_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
emac_hal_clock_enable_ptp(&emac->hal, config->clk_src, true);
}
emac_hal_ptp_config_t ptp_config = {
@@ -857,7 +850,7 @@ esp_err_t esp_eth_mac_ptp_disable(esp_eth_mac_t *mac)
emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
ESP_RETURN_ON_ERROR(emac_hal_ptp_stop(&emac->hal), TAG, "failed to stop PTP module");
emac_esp_dma_ts_enable(emac->emac_dma_hndl, false);
EMAC_IF_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
emac_hal_clock_enable_ptp(&emac->hal, 0, false);
}
return ESP_OK;
components/esp_hal_i2c/test_apps/hal_i2c/components/hal_i2c/hal_i2c.c
+2 -15
View File
@@ -37,19 +37,6 @@ static inline uint32_t time_get_us_by_ccount(uint32_t counter)
ESP_LOG_ATTR_TAG(TAG, "hal-i2c");
// If Reset and Clock Control is independent, we need this macro to avoid concurrency issue
#if !SOC_RCC_IS_INDEPENDENT
#define I2C_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define I2C_RCC_ATOMIC()
#endif
#if SOC_PERIPH_CLK_CTRL_SHARED
#define I2C_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define I2C_CLOCK_SRC_ATOMIC()
#endif
typedef struct {
i2c_dev_t *i2c_dev;
bool initialized;
@@ -76,7 +63,7 @@ esp_err_t hal_i2c_init(hal_i2c_config *cfg)
uint32_t freq = cfg->freq;
i2c_dev_t *dev = i2c_context[cfg->i2c_port].i2c_dev;
I2C_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_ll_enable_bus_clock(0, true);
i2c_ll_reset_register(0);
}
@@ -130,7 +117,7 @@ esp_err_t hal_i2c_init(hal_i2c_config *cfg)
// init clock, always use xtal in hal driver.
i2c_hal_clk_config_t clk_cal = {0};
I2C_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
i2c_ll_set_source_clk(dev, SOC_MOD_CLK_XTAL);
}
uint32_t xtal_freq = 0;
components/esp_hw_support/adc_share_hw_ctrl.c
+2 -2
View File
@@ -206,7 +206,7 @@ void adc_apb_periph_claim(void)
esp_os_enter_critical(&s_spinlock);
s_adc_digi_ctrlr_cnt++;
if (s_adc_digi_ctrlr_cnt == 1) {
ADC_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
adc_ll_enable_bus_clock(true);
#if SOC_RCC_IS_INDEPENDENT
adc_ll_enable_func_clock(true);
@@ -223,7 +223,7 @@ void adc_apb_periph_free(void)
esp_os_enter_critical(&s_spinlock);
s_adc_digi_ctrlr_cnt--;
if (s_adc_digi_ctrlr_cnt == 0) {
ADC_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
adc_ll_enable_bus_clock(false);
#if SOC_RCC_IS_INDEPENDENT
adc_ll_enable_func_clock(false);
components/esp_hw_support/etm/esp_etm.c
+2 -9
View File
@@ -32,13 +32,6 @@
#define ETM_USE_RETENTION_LINK (SOC_ETM_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
#if !SOC_RCC_IS_INDEPENDENT
// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
#define ETM_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define ETM_RCC_ATOMIC()
#endif
ESP_LOG_ATTR_TAG(TAG, "etm");
typedef struct etm_platform_t etm_platform_t;
@@ -117,7 +110,7 @@ static etm_group_t *etm_acquire_group_handle(int group_id)
group->group_id = group_id;
group->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
// enable bus clock for the ETM registers
ETM_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
etm_ll_enable_bus_clock(group_id, true);
etm_ll_reset_register(group_id);
}
@@ -172,7 +165,7 @@ static void etm_release_group_handle(etm_group_t *group)
s_platform.groups[group_id] = NULL; // deregister from platform
etm_hal_deinit(&group->hal);
// disable the bus clock for the ETM registers
ETM_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
etm_ll_enable_bus_clock(group_id, false);
}
components/esp_hw_support/include/esp_private/adc_share_hw_ctrl.h
+1 -6
View File
@@ -21,17 +21,12 @@
#include "esp_err.h"
#include "hal/adc_types.h"
#include "soc/soc_caps.h"
#include "esp_private/periph_ctrl.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_RCC_IS_INDEPENDENT || CONFIG_IDF_TARGET_ESP32
#define ADC_BUS_CLK_ATOMIC()
#else
#define ADC_BUS_CLK_ATOMIC() PERIPH_RCC_ATOMIC()
#endif
#if SOC_ADC_CALIBRATION_V1_SUPPORTED
/*---------------------------------------------------------------
ADC Hardware Calibration
components/esp_hw_support/include/esp_private/esp_crypto_lock_internal.h
+3 -3
View File
@@ -15,7 +15,7 @@ extern "C" {
// NOTE: [ESP-TEE] Since the clock configuration APIs are part
// of the TEE, the XYZ_RCC_ATOMIC macros need to be defined as void.
#if SOC_RCC_IS_INDEPENDENT || NON_OS_BUILD
#if NON_OS_BUILD
#define MPI_RCC_ATOMIC()
#define ECC_RCC_ATOMIC()
#define HMAC_RCC_ATOMIC()
@@ -24,7 +24,7 @@ extern "C" {
#define AES_RCC_ATOMIC()
#define SHA_RCC_ATOMIC()
#define KEY_MANAGER_RCC_ATOMIC()
#else /* !SOC_RCC_IS_INDEPENDENT */
#else
#define MPI_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#define ECC_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#define HMAC_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
@@ -33,7 +33,7 @@ extern "C" {
#define AES_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#define SHA_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#define KEY_MANAGER_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#endif /* SOC_RCC_IS_INDEPENDENT */
#endif
#ifdef __cplusplus
}
components/esp_hw_support/include/esp_private/spi_share_hw_ctrl.h
-6
View File
@@ -18,12 +18,6 @@
extern "C" {
#endif
#if !SOC_RCC_IS_INDEPENDENT
#define SPI_COMMON_RCC_CLOCK_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define SPI_COMMON_RCC_CLOCK_ATOMIC()
#endif
#define BUS_LOCK_DEBUG 0
#if BUS_LOCK_DEBUG
components/esp_hw_support/include/esp_private/uart_share_hw_ctrl.h
-38
View File
@@ -1,38 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc_caps.h"
#include "esp_private/periph_ctrl.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_PERIPH_CLK_CTRL_SHARED
#define HP_UART_SRC_CLK_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define HP_UART_SRC_CLK_ATOMIC()
#endif
#if SOC_RCC_IS_INDEPENDENT
#define HP_UART_BUS_CLK_ATOMIC()
#define HP_UART_PAD_CLK_ATOMIC()
#else
#define HP_UART_BUS_CLK_ATOMIC() PERIPH_RCC_ATOMIC()
#define HP_UART_PAD_CLK_ATOMIC() PERIPH_RCC_ATOMIC()
#endif
#if (SOC_UART_LP_NUM >= 1)
#define LP_UART_SRC_CLK_ATOMIC() PERIPH_RCC_ATOMIC()
#define LP_UART_BUS_CLK_ATOMIC() PERIPH_RCC_ATOMIC()
#endif
#ifdef __cplusplus
}
#endif
components/esp_hw_support/port/esp32/sar_periph_ctrl.c
+1 -1
View File
@@ -124,7 +124,7 @@ void sar_periph_ctrl_adc_continuous_power_release(void)
*----------------------------------------------------------------------------*/
void sar_periph_ctrl_adc_reset(void)
{
ADC_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
adc_ll_reset_register();
}
}
components/esp_hw_support/port/esp32c2/sar_periph_ctrl.c
+1 -1
View File
@@ -129,7 +129,7 @@ void sar_periph_ctrl_adc_oneshot_power_release(void)
*----------------------------------------------------------------------------*/
void sar_periph_ctrl_adc_reset(void)
{
ADC_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
adc_ll_reset_register();
}
}
components/esp_hw_support/port/esp32c3/sar_periph_ctrl.c
+1 -1
View File
@@ -145,7 +145,7 @@ void sar_periph_ctrl_adc_reset(void)
// Acquire ADC reset lock to prevent temperature sensor readings during ADC reset
adc_reset_lock_acquire();
ADC_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
// Save temperature sensor related register values before ADC reset
tsens_ll_reg_values_t saved_tsens_regs = {};
tsens_ll_backup_registers(&saved_tsens_regs);
components/esp_hw_support/port/esp32c5/sar_periph_ctrl.c
+1 -1
View File
@@ -134,7 +134,7 @@ void sar_periph_ctrl_adc_reset(void)
// Acquire ADC reset lock to prevent temperature sensor readings during ADC reset
adc_reset_lock_acquire();
ADC_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
// Save temperature sensor related register values before ADC reset
tsens_ll_reg_values_t saved_tsens_regs = {};
tsens_ll_backup_registers(&saved_tsens_regs);
components/esp_hw_support/port/esp32c6/sar_periph_ctrl.c
+1 -1
View File
@@ -135,7 +135,7 @@ void sar_periph_ctrl_adc_reset(void)
// Acquire ADC reset lock to prevent temperature sensor readings during ADC reset
adc_reset_lock_acquire();
ADC_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
// Save temperature sensor related register values before ADC reset
tsens_ll_reg_values_t saved_tsens_regs = {};
tsens_ll_backup_registers(&saved_tsens_regs);
components/esp_hw_support/port/esp32c61/sar_periph_ctrl.c
+1 -1
View File
@@ -134,7 +134,7 @@ void sar_periph_ctrl_adc_reset(void)
// Acquire ADC reset lock to prevent temperature sensor readings during ADC reset
adc_reset_lock_acquire();
ADC_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
// Save temperature sensor related register values before ADC reset
tsens_ll_reg_values_t saved_tsens_regs = {};
tsens_ll_backup_registers(&saved_tsens_regs);
components/esp_hw_support/port/esp32h2/sar_periph_ctrl.c
+1 -1
View File
@@ -134,7 +134,7 @@ void sar_periph_ctrl_adc_reset(void)
// Acquire ADC reset lock to prevent temperature sensor readings during ADC reset
adc_reset_lock_acquire();
ADC_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
// Save temperature sensor related register values before ADC reset
tsens_ll_reg_values_t saved_tsens_regs = {};
tsens_ll_backup_registers(&saved_tsens_regs);
components/esp_hw_support/port/esp32p4/sar_periph_ctrl.c
+1 -1
View File
@@ -126,7 +126,7 @@ void sar_periph_ctrl_adc_continuous_power_release(void)
*----------------------------------------------------------------------------*/
void sar_periph_ctrl_adc_reset(void)
{
ADC_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
adc_ll_reset_register();
}
}
components/esp_hw_support/port/esp32s2/sar_periph_ctrl.c
+1 -1
View File
@@ -125,7 +125,7 @@ void sar_periph_ctrl_adc_continuous_power_release(void)
*----------------------------------------------------------------------------*/
void sar_periph_ctrl_adc_reset(void)
{
ADC_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
adc_ll_reset_register();
}
}
components/esp_hw_support/port/esp32s3/sar_periph_ctrl.c
+1 -1
View File
@@ -128,7 +128,7 @@ void sar_periph_ctrl_adc_continuous_power_release(void)
*----------------------------------------------------------------------------*/
void sar_periph_ctrl_adc_reset(void)
{
ADC_BUS_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
adc_ll_reset_register();
}
}
components/esp_hw_support/port/pau_regdma.c
+1 -8
View File
@@ -25,13 +25,6 @@
ESP_LOG_ATTR_TAG(TAG, "pau_regdma");
#if !SOC_RCC_IS_INDEPENDENT
// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
#define PAU_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define PAU_RCC_ATOMIC()
#endif
typedef struct {
pau_hal_context_t *hal;
} pau_context_t;
@@ -46,7 +39,7 @@ pau_context_t * __attribute__((weak)) IRAM_ATTR PAU_instance(void)
if (pau_hal.dev == NULL) {
pau_hal.dev = &PAU;
PAU_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
pau_hal_enable_bus_clock(true);
}
pau_hal_set_regdma_wait_timeout(&pau_hal, PAU_REGDMA_LINK_WAIT_RETRY_COUNT, PAU_REGDMA_LINK_WAIT_READ_INTERNAL);
components/esp_hw_support/sar_tsens_ctrl.c
+2 -8
View File
@@ -29,12 +29,6 @@ ESP_LOG_ATTR_TAG(TAG_TSENS, "temperature_sensor");
#define INT_NOT_USED 999999
#if !SOC_RCC_IS_INDEPENDENT
#define TSENS_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define TSENS_RCC_ATOMIC()
#endif
#define TSENS_LINE_REGRESSION_US (200)
static int s_temperature_sensor_power_cnt;
@@ -51,7 +45,7 @@ void temperature_sensor_power_acquire(void)
#if !SOC_TSENS_IS_INDEPENDENT_FROM_ADC
adc_apb_periph_claim();
#endif
TSENS_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
temperature_sensor_ll_bus_clk_enable(true);
temperature_sensor_ll_reset_module();
}
@@ -74,7 +68,7 @@ void temperature_sensor_power_release(void)
abort();
} else if (s_temperature_sensor_power_cnt == 0) {
temperature_sensor_ll_enable(false);
TSENS_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
temperature_sensor_ll_bus_clk_enable(false);
}
#if !SOC_TSENS_IS_INDEPENDENT_FROM_ADC
components/esp_hw_support/spi_share_hw_ctrl.c
+2 -2
View File
@@ -34,7 +34,7 @@ bool spicommon_periph_claim(spi_host_device_t host, const char* source)
bool ret = atomic_compare_exchange_strong(&spi_periph_claimed[host], &false_var, true);
if (ret) {
spi_claiming_func[host] = source;
SPI_COMMON_RCC_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
spi_ll_enable_bus_clock(host, true);
spi_ll_reset_register(host);
}
@@ -55,7 +55,7 @@ bool spicommon_periph_free(spi_host_device_t host)
bool true_var = true;
bool ret = atomic_compare_exchange_strong(&spi_periph_claimed[host], &true_var, false);
if (ret) {
SPI_COMMON_RCC_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
spi_ll_enable_bus_clock(host, false);
}
}
components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_intr_alloc.c
+1 -6
View File
@@ -280,18 +280,13 @@ void IRAM_ATTR int_handler2(void *arg)
}
}
#if !SOC_RCC_IS_INDEPENDENT
#define TEST_BUS_RCC_CLOCK_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define TEST_BUS_RCC_CLOCK_ATOMIC()
#endif
TEST_CASE("allocate 2 handlers for a same source and remove the later one", "[intr_alloc]")
{
intr_alloc_test_ctx_t ctx = {false, false, false, false };
intr_handle_t handle1, handle2;
// enable SPI2
TEST_BUS_RCC_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
spi_ll_enable_bus_clock(1, true);
spi_ll_reset_register(1);
}
components/esp_hw_support/usb_phy/usb_phy.c
+3 -9
View File
@@ -25,12 +25,6 @@
#include "esp_sleep.h"
#endif
#if !SOC_RCC_IS_INDEPENDENT
#define USB_PHY_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define USB_PHY_RCC_ATOMIC()
#endif
static const char *USBPHY_TAG = "usb_phy";
#define USBPHY_NOT_INIT_ERR_STR "USB_PHY is not initialized"
@@ -283,13 +277,13 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r
phy_context->status = USB_PHY_STATUS_IN_USE;
if (phy_target != USB_PHY_TARGET_UTMI) {
USB_PHY_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
usb_wrap_hal_init(&phy_context->wrap_hal);
}
} else {
#if (SOC_USB_UTMI_PHY_NUM > 0)
usb_utmi_hal_context_t utmi_hal_context; // Unused for now
USB_PHY_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
usb_utmi_hal_init(&utmi_hal_context);
}
#endif
@@ -349,7 +343,7 @@ static void phy_uninstall(void)
if (p_phy_ctrl_obj->ref_count == 0) {
p_phy_ctrl_obj_free = p_phy_ctrl_obj;
p_phy_ctrl_obj = NULL;
USB_PHY_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
// Disable USB peripheral without reset the module
usb_wrap_hal_disable();
#if (SOC_USB_UTMI_PHY_NUM > 0)
components/esp_lcd/i80/esp_lcd_panel_io_i80.c
+2 -2
View File
@@ -145,7 +145,7 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc
}
// initialize HAL layer, so we can call LL APIs later
lcd_hal_init(&bus->hal, bus_id);
LCD_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
lcd_ll_enable_clock(bus->hal.dev, true);
}
// set peripheral clock resolution
@@ -554,7 +554,7 @@ static esp_err_t lcd_i80_select_periph_clock(esp_lcd_i80_bus_handle_t bus, lcd_c
TAG, "get clock source frequency failed");
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), TAG, "clock source enable failed");
LCD_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
lcd_ll_select_clk_src(bus->hal.dev, clk_src);
// force to use integer division, as fractional division might lead to clock jitter
lcd_ll_set_group_clock_coeff(bus->hal.dev, LCD_PERIPH_CLOCK_PRE_SCALE, 0, 0);
components/esp_lcd/priv_include/esp_lcd_common.h
-6
View File
@@ -27,12 +27,6 @@ extern "C" {
#define LCD_PERIPH_CLOCK_PRE_SCALE (2) // This is the minimum divider that can be applied to LCD peripheral
#if SOC_PERIPH_CLK_CTRL_SHARED
#define LCD_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define LCD_CLOCK_SRC_ATOMIC()
#endif
#define LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE 4095
#if SOC_HAS(LCDCAM_I80_LCD) || SOC_HAS(LCDCAM_RGB_LCD)
components/esp_lcd/rgb/esp_lcd_panel_rgb.c
+5 -5
View File
@@ -237,7 +237,7 @@ static esp_err_t lcd_rgb_panel_destroy(esp_rgb_panel_t *rgb_panel)
{
// ensure the HW state machine is stopped
lcd_ll_stop(rgb_panel->hal.dev);
LCD_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
lcd_ll_enable_clock(rgb_panel->hal.dev, false);
}
if (rgb_panel->panel_id >= 0) {
@@ -373,7 +373,7 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf
lcd_hal_init(&rgb_panel->hal, panel_id);
lcd_hal_context_t *hal = &rgb_panel->hal;
// enable clock
LCD_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
lcd_ll_enable_clock(hal->dev, true);
}
// set clock source
@@ -590,7 +590,7 @@ static esp_err_t rgb_panel_init(esp_lcd_panel_t *panel)
// set pixel clock frequency
hal_utils_clk_div_t lcd_clk_div = {};
rgb_panel->timings.pclk_hz = lcd_hal_cal_pclk_freq(&rgb_panel->hal, rgb_panel->src_clk_hz, rgb_panel->timings.pclk_hz, &lcd_clk_div);
LCD_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
lcd_ll_set_group_clock_coeff(rgb_panel->hal.dev, lcd_clk_div.integer, lcd_clk_div.denominator, lcd_clk_div.numerator);
}
// pixel clock phase and polarity
@@ -885,7 +885,7 @@ static esp_err_t lcd_rgb_panel_select_clock_src(esp_rgb_panel_t *rgb_panel, lcd_
TAG, "get clock source frequency failed");
rgb_panel->src_clk_hz = src_clk_hz;
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), TAG, "clock source enable failed");
LCD_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
lcd_ll_select_clk_src(rgb_panel->hal.dev, clk_src);
}
@@ -1220,7 +1220,7 @@ IRAM_ATTR static void lcd_rgb_panel_try_update_pclk(esp_rgb_panel_t *rgb_panel)
if (unlikely(rgb_panel->flags.need_update_pclk)) {
rgb_panel->flags.need_update_pclk = false;
rgb_panel->timings.pclk_hz = lcd_hal_cal_pclk_freq(&rgb_panel->hal, rgb_panel->src_clk_hz, rgb_panel->timings.pclk_hz, &lcd_clk_div);
LCD_CLOCK_SRC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
lcd_ll_set_group_clock_coeff(rgb_panel->hal.dev, lcd_clk_div.integer, lcd_clk_div.denominator, lcd_clk_div.numerator);
}
}
components/esp_pm/pm_impl.c
+2 -3
View File
@@ -48,7 +48,6 @@
#include "esp_private/sleep_cpu.h"
#include "esp_private/sleep_gpio.h"
#include "esp_private/sleep_modem.h"
#include "esp_private/uart_share_hw_ctrl.h"
#include "esp_private/esp_clk_utils.h"
#include "esp_sleep.h"
#include "esp_memory_utils.h"
@@ -979,7 +978,7 @@ void esp_pm_impl_init(void)
ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)clk_source, true));
/* When DFS is enabled, override system setting and use REFTICK as UART clock source */
HP_UART_SRC_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source);
}
uint32_t sclk_freq;
@@ -987,7 +986,7 @@ void esp_pm_impl_init(void)
// Return value unused if asserts are disabled
esp_err_t __attribute__((unused)) err = esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_source, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq);
assert(err == ESP_OK);
HP_UART_SRC_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE, sclk_freq);
}
#endif // CONFIG_ESP_CONSOLE_UART
components/esp_psram/device/esp_psram_impl_ap_hex.c
+1 -4
View File
@@ -15,9 +15,6 @@
#include "hal/mspi_ll.h"
#include "clk_ctrl_os.h"
// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
#define PSRAM_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#define AP_HEX_PSRAM_SYNC_READ 0x0000
#define AP_HEX_PSRAM_SYNC_WRITE 0x8080
#define AP_HEX_PSRAM_BURST_READ 0x2020
@@ -416,7 +413,7 @@ esp_err_t esp_psram_impl_enable(void)
ESP_EARLY_LOGD(TAG, "real_mpll_freq: %d", real_mpll_freq);
#endif
PSRAM_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
psram_ctrlr_ll_enable_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2, true);
psram_ctrlr_ll_reset_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2);
psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_2, PSRAM_CLK_SRC_MPLL);
components/esp_stdio/test_apps/stdio/main/test_app_main.c
-1
View File
@@ -12,7 +12,6 @@
#include "esp_rom_sys.h"
#include "hal/uart_ll.h"
#include "esp_private/uart_share_hw_ctrl.h"
#include "driver/uart.h"
#include "soc/uart_pins.h"
components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c
+3 -3
View File
@@ -9,6 +9,7 @@
#include <sys/param.h>
#include "esp_sleep.h"
#include "esp_private/esp_sleep_internal.h"
#include "esp_private/periph_ctrl.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@@ -29,7 +30,6 @@
#include "esp_timer.h"
#include "esp_private/esp_clk.h"
#include "esp_private/esp_clk_tree_common.h"
#include "esp_private/uart_share_hw_ctrl.h"
#include "esp_random.h"
#include "nvs_flash.h"
#include "nvs.h"
@@ -183,12 +183,12 @@ TEST_CASE("light sleep and frequency switching", "[lightsleep]")
clk_source = UART_SCLK_XTAL;
#endif
esp_clk_tree_enable_src((soc_module_clk_t)clk_source, true);
HP_UART_SRC_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source);
}
uint32_t sclk_freq;
TEST_ESP_OK(uart_get_sclk_freq(clk_source, &sclk_freq));
HP_UART_SRC_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE, sclk_freq);
}
#endif
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+1 -1
View File
@@ -435,6 +435,6 @@ config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
bool
default y
config SOC_PERIPH_CLK_CTRL_SHARED
config SOC_RCC_IS_INDEPENDENT
bool
default y
components/soc/esp32s31/include/soc/soc_caps.h
+1 -1
View File
@@ -286,4 +286,4 @@
#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (1) /*!< Any regi2c operation needs enable the analog i2c master clock first */
#define SOC_PERIPH_CLK_CTRL_SHARED (1) /*!< Peripheral clock control (e.g. set clock source) is shared between various peripherals */
#define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control has own registers for each module */
components/spi_flash/esp_flash_spi_init.c
+2 -8
View File
@@ -40,12 +40,6 @@ __attribute__((unused)) static const char TAG[] = "spi_flash";
#error "Flash chip size equal or over 32MB memory cannot use driver in ROM"
#endif
#if SOC_PERIPH_CLK_CTRL_SHARED
#define GPSPI_FLASH_RCC_CLOCK_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define GPSPI_FLASH_RCC_CLOCK_ATOMIC()
#endif
/* This pointer is defined in ROM and extern-ed on targets where CONFIG_SPI_FLASH_ROM_IMPL = y*/
#if !CONFIG_SPI_FLASH_ROM_IMPL
esp_flash_t *esp_flash_default_chip = NULL;
@@ -293,7 +287,7 @@ static uint32_t init_gpspi_clock(esp_flash_t *chip, const esp_flash_spi_device_c
esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq);
// Enable GPSPI clock
GPSPI_FLASH_RCC_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
gpspi_flash_ll_enable_clock(spi_flash_ll_get_hw(config->host_id), true);
gpspi_flash_ll_set_clk_source(spi_flash_ll_get_hw(config->host_id), clk_src);
}
@@ -349,7 +343,7 @@ static void deinit_gpspi_clock(esp_flash_t *chip)
}
// Disable GPSPI clock
GPSPI_FLASH_RCC_CLOCK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
gpspi_flash_ll_enable_clock(spi_flash_ll_get_hw(host_id), false);
}
components/ulp/lp_core/lp_core.c
+1 -7
View File
@@ -25,12 +25,6 @@
#include "esp32p4/rom/rtc.h"
#endif
#if CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5
#define LP_CORE_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define LP_CORE_RCC_ATOMIC()
#endif
#if ESP_ROM_HAS_LP_ROM
extern uint32_t _rtc_ulp_memory_start;
#endif //ESP_ROM_HAS_LP_ROM
@@ -92,7 +86,7 @@ esp_err_t ulp_lp_core_run(ulp_lp_core_cfg_t* cfg)
#endif //ESP_ROM_HAS_LP_ROM
LP_CORE_RCC_ATOMIC() {
PERIPH_RCC_ATOMIC() {
#if CONFIG_ULP_NORESET_UNDER_DEBUG
/* lp_core module reset causes loss of configured HW breakpoints and dcsr.ebreak* */
if (!esp_cpu_dbgr_is_attached()) {
components/ulp/lp_core/lp_core_uart.c
+1 -2
View File
@@ -17,7 +17,6 @@
#include "hal/rtc_io_types.h"
#include "esp_clk_tree.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/uart_share_hw_ctrl.h"
static const char *LP_UART_TAG = "lp_uart";
@@ -51,7 +50,7 @@ static esp_err_t lp_core_uart_param_config(const lp_core_uart_cfg_t *cfg)
}
// LP UART clock source is mixed with other peripherals in the same register
LP_UART_SRC_CLK_ATOMIC() {
PERIPH_RCC_ATOMIC() {
/* Enable LP UART bus clock */
lp_uart_ll_enable_bus_clock(0, true);
lp_uart_ll_set_source_clk(hal.dev, clk_src);