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Merge branch 'refactor/spi_flash_private_v6.0' into 'release/v6.0'
refactor(spi_flash): reorganize header files, improve encapsulation and simplify ROM implementation (v6.0) See merge request espressif/esp-idf!45488
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@@ -38,6 +38,9 @@ extern "C" {
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#define MSPI_LL_CORE_CLOCK_120_MHZ 120
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#define MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT MSPI_LL_CORE_CLOCK_80_MHZ
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// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow.
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#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1
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/*---------------------------------------------------------------
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MSPI
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---------------------------------------------------------------*/
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@@ -38,6 +38,9 @@ extern "C" {
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#define MSPI_LL_CORE_CLOCK_120_MHZ 120
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#define MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT MSPI_LL_CORE_CLOCK_80_MHZ
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// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow.
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#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1
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/************************** MSPI pll clock configurations **************************/
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/*
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@@ -28,6 +28,9 @@
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//TODO: [ESP32H4] IDF-12390 inherited from verification branch, need check
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// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow.
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#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1
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#ifdef __cplusplus
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extern "C" {
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#endif
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@@ -48,6 +48,9 @@ extern "C" {
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#define MSPI_TIMING_LL_MSPI_ID_0 0
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#define MSPI_TIMING_LL_MSPI_ID_1 1
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// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow.
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#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1
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#define MSPI_TIMING_LL_HP_FLASH_CORE_CLK_DIV 4
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#define MSPI_TIMING_LL_LP_FLASH_CORE_CLK_DIV 6
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#define MSPI_TIMING_LL_FLASH_FDUMMY_RIN_SUPPORTED 1
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