From 30f93c0bc51db0ebfe5a2a1cd592a35ceefdd68c Mon Sep 17 00:00:00 2001 From: Zhou Xiao Date: Wed, 12 Aug 2026 20:33:29 +0800 Subject: [PATCH] refactor(bt/ble_log): share SPI master pin config with IOMUX fallback Move the SPI2 bus, transfer-size and DMA-alignment constants shared by the full-duplex DMA and half-duplex HD transports into ble_log_prph_spi_common.h. Pin numbers stay Kconfig-driven but fall back to the target's native SPI2 IOMUX pins when configured negative, and default to -1 so both transports use the native pins out of the box; any GPIO number still overrides. --- components/bt/common/ble_log/Kconfig.in | 21 +++++++----- .../prph/ble_log_prph_spi_common.h | 34 +++++++++++++++++++ .../src/prph/ble_log_prph_spi_master_dma.c | 10 +++--- .../src/prph/ble_log_prph_spi_master_hd.c | 10 +++--- 4 files changed, 54 insertions(+), 21 deletions(-) create mode 100644 components/bt/common/ble_log/src/internal_include/prph/ble_log_prph_spi_common.h diff --git a/components/bt/common/ble_log/Kconfig.in b/components/bt/common/ble_log/Kconfig.in index 1d8012b4d6d..ed7ef7a6877 100644 --- a/components/bt/common/ble_log/Kconfig.in +++ b/components/bt/common/ble_log/Kconfig.in @@ -219,22 +219,25 @@ if BLE_LOG_ENABLED if BLE_LOG_PRPH_SPI_MASTER_DMA || BLE_LOG_PRPH_SPI_MASTER_HD config BLE_LOG_PRPH_SPI_MASTER_DMA_MOSI_IO_NUM - int "GPIO number of MOSI port for SPI master transport" - default 0 + int "GPIO number of MOSI port for SPI master transport (-1: native SPI2 IOMUX)" + default -1 help - GPIO number of MOSI port for SPI master transport + GPIO number of MOSI port for SPI master transport. Set to -1 + to use the target's native SPI2 IOMUX pin. config BLE_LOG_PRPH_SPI_MASTER_DMA_SCLK_IO_NUM - int "GPIO number of SCLK port for SPI master transport" - default 0 + int "GPIO number of SCLK port for SPI master transport (-1: native SPI2 IOMUX)" + default -1 help - GPIO number of SCLK port for SPI master transport + GPIO number of SCLK port for SPI master transport. Set to -1 + to use the target's native SPI2 IOMUX pin. config BLE_LOG_PRPH_SPI_MASTER_DMA_CS_IO_NUM - int "GPIO number of CS port for SPI master transport" - default 0 + int "GPIO number of CS port for SPI master transport (-1: native SPI2 IOMUX)" + default -1 help - GPIO number of CS port for SPI master transport + GPIO number of CS port for SPI master transport. Set to -1 to + use the target's native SPI2 IOMUX pin. endif if BLE_LOG_PRPH_UART_DMA diff --git a/components/bt/common/ble_log/src/internal_include/prph/ble_log_prph_spi_common.h b/components/bt/common/ble_log/src/internal_include/prph/ble_log_prph_spi_common.h new file mode 100644 index 00000000000..076de131663 --- /dev/null +++ b/components/bt/common/ble_log/src/internal_include/prph/ble_log_prph_spi_common.h @@ -0,0 +1,34 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __BLE_LOG_PRPH_SPI_COMMON_H__ +#define __BLE_LOG_PRPH_SPI_COMMON_H__ + +/* ------------------------------------------------------ */ +/* BLE Log - Peripheral Interface - SPI Master Common IO */ +/* ------------------------------------------------------ */ + +/* INCLUDE */ +#include "hal/spi_types.h" +#include "soc/spi_pins.h" + +/* MACRO */ +#define BLE_LOG_SPI_BUS SPI2_HOST +#define BLE_LOG_SPI_MAX_TRANSFER_SIZE (10240) +#define BLE_LOG_SPI_DMA_ALIGN_BYTES (4U) + +/* Fall back to the target's native SPI2 IOMUX pin when the configured + * GPIO number is negative. */ +#define BLE_LOG_SPI_MOSI_IO_NUM \ + (CONFIG_BLE_LOG_PRPH_SPI_MASTER_DMA_MOSI_IO_NUM < 0 ? \ + SPI2_IOMUX_PIN_NUM_MOSI : CONFIG_BLE_LOG_PRPH_SPI_MASTER_DMA_MOSI_IO_NUM) +#define BLE_LOG_SPI_SCLK_IO_NUM \ + (CONFIG_BLE_LOG_PRPH_SPI_MASTER_DMA_SCLK_IO_NUM < 0 ? \ + SPI2_IOMUX_PIN_NUM_CLK : CONFIG_BLE_LOG_PRPH_SPI_MASTER_DMA_SCLK_IO_NUM) +#define BLE_LOG_SPI_CS_IO_NUM \ + (CONFIG_BLE_LOG_PRPH_SPI_MASTER_DMA_CS_IO_NUM < 0 ? \ + SPI2_IOMUX_PIN_NUM_CS : CONFIG_BLE_LOG_PRPH_SPI_MASTER_DMA_CS_IO_NUM) + +#endif /* __BLE_LOG_PRPH_SPI_COMMON_H__ */ diff --git a/components/bt/common/ble_log/src/prph/ble_log_prph_spi_master_dma.c b/components/bt/common/ble_log/src/prph/ble_log_prph_spi_master_dma.c index e1a7167a7ea..7014a58892b 100644 --- a/components/bt/common/ble_log/src/prph/ble_log_prph_spi_master_dma.c +++ b/components/bt/common/ble_log/src/prph/ble_log_prph_spi_master_dma.c @@ -9,15 +9,13 @@ /* INCLUDE */ #include "ble_log_prph_spi_master_dma.h" +#include "ble_log_prph_spi_common.h" #include "ble_log_lbm.h" #include "esp_timer.h" /* MACRO */ -#define BLE_LOG_SPI_BUS SPI2_HOST -#define BLE_LOG_SPI_MAX_TRANSFER_SIZE (10240) #define BLE_LOG_SPI_TRANS_ITVL_MIN_US (30) -#define BLE_LOG_SPI_DMA_ALIGN_BYTES (4U) #define BLE_LOG_SPI_ALIGN_LOG_PERIOD (256U) #if CONFIG_SPI_MASTER_ISR_IN_IRAM @@ -64,8 +62,8 @@ bool ble_log_prph_init(size_t trans_cnt) /* SPI master initialization */ spi_bus_config_t bus_config = { .miso_io_num = -1, - .mosi_io_num = CONFIG_BLE_LOG_PRPH_SPI_MASTER_DMA_MOSI_IO_NUM, - .sclk_io_num = CONFIG_BLE_LOG_PRPH_SPI_MASTER_DMA_SCLK_IO_NUM, + .mosi_io_num = BLE_LOG_SPI_MOSI_IO_NUM, + .sclk_io_num = BLE_LOG_SPI_SCLK_IO_NUM, .quadwp_io_num = -1, .quadhd_io_num = -1, .max_transfer_sz = BLE_LOG_SPI_MAX_TRANSFER_SIZE, @@ -80,7 +78,7 @@ bool ble_log_prph_init(size_t trans_cnt) spi_device_interface_config_t dev_config = { .clock_speed_hz = SPI_MASTER_FREQ_20M, .mode = 0, - .spics_io_num = CONFIG_BLE_LOG_PRPH_SPI_MASTER_DMA_CS_IO_NUM, + .spics_io_num = BLE_LOG_SPI_CS_IO_NUM, .queue_size = trans_cnt, .post_cb = spi_master_dma_tx_done_cb, .pre_cb = spi_master_dma_pre_tx_cb, diff --git a/components/bt/common/ble_log/src/prph/ble_log_prph_spi_master_hd.c b/components/bt/common/ble_log/src/prph/ble_log_prph_spi_master_hd.c index 11c293408f7..04730fe0f22 100644 --- a/components/bt/common/ble_log/src/prph/ble_log_prph_spi_master_hd.c +++ b/components/bt/common/ble_log/src/prph/ble_log_prph_spi_master_hd.c @@ -9,15 +9,13 @@ /* INCLUDE */ #include "ble_log_prph_spi_master_hd.h" +#include "ble_log_prph_spi_common.h" #include "ble_log_lbm.h" #include "hal/spi_ll.h" #include "hal/spi_types.h" /* MACRO */ -#define BLE_LOG_SPI_BUS SPI2_HOST -#define BLE_LOG_SPI_MAX_TRANSFER_SIZE (10240) -#define BLE_LOG_SPI_DMA_ALIGN_BYTES (4U) #define BLE_LOG_SPI_HD_DATA_DONE BIT(0) #define BLE_LOG_SPI_HD_END_QUEUE_FAILED BIT(1) @@ -61,8 +59,8 @@ bool ble_log_prph_init(size_t trans_cnt) /* SPI master initialization */ spi_bus_config_t bus_config = { .miso_io_num = -1, - .mosi_io_num = CONFIG_BLE_LOG_PRPH_SPI_MASTER_DMA_MOSI_IO_NUM, - .sclk_io_num = CONFIG_BLE_LOG_PRPH_SPI_MASTER_DMA_SCLK_IO_NUM, + .mosi_io_num = BLE_LOG_SPI_MOSI_IO_NUM, + .sclk_io_num = BLE_LOG_SPI_SCLK_IO_NUM, .quadwp_io_num = -1, .quadhd_io_num = -1, .max_transfer_sz = BLE_LOG_SPI_MAX_TRANSFER_SIZE, @@ -78,7 +76,7 @@ bool ble_log_prph_init(size_t trans_cnt) spi_device_interface_config_t dev_config = { .clock_speed_hz = SPI_MASTER_FREQ_20M, .mode = 0, - .spics_io_num = CONFIG_BLE_LOG_PRPH_SPI_MASTER_DMA_CS_IO_NUM, + .spics_io_num = BLE_LOG_SPI_CS_IO_NUM, .queue_size = (int)(trans_cnt * 2), .command_bits = 8, .address_bits = 8,