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fix(esp32h4): fix g0 component build

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This commit is contained in:
Chen Jichang
2025-03-04 16:17:18 +08:00
parent b16095cf00
commit 30f2578e75
13 changed files with 156 additions and 123 deletions
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components/soc/esp32h4/include/soc/periph_defs.h
+72
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@@ -0,0 +1,72 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/interrupts.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
/* HP peripherals */
PERIPH_LEDC_MODULE = 0,
PERIPH_UART0_MODULE,
PERIPH_UART1_MODULE,
PERIPH_USB_DEVICE_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2C1_MODULE,
PERIPH_I2S1_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE,
PERIPH_UHCI0_MODULE,
PERIPH_RMT_MODULE,
PERIPH_PCNT_MODULE,
PERIPH_SPI_MODULE, //SPI1
PERIPH_SPI2_MODULE, //SPI2
PERIPH_TWAI0_MODULE,
PERIPH_TWAI1_MODULE,
PERIPH_RNG_MODULE,
PERIPH_AES_MODULE,
PERIPH_SHA_MODULE,
PERIPH_ECC_MODULE,
PERIPH_HMAC_MODULE,
PERIPH_DS_MODULE,
PERIPH_SDIO_SLAVE_MODULE,
PERIPH_GDMA_MODULE,
PERIPH_MCPWM0_MODULE,
PERIPH_MCPWM1_MODULE,
PERIPH_ETM_MODULE,
PERIPH_PARLIO_MODULE,
PERIPH_SYSTIMER_MODULE,
PERIPH_SARADC_MODULE,
PERIPH_TEMPSENSOR_MODULE,
PERIPH_REGDMA_MODULE,
PERIPH_ASSIST_DEBUG_MODULE,
/* LP peripherals */
PERIPH_LP_I2C0_MODULE,
PERIPH_LP_UART0_MODULE,
/* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */
PERIPH_BT_MODULE,
PERIPH_IEEE802154_MODULE,
PERIPH_COEX_MODULE,
PERIPH_PHY_MODULE,
PERIPH_ANA_I2C_MASTER_MODULE,
PERIPH_MODEM_ETM_MODULE,
PERIPH_MODEM_ADC_COMMON_FE_MODULE,
PERIPH_MODULE_MAX
/* !!! Don't append soc modules here !!! */
} periph_module_t;
#define PERIPH_MODEM_MODULE_MIN PERIPH_WIFI_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE
#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1)
#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX))
#ifdef __cplusplus
}
#endif
components/soc/esp32h4/register/soc/gpio_struct.h
+9 -9
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@@ -641,12 +641,12 @@ typedef union {
} gpio_func_in_sel_cfg_reg_t;
/** Group: Output Configuration Registers */
/** Type of funcn_out_sel_cfg register
/** Type of out_sel_cfg register
* Configuration register for GPIOn output
*/
typedef union {
struct {
/** funcn_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
/** out_sel : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIOn.
* 0: Select signal 0
@@ -661,25 +661,25 @@ typedef union {
* For the detailed signal list, see Table .
* "
*/
uint32_t funcn_out_sel:9;
/** funcn_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
uint32_t out_sel:9;
/** out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.
* 0: Not invert
* 1: Invert
*/
uint32_t funcn_out_inv_sel:1;
/** funcn_oe_sel : R/W; bitpos: [10]; default: 0;
uint32_t out_inv_sel:1;
/** oe_sel : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.
* 0: Use output enable signal from peripheral.
* 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG.
*/
uint32_t funcn_oe_sel:1;
/** funcn_oe_inv_sel : R/W; bitpos: [11]; default: 0;
uint32_t oe_sel:1;
/** oe_inv_sel : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.
* 0: Not invert
* 1: Invert
*/
uint32_t funcn_oe_inv_sel:1;
uint32_t oe_inv_sel:1;
uint32_t reserved_12:20;
};
uint32_t val;
components/soc/esp32h4/register/soc/huk_struct.h
+2 -2
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@@ -149,10 +149,10 @@ typedef union {
* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
*/
uint32_t start:1;
/** continue : WT; bitpos: [1]; default: 0;
/** conti : WT; bitpos: [1]; default: 0;
* Write 1 to start HUK Generator at IDLE state.
*/
uint32_t continue:1;
uint32_t conti:1;
uint32_t reserved_2:30;
};
uint32_t val;
components/soc/esp32h4/register/soc/io_mux_struct.h
+33 -33
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@@ -16,96 +16,96 @@ extern "C" {
*/
typedef union {
struct {
/** mux_gpion_mcu_oe : R/W; bitpos: [0]; default: 0;
/** mcu_oe : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the output of GPIOn in sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_mcu_oe:1;
/** mux_gpion_slp_sel : R/W; bitpos: [1]; default: 0;
uint32_t mcu_oe:1;
/** slp_sel : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enter sleep mode for GPIOn.
* 0: Not enter
* 1: Enter
*/
uint32_t mux_gpion_slp_sel:1;
/** mux_gpion_mcu_wpd : R/W; bitpos: [2]; default: 0;
uint32_t slp_sel:1;
/** mcu_wpd : R/W; bitpos: [2]; default: 0;
* Configure whether or not to enable pull-down resistor of GPIOn in sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_mcu_wpd:1;
/** mux_gpion_mcu_wpu : R/W; bitpos: [3]; default: 0;
uint32_t mcu_wpd:1;
/** mcu_wpu : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable pull-up resistor of GPIOn during sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_mcu_wpu:1;
/** mux_gpion_mcu_ie : R/W; bitpos: [4]; default: 0;
uint32_t mcu_wpu:1;
/** mcu_ie : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable the input of GPIOn during sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_mcu_ie:1;
/** mux_gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0;
uint32_t mcu_ie:1;
/** mcu_drv : R/W; bitpos: [6:5]; default: 0;
* Configures the drive strength of GPIOn during sleep mode.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
uint32_t mux_gpion_mcu_drv:2;
/** mux_gpion_fun_wpd : R/W; bitpos: [7]; default: 0;
uint32_t mcu_drv:2;
/** fun_wpd : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable pull-down resistor of GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_fun_wpd:1;
/** mux_gpion_fun_wpu : R/W; bitpos: [8]; default: 0;
uint32_t fun_wpd:1;
/** fun_wpu : R/W; bitpos: [8]; default: 0;
* Configures whether or not enable pull-up resistor of GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_fun_wpu:1;
/** mux_gpion_fun_ie : R/W; bitpos: [9]; default: 0;
uint32_t fun_wpu:1;
/** fun_ie : R/W; bitpos: [9]; default: 0;
* Configures whether or not to enable input of GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_fun_ie:1;
/** mux_gpion_fun_drv : R/W; bitpos: [11:10]; default: 2;
uint32_t fun_ie:1;
/** fun_drv : R/W; bitpos: [11:10]; default: 2;
* Configures the drive strength of GPIOn.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
uint32_t mux_gpion_fun_drv:2;
/** mux_gpion_mcu_sel : R/W; bitpos: [14:12]; default: 1;
uint32_t fun_drv:2;
/** mcu_sel : R/W; bitpos: [14:12]; default: 1;
* Configures to select IO MUX function for this signal.
* 0: Select Function 0
* 1: Select Function 1
* ......
*/
uint32_t mux_gpion_mcu_sel:3;
/** mux_gpion_filter_en : R/W; bitpos: [15]; default: 0;
uint32_t mcu_sel:3;
/** filter_en : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable filter for pin input signals.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_filter_en:1;
/** mux_gpion_hys_en : R/W; bitpos: [16]; default: 0;
uint32_t filter_en:1;
/** hys_en : R/W; bitpos: [16]; default: 0;
* Configures whether or not to enable the hysteresis function of the pin when
* IO_MUX_GPIOn_HYS_SEL is set to 1.
* 0: Disable
* 1: Enable
*/
uint32_t mux_gpion_hys_en:1;
/** mux_gpion_hys_sel : R/W; bitpos: [17]; default: 0;
uint32_t hys_en:1;
/** hys_sel : R/W; bitpos: [17]; default: 0;
* Configures to choose the signal for enabling the hysteresis function for GPIOn.
* 0: Choose the output enable signal of eFuse
* 1: Choose the output enable signal of IO_MUX_GPIOn_HYS_EN
*/
uint32_t mux_gpion_hys_sel:1;
uint32_t hys_sel:1;
uint32_t reserved_18:14;
};
uint32_t val;
@@ -129,15 +129,15 @@ typedef union {
typedef struct {
volatile io_mux_gpion_reg_t mux_gpion[40];
volatile io_mux_gpion_reg_t gpio[40];
uint32_t reserved_0a0[87];
volatile io_mux_date_reg_t mux_date;
} io_dev_t;
volatile io_mux_date_reg_t date;
} io_mux_dev_t;
extern io_dev_t IO_MUX;
extern io_mux_dev_t IO_MUX;
#ifndef __cplusplus
_Static_assert(sizeof(io_dev_t) == 0x200, "Invalid size of io_dev_t structure");
_Static_assert(sizeof(io_mux_dev_t) == 0x200, "Invalid size of io_mux_dev_t structure");
#endif
#ifdef __cplusplus
components/soc/esp32h4/register/soc/keymng_struct.h
+4 -4
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@@ -221,13 +221,13 @@ typedef union {
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to continue Key Manager operation at LOAD/GAIN state.
* Write 1 to conti Key Manager operation at LOAD/GAIN state.
*/
uint32_t start:1;
/** continue : WT; bitpos: [1]; default: 0;
/** conti : WT; bitpos: [1]; default: 0;
* Write 1 to start Key Manager at IDLE state.
*/
uint32_t continue:1;
uint32_t conti:1;
uint32_t reserved_2:30;
};
uint32_t val;
@@ -349,7 +349,7 @@ typedef struct {
volatile keymng_int_st_reg_t int_st;
volatile keymng_int_ena_reg_t int_ena;
volatile keymng_int_clr_reg_t int_clr;
volatile keymng_static_reg_t static;
volatile keymng_static_reg_t static_cfg;
volatile keymng_lock_reg_t lock;
volatile keymng_conf_reg_t conf;
volatile keymng_start_reg_t start;
components/soc/esp32h4/register/soc/lp_peri_reg.h → components/soc/esp32h4/register/soc/lpperi_reg.h
View File
components/soc/esp32h4/register/soc/lp_peri_struct.h → components/soc/esp32h4/register/soc/lpperi_struct.h
View File
components/soc/esp32h4/register/soc/sha_struct.h
+5 -5
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@@ -73,10 +73,10 @@ typedef union {
*/
typedef union {
struct {
/** continue : WO; bitpos: [0]; default: 0;
/** conti : WO; bitpos: [0]; default: 0;
* Continue typical sha.
*/
uint32_t continue:1;
uint32_t conti:1;
uint32_t reserved_1:31;
};
uint32_t val;
@@ -196,7 +196,7 @@ typedef struct {
uint32_t reserved_004[2];
volatile sha_dma_block_num_reg_t dma_block_num;
volatile sha_start_reg_t start;
volatile sha_continue_reg_t continue;
volatile sha_continue_reg_t conti;
volatile sha_busy_reg_t busy;
volatile sha_dma_start_reg_t dma_start;
volatile sha_dma_continue_reg_t dma_continue;
@@ -205,8 +205,8 @@ typedef struct {
volatile sha_date_reg_t date;
volatile sha_dma_rx_reset_reg_t dma_rx_reset;
uint32_t reserved_034[3];
volatile uint32_t 2_sm_3_h[16];
volatile uint32_t 2_sm_3_m[32];
volatile uint32_t h[16];
volatile uint32_t m[32];
} sha_dev_t;
extern sha_dev_t SHA;
components/soc/esp32h4/register/soc/timer_group_reg.h
+1 -1
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@@ -11,7 +11,7 @@
extern "C" {
#endif
#define DR_REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define DR_REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i)*0x1000)
/** TIMG_T0CONFIG_REG register
* Timer 0 configuration register