Merge branch 'fix/handle_shared_intr_v5.5' into 'release/v5.5'

Fix/handle shared intr (v5.5)

See merge request espressif/esp-idf!44071

components/hal/esp32c6/include/hal/ledc_ll.h

@@ -31,6 +31,8 @@ extern "C" {
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
 #define LEDC_LL_GLOBAL_CLOCKS      SOC_LEDC_CLKS
+/// Get the mask of the fade end interrupt status register.
+#define LEDC_LL_FADE_END_INTR_MASK  (0x3fUL << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S)
 
 #define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST
 
@@ -625,7 +627,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m
  *
  * @param hw Beginning address of the peripheral registers
  * @param speed_mode LEDC speed_mode, low-speed mode only
- * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
  * @param intr_status The fade end interrupt status
  *
  * @return None
@@ -637,6 +638,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t
     *intr_status = (value >> int_en_base) & 0xff;
 }
 
+/**
+ * @brief Get the address of the fade end interrupt status register.
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @return Pointer to the fade end interrupt status register.
+ */
+static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
+
 /**
  * @brief Clear fade end interrupt status
  *

components/hal/esp32c6/include/hal/sdio_slave_ll.h

@@ -37,6 +37,8 @@ extern "C" {
 #define sdio_slave_ll_get_host(ID)  (&HOST)
 /// Get address of the only HINF registers
 #define sdio_slave_ll_get_hinf(ID)  (&HINF)
+/// Get the mask of the interrupt status.
+#define sdio_slave_ll_intr_status_mask  (0xff | SDIO_SLC0_RX_DONE_INT_ST | SDIO_SLC0_RX_EOF_INT_ST | SDIO_SLC0_TX_DONE_INT_ST)
 
 /*
  *  SLC2 DMA Desc struct, aka sdio_slave_ll_desc_t
@@ -533,6 +535,17 @@ static inline void sdio_slave_ll_slvint_fetch_clear(slc_dev_t *slc, sdio_slave_l
     slc->slc0int_clr.val = slv_int;
 }
 
+/**
+ * Get the address of the interrupt status register.
+ *
+ * @param slc Address of the SLC registers
+ * @return Address of the interrupt status register
+ */
+static inline volatile void* sdio_slave_ll_get_intr_status_reg(slc_dev_t *slc)
+{
+    return &slc->slc0int_st.val;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32c6/include/hal/spi_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */

components/hal/esp32c6/include/hal/uart_ll.h

@@ -507,6 +507,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
     return hw->int_st.val;
 }
 
+FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
 /**
  * @brief  Clear the UART interrupt status based on the given mask.
  *