feat(esp_driver_i2s): support clk tree source management across I2S components

components/esp_driver_i2s/i2s_common.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -57,6 +57,7 @@
 
 #include "clk_ctrl_os.h"
 #include "esp_clk_tree.h"
+#include "esp_private/esp_clk_tree_common.h"
 #include "esp_intr_alloc.h"
 #include "esp_check.h"
 #include "esp_attr.h"
@@ -1028,6 +1029,7 @@ esp_err_t i2s_new_channel(const i2s_chan_config_t *chan_cfg, i2s_chan_handle_t *
         i2s_obj->tx_chan->start = i2s_tx_channel_start;
         i2s_obj->tx_chan->stop = i2s_tx_channel_stop;
         *tx_handle = i2s_obj->tx_chan;
+        esp_clk_tree_enable_src((soc_module_clk_t)i2s_ll_tx_clk_get_src(i2s_obj->hal.dev), true);
         ESP_LOGD(TAG, "tx channel is registered on I2S%d successfully", i2s_obj->id);
     }
     /* Register and specify the rx handle */
@@ -1042,6 +1044,7 @@ esp_err_t i2s_new_channel(const i2s_chan_config_t *chan_cfg, i2s_chan_handle_t *
         i2s_obj->rx_chan->start = i2s_rx_channel_start;
         i2s_obj->rx_chan->stop = i2s_rx_channel_stop;
         *rx_handle = i2s_obj->rx_chan;
+        esp_clk_tree_enable_src((soc_module_clk_t)i2s_ll_rx_clk_get_src(i2s_obj->hal.dev), true);
         ESP_LOGD(TAG, "rx channel is registered on I2S%d successfully", i2s_obj->id);
     }
 
@@ -1086,7 +1089,18 @@ esp_err_t i2s_del_channel(i2s_chan_handle_t handle)
             i2s_ll_rx_disable_clock(handle->controller->hal.dev);
         }
     }
+    if (handle->clk_src != I2S_CLK_SRC_EXTERNAL)
 #endif
+    {
+        i2s_clock_src_t clk_src = handle->clk_src;
+#ifdef I2S_LL_DEFAULT_CLK_SRC
+        if (clk_src == I2S_CLK_SRC_DEFAULT) {
+            clk_src = I2S_LL_DEFAULT_CLK_SRC;
+        }
+#endif
+        esp_clk_tree_enable_src((soc_module_clk_t)clk_src, false);
+    }
+
 #if SOC_I2S_SUPPORTS_APLL
     if (handle->apll_en) {
         /* Must switch back to D2CLK on ESP32-S2,

components/esp_driver_i2s/i2s_pdm.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,6 +19,7 @@
 #include "driver/gpio.h"
 #include "driver/i2s_pdm.h"
 #include "i2s_private.h"
+#include "esp_private/esp_clk_tree_common.h"
 #include "clk_ctrl_os.h"
 #include "esp_intr_alloc.h"
 #include "esp_check.h"
@@ -82,6 +83,19 @@ static esp_err_t i2s_pdm_tx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_tx
     /* Calculate clock parameters */
     ESP_RETURN_ON_ERROR(i2s_pdm_tx_calculate_clock(handle, clk_cfg, &clk_info), TAG, "clock calculate failed");
 
+#if SOC_I2S_HW_VERSION_2
+    i2s_clock_src_t old_clk_src = handle->clk_src;
+    if (clk_cfg->clk_src != I2S_CLK_SRC_EXTERNAL)
+#endif
+    {
+        i2s_clock_src_t clk_src = clk_cfg->clk_src;
+#ifdef I2S_LL_DEFAULT_CLK_SRC
+        if (clk_src == I2S_CLK_SRC_DEFAULT) {
+            clk_src = I2S_LL_DEFAULT_CLK_SRC;
+        }
+#endif
+        esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true);
+    }
     hal_utils_clk_div_t ret_mclk_div = {};
     portENTER_CRITICAL(&g_i2s.spinlock);
     /* Set clock configurations in HAL*/
@@ -106,6 +120,12 @@ static esp_err_t i2s_pdm_tx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_tx
     handle->curr_mclk_hz = handle->origin_mclk_hz;
     handle->bclk_hz = clk_info.bclk;
 
+#if SOC_I2S_HW_VERSION_2
+    if (old_clk_src != I2S_CLK_SRC_EXTERNAL) {
+        esp_clk_tree_enable_src((soc_module_clk_t)old_clk_src, false);
+    }
+#endif
+
     ESP_LOGD(TAG, "Clock division info: [sclk] %"PRIu32" Hz [mdiv] %"PRIu32" %"PRIu32"/%"PRIu32" [mclk] %"PRIu32" Hz [bdiv] %d [bclk] %"PRIu32" Hz",
              clk_info.sclk, ret_mclk_div.integer, ret_mclk_div.numerator, ret_mclk_div.denominator, handle->origin_mclk_hz, clk_info.bclk_div, clk_info.bclk);
 
@@ -419,6 +439,19 @@ static esp_err_t i2s_pdm_rx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_rx
     /* Calculate clock parameters */
     ESP_RETURN_ON_ERROR(i2s_pdm_rx_calculate_clock(handle, clk_cfg, &clk_info), TAG, "clock calculate failed");
 
+#if SOC_I2S_HW_VERSION_2
+    i2s_clock_src_t old_clk_src = handle->clk_src;
+    if (clk_cfg->clk_src != I2S_CLK_SRC_EXTERNAL)
+#endif
+    {
+        i2s_clock_src_t clk_src = clk_cfg->clk_src;
+#ifdef I2S_LL_DEFAULT_CLK_SRC
+        if (clk_src == I2S_CLK_SRC_DEFAULT) {
+            clk_src = I2S_LL_DEFAULT_CLK_SRC;
+        }
+#endif
+        esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true);
+    }
     hal_utils_clk_div_t ret_mclk_div = {};
     portENTER_CRITICAL(&g_i2s.spinlock);
     /* Set clock configurations in HAL*/
@@ -437,6 +470,13 @@ static esp_err_t i2s_pdm_rx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_rx
     handle->origin_mclk_hz = ((uint64_t)clk_info.sclk * ret_mclk_div.denominator) / tmp_div;
     handle->curr_mclk_hz = handle->origin_mclk_hz;
     handle->bclk_hz = clk_info.bclk;
+
+#if SOC_I2S_HW_VERSION_2
+    if (old_clk_src != I2S_CLK_SRC_EXTERNAL) {
+        esp_clk_tree_enable_src((soc_module_clk_t)old_clk_src, false);
+    }
+#endif
+
     ESP_LOGD(TAG, "Clock division info: [sclk] %"PRIu32" Hz [mdiv] %"PRIu32" %"PRIu32"/%"PRIu32" [mclk] %"PRIu32" Hz [bdiv] %d [bclk] %"PRIu32" Hz",
              clk_info.sclk, ret_mclk_div.integer, ret_mclk_div.numerator, ret_mclk_div.denominator, handle->origin_mclk_hz, clk_info.bclk_div, clk_info.bclk);
 

components/esp_driver_i2s/i2s_std.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,6 +20,7 @@
 #include "driver/gpio.h"
 #include "driver/i2s_std.h"
 #include "i2s_private.h"
+#include "esp_private/esp_clk_tree_common.h"
 #include "clk_ctrl_os.h"
 #include "esp_intr_alloc.h"
 #include "esp_check.h"
@@ -85,6 +86,19 @@ static esp_err_t i2s_std_set_clock(i2s_chan_handle_t handle, const i2s_std_clk_c
     /* Calculate clock parameters */
     ESP_RETURN_ON_ERROR(i2s_std_calculate_clock(handle, clk_cfg, &clk_info), TAG, "clock calculate failed");
 
+#if SOC_I2S_HW_VERSION_2
+    i2s_clock_src_t old_clk_src = handle->clk_src;
+    if (clk_cfg->clk_src != I2S_CLK_SRC_EXTERNAL)
+#endif
+    {
+        i2s_clock_src_t clk_src = clk_cfg->clk_src;
+#ifdef I2S_LL_DEFAULT_CLK_SRC
+        if (clk_src == I2S_CLK_SRC_DEFAULT) {
+            clk_src = I2S_LL_DEFAULT_CLK_SRC;
+        }
+#endif
+        esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true);
+    }
     hal_utils_clk_div_t ret_mclk_div = {};
     portENTER_CRITICAL(&g_i2s.spinlock);
     /* Set clock configurations in HAL*/
@@ -107,6 +121,12 @@ static esp_err_t i2s_std_set_clock(i2s_chan_handle_t handle, const i2s_std_clk_c
     handle->curr_mclk_hz = handle->origin_mclk_hz;
     handle->bclk_hz = clk_info.bclk;
 
+#if SOC_I2S_HW_VERSION_2
+    if (old_clk_src != I2S_CLK_SRC_EXTERNAL) {
+        esp_clk_tree_enable_src((soc_module_clk_t)old_clk_src, false);
+    }
+#endif
+
     ESP_LOGD(TAG, "Clock division info: [sclk] %"PRIu32" Hz [mdiv] %"PRIu32" %"PRIu32"/%"PRIu32" [mclk] %"PRIu32" Hz [bdiv] %d [bclk] %"PRIu32" Hz",
              clk_info.sclk, ret_mclk_div.integer, ret_mclk_div.numerator, ret_mclk_div.denominator, handle->origin_mclk_hz, clk_info.bclk_div, clk_info.bclk);
 

components/esp_driver_i2s/i2s_tdm.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,6 +20,7 @@
 #include "driver/gpio.h"
 #include "driver/i2s_tdm.h"
 #include "i2s_private.h"
+#include "esp_private/esp_clk_tree_common.h"
 #include "clk_ctrl_os.h"
 #include "esp_intr_alloc.h"
 #include "esp_check.h"
@@ -82,6 +83,19 @@ static esp_err_t i2s_tdm_set_clock(i2s_chan_handle_t handle, const i2s_tdm_clk_c
     /* Calculate clock parameters */
     ESP_RETURN_ON_ERROR(i2s_tdm_calculate_clock(handle, clk_cfg, &clk_info), TAG, "clock calculate failed");
 
+#if SOC_I2S_HW_VERSION_2
+    i2s_clock_src_t old_clk_src = handle->clk_src;
+    if (clk_cfg->clk_src != I2S_CLK_SRC_EXTERNAL)
+#endif
+    {
+        i2s_clock_src_t clk_src = clk_cfg->clk_src;
+#ifdef I2S_LL_DEFAULT_CLK_SRC
+        if (clk_src == I2S_CLK_SRC_DEFAULT) {
+            clk_src = I2S_LL_DEFAULT_CLK_SRC;
+        }
+#endif
+        esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true);
+    }
     hal_utils_clk_div_t ret_mclk_div = {};
     portENTER_CRITICAL(&g_i2s.spinlock);
     /* Set clock configurations in HAL*/
@@ -104,6 +118,12 @@ static esp_err_t i2s_tdm_set_clock(i2s_chan_handle_t handle, const i2s_tdm_clk_c
     handle->curr_mclk_hz = handle->origin_mclk_hz;
     handle->bclk_hz = clk_info.bclk;
 
+#if SOC_I2S_HW_VERSION_2
+    if (old_clk_src != I2S_CLK_SRC_EXTERNAL) {
+        esp_clk_tree_enable_src((soc_module_clk_t)old_clk_src, false);
+    }
+#endif
+
     ESP_LOGD(TAG, "Clock division info: [sclk] %"PRIu32" Hz [mdiv] %"PRIu32" %"PRIu32"/%"PRIu32" [mclk] %"PRIu32" Hz [bdiv] %d [bclk] %"PRIu32" Hz",
              clk_info.sclk, ret_mclk_div.integer, ret_mclk_div.numerator, ret_mclk_div.denominator, handle->origin_mclk_hz, clk_info.bclk_div, clk_info.bclk);
 

components/esp_hal_i2s/esp32/include/hal/i2s_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -324,6 +324,28 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
     hw->clkm_conf.clka_en = (src == I2S_CLK_SRC_APLL) ? 1 : 0;
 }
 
+/**
+ * @brief Get TX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current TX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_tx_clk_get_src(i2s_dev_t *hw)
+{
+    return (hw->clkm_conf.clka_en) ? (i2s_clock_src_t)I2S_CLK_SRC_APLL : (i2s_clock_src_t)I2S_CLK_SRC_PLL_160M;
+}
+
+/**
+ * @brief Get RX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current RX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_rx_clk_get_src(i2s_dev_t *hw)
+{
+    return (hw->clkm_conf.clka_en) ? (i2s_clock_src_t)I2S_CLK_SRC_APLL : (i2s_clock_src_t)I2S_CLK_SRC_PLL_160M;
+}
+
 /**
  * @brief Set I2S tx bck div num
  *

components/esp_hal_i2s/esp32c3/include/hal/i2s_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -269,6 +269,38 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
     }
 }
 
+/**
+ * @brief Get TX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current TX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_tx_clk_get_src(i2s_dev_t *hw)
+{
+    switch (hw->tx_clkm_conf.tx_clk_sel) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 2: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_160M;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
+/**
+ * @brief Get RX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current RX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_rx_clk_get_src(i2s_dev_t *hw)
+{
+    switch (hw->rx_clkm_conf.rx_clk_sel) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 2: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_160M;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
 /**
  * @brief Set I2S tx bck div num
  *

components/esp_hal_i2s/esp32c5/include/hal/i2s_ll.h

@@ -289,6 +289,42 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
     }
 }
 
+/**
+ * @brief Get TX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current TX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_tx_clk_get_src(i2s_dev_t *hw)
+{
+    (void)hw;
+    switch (PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 1: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_240M;
+    case 2: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_160M;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
+/**
+ * @brief Get RX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current RX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_rx_clk_get_src(i2s_dev_t *hw)
+{
+    (void)hw;
+    switch (PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 1: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_240M;
+    case 2: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_160M;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
 /**
  * @brief Set I2S tx bck div num
  *

components/esp_hal_i2s/esp32c6/include/hal/i2s_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -287,6 +287,42 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
     }
 }
 
+/**
+ * @brief Get TX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current TX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_tx_clk_get_src(i2s_dev_t *hw)
+{
+    (void)hw;
+    switch (PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 1: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_240M;
+    case 2: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_160M;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
+/**
+ * @brief Get RX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current RX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_rx_clk_get_src(i2s_dev_t *hw)
+{
+    (void)hw;
+    switch (PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 1: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_240M;
+    case 2: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_160M;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
 /**
  * @brief Set I2S tx bck div num
  *

components/esp_hal_i2s/esp32c61/include/hal/i2s_ll.h

@@ -290,6 +290,42 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
     }
 }
 
+/**
+ * @brief Get TX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current TX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_tx_clk_get_src(i2s_dev_t *hw)
+{
+    (void)hw;
+    switch (PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 1: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_120M;
+    case 2: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_160M;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
+/**
+ * @brief Get RX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current RX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_rx_clk_get_src(i2s_dev_t *hw)
+{
+    (void)hw;
+    switch (PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 1: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_120M;
+    case 2: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_160M;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
 /**
  * @brief Set I2S tx bck div num
  *

components/esp_hal_i2s/esp32h2/include/hal/i2s_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -287,6 +287,42 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
     }
 }
 
+/**
+ * @brief Get TX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current TX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_tx_clk_get_src(i2s_dev_t *hw)
+{
+    (void)hw;
+    switch (PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 1: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_96M;
+    case 2: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_64M;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
+/**
+ * @brief Get RX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current RX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_rx_clk_get_src(i2s_dev_t *hw)
+{
+    (void)hw;
+    switch (PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 1: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_96M;
+    case 2: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_64M;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
 /**
  * @brief Set I2S tx bck div num
  *

components/esp_hal_i2s/esp32h21/include/hal/i2s_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -287,6 +287,40 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
     }
 }
 
+/**
+ * @brief Get TX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current TX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_tx_clk_get_src(i2s_dev_t *hw)
+{
+    (void)hw;
+    switch (PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 1: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_96M;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
+/**
+ * @brief Get RX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current RX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_rx_clk_get_src(i2s_dev_t *hw)
+{
+    (void)hw;
+    switch (PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 1: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_96M;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
 /**
  * @brief Set I2S tx bck div num
  *

components/esp_hal_i2s/esp32h4/include/hal/i2s_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -291,6 +291,40 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
     }
 }
 
+/**
+ * @brief Get TX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current TX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_tx_clk_get_src(i2s_dev_t *hw)
+{
+    (void)hw;
+    switch (PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 1: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_96M;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
+/**
+ * @brief Get RX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current RX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_rx_clk_get_src(i2s_dev_t *hw)
+{
+    (void)hw;
+    switch (PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 1: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_96M;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
 /**
  * @brief Set I2S tx bck div num
  *

components/esp_hal_i2s/esp32p4/include/hal/i2s_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -522,6 +522,68 @@ static inline void _i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
         _i2s_ll_rx_clk_set_src(__VA_ARGS__); \
     } while(0)
 
+/**
+ * @brief Get TX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current TX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_tx_clk_get_src(i2s_dev_t *hw)
+{
+    uint32_t clk_src;
+    switch (I2S_LL_GET_ID(hw)) {
+    case 0:
+        clk_src = HP_SYS_CLKRST.peri_clk_ctrl13.reg_i2s0_tx_clk_src_sel;
+        break;
+    case 1:
+        clk_src = HP_SYS_CLKRST.peri_clk_ctrl15.reg_i2s1_tx_clk_src_sel;
+        break;
+    case 2:
+        clk_src = HP_SYS_CLKRST.peri_clk_ctrl18.reg_i2s2_tx_clk_src_sel;
+        break;
+    default:
+        return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+    switch (clk_src) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 1: return (i2s_clock_src_t)I2S_CLK_SRC_APLL;
+    case 2: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_160M;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
+/**
+ * @brief Get RX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current RX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_rx_clk_get_src(i2s_dev_t *hw)
+{
+    uint32_t clk_src;
+    switch (I2S_LL_GET_ID(hw)) {
+    case 0:
+        clk_src = HP_SYS_CLKRST.peri_clk_ctrl11.reg_i2s0_rx_clk_src_sel;
+        break;
+    case 1:
+        clk_src = HP_SYS_CLKRST.peri_clk_ctrl14.reg_i2s1_rx_clk_src_sel;
+        break;
+    case 2:
+        clk_src = HP_SYS_CLKRST.peri_clk_ctrl17.reg_i2s2_rx_clk_src_sel;
+        break;
+    default:
+        return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+    switch (clk_src) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 1: return (i2s_clock_src_t)I2S_CLK_SRC_APLL;
+    case 2: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_160M;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
 /**
  * @brief Set I2S tx bck div num
  *

components/esp_hal_i2s/esp32s2/include/hal/i2s_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -303,6 +303,28 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
     hw->clkm_conf.clk_sel = (src == I2S_CLK_SRC_APLL) ? 1 : 2;
 }
 
+/**
+ * @brief Get TX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current TX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_tx_clk_get_src(i2s_dev_t *hw)
+{
+    return (hw->clkm_conf.clk_sel == 1) ? (i2s_clock_src_t)I2S_CLK_SRC_APLL : (i2s_clock_src_t)I2S_CLK_SRC_PLL_160M;
+}
+
+/**
+ * @brief Get RX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current RX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_rx_clk_get_src(i2s_dev_t *hw)
+{
+    return (hw->clkm_conf.clk_sel == 1) ? (i2s_clock_src_t)I2S_CLK_SRC_APLL : (i2s_clock_src_t)I2S_CLK_SRC_PLL_160M;
+}
+
 /**
  * @brief Set I2S tx bck div num
  *

components/esp_hal_i2s/esp32s3/include/hal/i2s_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -281,6 +281,41 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
         break;
     }
 }
+
+/**
+ * @brief Get TX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current TX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_tx_clk_get_src(i2s_dev_t *hw)
+{
+    switch (hw->tx_clkm_conf.tx_clk_sel) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 1: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_240M;
+    case 2: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_160M;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
+/**
+ * @brief Get RX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return Current RX clock source (i2s_clock_src_t).
+ */
+static inline i2s_clock_src_t i2s_ll_rx_clk_get_src(i2s_dev_t *hw)
+{
+    switch (hw->rx_clkm_conf.rx_clk_sel) {
+    case 0: return (i2s_clock_src_t)I2S_CLK_SRC_XTAL;
+    case 1: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_240M;
+    case 2: return (i2s_clock_src_t)I2S_CLK_SRC_PLL_160M;
+    case 3: return (i2s_clock_src_t)I2S_CLK_SRC_EXTERNAL;
+    default: return (i2s_clock_src_t)I2S_CLK_SRC_DEFAULT;
+    }
+}
+
 /**
  * @brief Set I2S tx bck div num
  *