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feat(esp_driver_i2s): support clk tree source management across I2S components

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This commit is contained in:
wuzhenghui
2026-03-05 10:11:56 +08:00
parent 51cca0a88f
commit 2f41c43f3b
15 changed files with 492 additions and 13 deletions
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components/esp_driver_i2s/i2s_common.c
+15 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -57,6 +57,7 @@
#include "clk_ctrl_os.h"
#include "esp_clk_tree.h"
#include "esp_private/esp_clk_tree_common.h"
#include "esp_intr_alloc.h"
#include "esp_check.h"
#include "esp_attr.h"
@@ -1028,6 +1029,7 @@ esp_err_t i2s_new_channel(const i2s_chan_config_t *chan_cfg, i2s_chan_handle_t *
i2s_obj->tx_chan->start = i2s_tx_channel_start;
i2s_obj->tx_chan->stop = i2s_tx_channel_stop;
*tx_handle = i2s_obj->tx_chan;
esp_clk_tree_enable_src((soc_module_clk_t)i2s_ll_tx_clk_get_src(i2s_obj->hal.dev), true);
ESP_LOGD(TAG, "tx channel is registered on I2S%d successfully", i2s_obj->id);
}
/* Register and specify the rx handle */
@@ -1042,6 +1044,7 @@ esp_err_t i2s_new_channel(const i2s_chan_config_t *chan_cfg, i2s_chan_handle_t *
i2s_obj->rx_chan->start = i2s_rx_channel_start;
i2s_obj->rx_chan->stop = i2s_rx_channel_stop;
*rx_handle = i2s_obj->rx_chan;
esp_clk_tree_enable_src((soc_module_clk_t)i2s_ll_rx_clk_get_src(i2s_obj->hal.dev), true);
ESP_LOGD(TAG, "rx channel is registered on I2S%d successfully", i2s_obj->id);
}
@@ -1086,7 +1089,18 @@ esp_err_t i2s_del_channel(i2s_chan_handle_t handle)
i2s_ll_rx_disable_clock(handle->controller->hal.dev);
}
}
if (handle->clk_src != I2S_CLK_SRC_EXTERNAL)
#endif
{
i2s_clock_src_t clk_src = handle->clk_src;
#ifdef I2S_LL_DEFAULT_CLK_SRC
if (clk_src == I2S_CLK_SRC_DEFAULT) {
clk_src = I2S_LL_DEFAULT_CLK_SRC;
}
#endif
esp_clk_tree_enable_src((soc_module_clk_t)clk_src, false);
}
#if SOC_I2S_SUPPORTS_APLL
if (handle->apll_en) {
/* Must switch back to D2CLK on ESP32-S2,
components/esp_driver_i2s/i2s_pdm.c
+41 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -19,6 +19,7 @@
#include "driver/gpio.h"
#include "driver/i2s_pdm.h"
#include "i2s_private.h"
#include "esp_private/esp_clk_tree_common.h"
#include "clk_ctrl_os.h"
#include "esp_intr_alloc.h"
#include "esp_check.h"
@@ -82,6 +83,19 @@ static esp_err_t i2s_pdm_tx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_tx
/* Calculate clock parameters */
ESP_RETURN_ON_ERROR(i2s_pdm_tx_calculate_clock(handle, clk_cfg, &clk_info), TAG, "clock calculate failed");
#if SOC_I2S_HW_VERSION_2
i2s_clock_src_t old_clk_src = handle->clk_src;
if (clk_cfg->clk_src != I2S_CLK_SRC_EXTERNAL)
#endif
{
i2s_clock_src_t clk_src = clk_cfg->clk_src;
#ifdef I2S_LL_DEFAULT_CLK_SRC
if (clk_src == I2S_CLK_SRC_DEFAULT) {
clk_src = I2S_LL_DEFAULT_CLK_SRC;
}
#endif
esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true);
}
hal_utils_clk_div_t ret_mclk_div = {};
portENTER_CRITICAL(&g_i2s.spinlock);
/* Set clock configurations in HAL*/
@@ -106,6 +120,12 @@ static esp_err_t i2s_pdm_tx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_tx
handle->curr_mclk_hz = handle->origin_mclk_hz;
handle->bclk_hz = clk_info.bclk;
#if SOC_I2S_HW_VERSION_2
if (old_clk_src != I2S_CLK_SRC_EXTERNAL) {
esp_clk_tree_enable_src((soc_module_clk_t)old_clk_src, false);
}
#endif
ESP_LOGD(TAG, "Clock division info: [sclk] %"PRIu32" Hz [mdiv] %"PRIu32" %"PRIu32"/%"PRIu32" [mclk] %"PRIu32" Hz [bdiv] %d [bclk] %"PRIu32" Hz",
clk_info.sclk, ret_mclk_div.integer, ret_mclk_div.numerator, ret_mclk_div.denominator, handle->origin_mclk_hz, clk_info.bclk_div, clk_info.bclk);
@@ -419,6 +439,19 @@ static esp_err_t i2s_pdm_rx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_rx
/* Calculate clock parameters */
ESP_RETURN_ON_ERROR(i2s_pdm_rx_calculate_clock(handle, clk_cfg, &clk_info), TAG, "clock calculate failed");
#if SOC_I2S_HW_VERSION_2
i2s_clock_src_t old_clk_src = handle->clk_src;
if (clk_cfg->clk_src != I2S_CLK_SRC_EXTERNAL)
#endif
{
i2s_clock_src_t clk_src = clk_cfg->clk_src;
#ifdef I2S_LL_DEFAULT_CLK_SRC
if (clk_src == I2S_CLK_SRC_DEFAULT) {
clk_src = I2S_LL_DEFAULT_CLK_SRC;
}
#endif
esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true);
}
hal_utils_clk_div_t ret_mclk_div = {};
portENTER_CRITICAL(&g_i2s.spinlock);
/* Set clock configurations in HAL*/
@@ -437,6 +470,13 @@ static esp_err_t i2s_pdm_rx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_rx
handle->origin_mclk_hz = ((uint64_t)clk_info.sclk * ret_mclk_div.denominator) / tmp_div;
handle->curr_mclk_hz = handle->origin_mclk_hz;
handle->bclk_hz = clk_info.bclk;
#if SOC_I2S_HW_VERSION_2
if (old_clk_src != I2S_CLK_SRC_EXTERNAL) {
esp_clk_tree_enable_src((soc_module_clk_t)old_clk_src, false);
}
#endif
ESP_LOGD(TAG, "Clock division info: [sclk] %"PRIu32" Hz [mdiv] %"PRIu32" %"PRIu32"/%"PRIu32" [mclk] %"PRIu32" Hz [bdiv] %d [bclk] %"PRIu32" Hz",
clk_info.sclk, ret_mclk_div.integer, ret_mclk_div.numerator, ret_mclk_div.denominator, handle->origin_mclk_hz, clk_info.bclk_div, clk_info.bclk);
components/esp_driver_i2s/i2s_std.c
+21 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -20,6 +20,7 @@
#include "driver/gpio.h"
#include "driver/i2s_std.h"
#include "i2s_private.h"
#include "esp_private/esp_clk_tree_common.h"
#include "clk_ctrl_os.h"
#include "esp_intr_alloc.h"
#include "esp_check.h"
@@ -85,6 +86,19 @@ static esp_err_t i2s_std_set_clock(i2s_chan_handle_t handle, const i2s_std_clk_c
/* Calculate clock parameters */
ESP_RETURN_ON_ERROR(i2s_std_calculate_clock(handle, clk_cfg, &clk_info), TAG, "clock calculate failed");
#if SOC_I2S_HW_VERSION_2
i2s_clock_src_t old_clk_src = handle->clk_src;
if (clk_cfg->clk_src != I2S_CLK_SRC_EXTERNAL)
#endif
{
i2s_clock_src_t clk_src = clk_cfg->clk_src;
#ifdef I2S_LL_DEFAULT_CLK_SRC
if (clk_src == I2S_CLK_SRC_DEFAULT) {
clk_src = I2S_LL_DEFAULT_CLK_SRC;
}
#endif
esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true);
}
hal_utils_clk_div_t ret_mclk_div = {};
portENTER_CRITICAL(&g_i2s.spinlock);
/* Set clock configurations in HAL*/
@@ -107,6 +121,12 @@ static esp_err_t i2s_std_set_clock(i2s_chan_handle_t handle, const i2s_std_clk_c
handle->curr_mclk_hz = handle->origin_mclk_hz;
handle->bclk_hz = clk_info.bclk;
#if SOC_I2S_HW_VERSION_2
if (old_clk_src != I2S_CLK_SRC_EXTERNAL) {
esp_clk_tree_enable_src((soc_module_clk_t)old_clk_src, false);
}
#endif
ESP_LOGD(TAG, "Clock division info: [sclk] %"PRIu32" Hz [mdiv] %"PRIu32" %"PRIu32"/%"PRIu32" [mclk] %"PRIu32" Hz [bdiv] %d [bclk] %"PRIu32" Hz",
clk_info.sclk, ret_mclk_div.integer, ret_mclk_div.numerator, ret_mclk_div.denominator, handle->origin_mclk_hz, clk_info.bclk_div, clk_info.bclk);
components/esp_driver_i2s/i2s_tdm.c
+21 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -20,6 +20,7 @@
#include "driver/gpio.h"
#include "driver/i2s_tdm.h"
#include "i2s_private.h"
#include "esp_private/esp_clk_tree_common.h"
#include "clk_ctrl_os.h"
#include "esp_intr_alloc.h"
#include "esp_check.h"
@@ -82,6 +83,19 @@ static esp_err_t i2s_tdm_set_clock(i2s_chan_handle_t handle, const i2s_tdm_clk_c
/* Calculate clock parameters */
ESP_RETURN_ON_ERROR(i2s_tdm_calculate_clock(handle, clk_cfg, &clk_info), TAG, "clock calculate failed");
#if SOC_I2S_HW_VERSION_2
i2s_clock_src_t old_clk_src = handle->clk_src;
if (clk_cfg->clk_src != I2S_CLK_SRC_EXTERNAL)
#endif
{
i2s_clock_src_t clk_src = clk_cfg->clk_src;
#ifdef I2S_LL_DEFAULT_CLK_SRC
if (clk_src == I2S_CLK_SRC_DEFAULT) {
clk_src = I2S_LL_DEFAULT_CLK_SRC;
}
#endif
esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true);
}
hal_utils_clk_div_t ret_mclk_div = {};
portENTER_CRITICAL(&g_i2s.spinlock);
/* Set clock configurations in HAL*/
@@ -104,6 +118,12 @@ static esp_err_t i2s_tdm_set_clock(i2s_chan_handle_t handle, const i2s_tdm_clk_c
handle->curr_mclk_hz = handle->origin_mclk_hz;
handle->bclk_hz = clk_info.bclk;
#if SOC_I2S_HW_VERSION_2
if (old_clk_src != I2S_CLK_SRC_EXTERNAL) {
esp_clk_tree_enable_src((soc_module_clk_t)old_clk_src, false);
}
#endif
ESP_LOGD(TAG, "Clock division info: [sclk] %"PRIu32" Hz [mdiv] %"PRIu32" %"PRIu32"/%"PRIu32" [mclk] %"PRIu32" Hz [bdiv] %d [bclk] %"PRIu32" Hz",
clk_info.sclk, ret_mclk_div.integer, ret_mclk_div.numerator, ret_mclk_div.denominator, handle->origin_mclk_hz, clk_info.bclk_div, clk_info.bclk);